60 results about "Microcode" patented technology

The invention discloses a tensor processing architecture based on reconfigurable calculation, a working mode of the tensor processing architecture and an FPGA (Field Programmable Gate Array) development board. The overall architecture comprises a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, an RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module and a result return network. The working modes of the overall architecture are divided into two modes: a CPU control mode and a cluster computing mode, wherein the CPU control mode is used for controlling global computing and output through a CPU during single-chip computing; the cluster calculation mode is used for being connected with an upper computer to cooperate with the upper computer to execute calculation tasks such as matrix calculation; the whole architecture is realized through an FPGA (Field Programmable Gate Array) development board, and the FPGA development board adopts Virtex UltraScale + VU13P as a main logic realization platform. Through the dynamic granularity configuration of the on-chip microcode, multiple operation modes can be realized, and the utilization rate of hardware is improved; and hardware realizes multiple configuration strategies, and the universality is high.

Examples of the present disclosure describe systems and methods for providing control of input, output, and processing of an AI model. In examples, a request to execute an AI model implemented by a client device is received, where the AI model is associated with one or more licenses that specify a protection level that is applied to one or more portions of the AI model during the AI model runtime. In response to the request, the AI model is translated to a first set of commands in an intermediate language. The first set of commands is translated into a second set of commands for a hardware device of the client device. The second set of commands is translated into microcode that is executable by the hardware device. The hardware device then executes the microcode to generate an output in furtherance of the request.

The embodiment of the invention provides a task execution method and device, a storage medium and a product. Relates to the technical field of computers. The method comprises the steps of obtaining a to-be-executed calculation task; task parameters of the calculation task are extracted, a microcode command meeting a preset microcode format is constructed according to the task parameters, and the preset microcode format is the format of a microcode set used by user equipment; and sending the microcode command to the user equipment, so that the user equipment starts execution of the calculation task by executing the microcode command under the condition of receiving the microcode command. According to the method, the problems that in the prior art, the effective calculation time proportion is reduced, and the real-time performance and the calculation power utilization rate of a heterogeneous calculation system are restricted can be solved.

The invention provides a parallel operation processor and electronic equipment. The parallel operation processor comprises a write-in control unit, a selector, N transmitting queues, N state machines and N pre-decoding units, the input end of the write-in control unit and the first input end of the selector are connected to the first register, the ith control end of the write-in control unit, the ith control end of the selector and the first input end of the ith pre-decoding unit are connected to the first end of the ith state machine, and the ith output end of the write-in control unit is connected to the input end of the ith transmitting queue; the output end of the ith transmitting queue is connected to the second input end of the selector, the output end of the selector is connected to the second register and the second input ends of the N pre-decoding units, and the output ends of the N pre-decoding units are connected to the second register; the N state machines and the N pre-decoding units are further connected with the decoding module, and the decoding module is further connected to the second register. N microcode instructions are executed in parallel, and the operation efficiency of the processor is improved.

The invention provides a processor and electronic equipment based on RISC-V. A pre-decoding module sends obtained N groups of pre-decoding information and a second target instruction to a second register; the decoding module reads information from the second register, sends corresponding source data to a third register according to a source register address in the pre-decoding information, decodes a read second target instruction to obtain N groups of decoding information, and sends the N groups of decoding information to the third register; and the back-end module executes the corresponding microcode instruction according to the N groups of decoding information and source data which are written in the third register recently. The first target instruction comprises at least two microcode instructions, so that a plurality of microcode instructions can be executed in each clock period, and the operation performance of the processor can be improved. Through the pre-decoding information, the source data is written into the third register in advance, so that the corresponding source data can be directly called when the microcode instruction is executed, and the running efficiency of the processor is improved.

The invention relates to the technical field of software security, and discloses an IDA microcode-based digital multimeter customized code obfuscator construction method and system, and the method comprises the steps: carrying out the obfuscation replacement of a measurement algorithm and a data processing method in a digital multimeter code based on an instruction replacement technology; confusing a control flow of the digital multimeter based on a false control flow technology, namely obtaining a calling relation of basic blocks to reconstruct an original program, and avoiding generation of an endless loop in a symbolic execution process through a method of assigning a value to an opaque predicate in advance; randomly modifying variable names, identifiers and function names of the sensitive data information of the digital multimeter based on a variable name confusion algorithm; and carrying out decompilation and code conversion on the obfuscation algorithm based on the IDA microcode, and constructing the digital multimeter customized code obfuscator based on the IDA microcode. The method can be integrated into the development environment of the digital multimeter, the safety protection level of the digital multimeter is improved, and the measurement data is prevented from being illegally stolen.

The invention discloses an internet of things security real-time monitoring and protection system, which carries out adversarial sample enhancement by introducing a generative adversarial network constrained by a physical rule so as to solve the problem of insufficient model training caused by scarcity of attack samples, and deeply mines long-time-sequence feature association of heterogeneous data in combination with time sequence stacking and a long-short-term memory network so as to realize real-time monitoring and protection of the internet of things security. Therefore, a closed-loop process from state sensing to threat research and judgment to precise blocking is realized. Through the mode, not only can the sensitivity and the recognition precision of scarce attack modes be remarkably improved and the false alarm rate be effectively reduced, but also microsecond-level real-time monitoring and precise blocking of a hardware level can be realized based on a microcode control instruction; therefore, high-reliability protection guarantee is provided for information physical safety of key infrastructures such as a novel electric power system and the like.

This invention relates to a method for verifying a memory device. The method includes verifying a second memory device based on one or more first microcode instructions stored in a predetermined portion of the verification of a first memory device to detect the operating state of the second memory device. Furthermore, the method includes receiving one or more second microcode instructions after verifying the second memory device. Finally, the first memory device is verified based on the one or more second microcode instructions stored in the second memory device to detect the operating state of the first memory device.

The invention discloses a hardware acceleration device and method for high-throughput lossless data compression, and relates to the field of integrated circuit design. The device comprises a front-end LZ77 compression module, a middle buffer module and a rear-end entropy coding module, wherein the front-end LZ77 compression module is configured to search and match input data; the intermediate buffer module is configured to realize decoupling of front and rear end processing time domains through an asynchronous symbol buffer; the back-end entropy coding module is configured to receive an output of the intermediate buffer module, construct a microcode packet intermediate representation containing codeword information, and parse the microcode packet to generate a serial compressed bit stream. According to the method, invalid memory reading and assembly line pause can be effectively eliminated, the throughput and the energy efficiency ratio of the hardware compressor are remarkably improved on the premise of not sacrificing the compression rate, and the method is suitable for unloading acceleration of a high-performance solid state disk controller, an intelligent network card and a cloud server.

The embodiment of the invention provides a solid state disk firmware damaged data recovery method and system. The method comprises the steps of performing information identification on a to-be-recovered solid state disk; if the hard disk information meeting the preset condition is not recognized, the hard disk is controlled to enter a preset safety mode; in a preset security mode, identifying a master control type and NAND particle information; based on the identified master control type and NAND particle information, selecting a matched target microcode from a preset firmware library; based on the target microcode, information identification is carried out again; if the hard disk information meeting the preset condition is recognized, configuring parameter information of the to-be-recovered solid state disk according to the hard disk information; and performing file system data recovery based on the NAND particle information and the parameter information. According to the method, the data recovery efficiency and the data integrity are improved.

The present invention discloses a tensor processing system based on reconfigurable computing, its working method, and an FPGA development board. The system includes: a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, a RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module, and a result return network. The system has two working methods: a CPU control method and a cluster computing method. The CPU control method is used to control global calculations and outputs through the CPU during single-chip computing; the cluster computing method is used to connect to a host computer and cooperate with the host computer to perform computing tasks such as matrix calculations. The system is implemented through an FPGA development board, and the FPGA development board uses Virtex UltraScale+VU13P as the main logic implementation platform. The present invention can realize multiple operation modes and improve hardware utilization through dynamic granularity configuration of on-chip microcode; the hardware implements multiple configuration strategies and is highly versatile.

The present invention provides a parallel computing processor and electronic device, comprising a write control unit, a selector, N transmit queues, N state machines, and N pre-decoding units. The input end of the write control unit and the first input end of the selector are connected to a first register. The i-th control end of the write control unit, the i-th control end of the selector, and the first input end of the i-th pre-decoding unit are connected to the first end of the i-th state machine. The i-th output end of the write control unit is connected to the input end of the i-th transmit queue, the output end of the i-th transmit queue is connected to the second input end of the selector, the output end of the selector is connected to a second register and the second input ends of the N pre-decoding units, and the output ends of the N pre-decoding units are connected to the second register. The N state machines and the N pre-decoding units are further connected to a decoding module, which is further connected to the second register. N microcode instructions are executed in parallel, thereby improving the operating efficiency of the processor.

The invention discloses a speculative fusion design structure supporting discontinuous microcodes. The speculative fusion design structure is composed of a fusion predictor, a microcode queue, a reservation station and a fusion historical queue. The invention further discloses a speculation fusion optimization method supporting the discontinuous microcodes, which comprises the following steps of: S1, accessing the fusion predictor, acquiring fusion information of the corresponding microcodes, and storing the hit corresponding microcodes and the fusion information carried by the microcodes into a microcode queue; s2, after the microcodes and fusion information carried by the microcodes are stored in a microcode queue, internal correlation check and deadlock check of the microcodes are carried out; and S3, checking the correctness of microcode fusion in a submission stage after microcode fusion. According to the method, effective detection can be carried out during non-continuous microcode fusion, the problem of execution conflicts generated after non-continuous microcode fusion is avoided, the confidence degree of the prediction path is dynamically monitored, and the prefetching range and the prefetching accuracy are both considered.

The invention provides a microcode generation method and system based on reinforcement learning, and relates to the technical field of data processing.The microcode generation method comprises the steps that a pre-trained reinforcement learning strategy model is adopted, a state feature vector represented in the middle of microcodes is extracted, action probability distribution is output, and a target action is selected based on the action probability distribution; according to the method and the system, the current micro-code intermediate representation is subjected to iterative updating, the model comprehensively balances the subsequent income in combination with the current state in the iterative updating process, and a better scheduling sequence can be gradually approached under the condition that the micro-operation dependency relationship and hardware resource competition coexist. Meanwhile, a better scheduling change operation is selected through iterative updating, so that unnecessary pauses and resource conflicts can be reduced, and the utilization efficiency of key execution resources is improved.

The invention provides a light formula compiling method based on a scene graph, a bridge end compiler, a medium and a system. The method comprises the following steps: acquiring a user scene demand, and converting the user scene demand into a directional and loop-free scene graph; based on the point-edge association relationship of the scene graph and a preset constraint condition, detecting conflicts of the scene segments, and resolving the conflicts according to a constraint priority; grouping all scene segments based on the point-edge association relationship of the scene graph, wherein the groups comprise parallel groups which can be started and executed at the same time and sequence groups which need to be executed in sequence; according to a time sequence, the operation of each parallel group and the operation of each sequence group are converted into corresponding microcode fragments, and each microcode fragment corresponds to one group of parallel operation or sequence operation; and compressing and proofreading the microcode fragment, and issuing the microcode fragment to a lamp terminal for execution. According to the method, conflicts such as power and parameters are eliminated in advance in the compiling period, and operation abnormity and potential safety hazards are avoided.

Provided are an accelerator, an acceleration method, and an electronic device. The accelerator includes: a calculating unit including a general operation logic performing an operation of different operation types in response to different inputs; an acquiring unit, configured to acquire a target microcode instruction generated according to a target type operation to be implemented; the target microcode instruction is used to indicate target input data required to enable the general operation logic to implement the target type operation; a parsing unit, configured to parse the target microcode instruction to obtain a parsing result corresponding to the target input data; and a controlling unit, configured to, in response to the parsing result, control the calculating unit to enable the calculating unit to acquire the target input data and run the general operation logic based on the target input data so as to complete the target type operation.

This application provides a scene graph-based light recipe compilation method, bridge compiler, medium, and system. The method includes: acquiring user scene requirements and converting them into a directional, loop-free scene graph; detecting conflicts in each scene segment based on the node-edge relationships and preset constraints of the scene graph and resolving these conflicts according to constraint priority; grouping all scene segments based on the node-edge relationships of the scene graph, the grouping including parallel groups that can be executed simultaneously and sequential groups that need to be executed in sequence; converting the operations of each parallel group and sequential group into corresponding microcode segments according to timing, wherein each microcode segment corresponds to a set of parallel or sequential operations; compressing and verifying the microcode segments before sending them to the lighting terminal for execution. This application resolves power and parameter conflicts in advance during compilation, avoiding operational anomalies and safety hazards.

The invention relates to the field of program dynamic analysis, and provides a hardware implementation-oriented multi-label data stream tracking method, which comprises the following steps of: dividing input data into a plurality of areas with fixed sizes, and distributing a unique label vector to each area; decoding an instruction actually executed by a program according to data operation semantics of the instruction, calculating a microcode sequence through predefined taint propagation according to an instruction decoding result, and performing taint propagation calculation on tag vectors of a source operand and a target operand to obtain tag vectors after taint propagation; reversely backtracking a taint area according to a bit set to 1 in a tag vector corresponding to the instruction operand by taking a specified position executed by a program as a starting point; label vector distribution and taint propagation calculation are changed as much as possible according to the size of the taint area until the target precision is achieved. The problem that dynamic taint analysis and calculation efficiency is low is solved, taint propagation efficiency is improved, and meanwhile more detailed dynamic precision adjustment is achieved.

The invention discloses a command transmission method and device, a processor, a system on chip, equipment and a medium, and belongs to the technical field of computers. The method comprises the steps of generating a microcode instruction through a central processing unit according to a task attribute of a processing task; the microcode instruction is composed of an operation code field, a microcode configuration field and an operand; the microcode instruction comprises an immediate microcode or a stream microcode; sending the microcode instruction to a microcode processor in a graphics processor through a central processing unit; the microcode processor is composed of logic units in the graphics processor; and analyzing the microcode instruction through the microcode processor, and distributing the processing task to an execution unit in the graphics processor. The problem that an existing instruction generation method is high in complexity can be solved.

The invention relates to the technical field of data processing, and discloses a dynamic switching Hash and symmetric cryptography hybrid hardware acceleration system, which comprises a unified state register; the reconfigurable unified calculation data path integrates calculation logics of different key path durations; a microcode configuration and control unit and self-adaptive time sequence constraint logic; the microcode configuration and control unit is configured to respond to a configuration state change and cooperatively generate a function reconstruction signal and a time sequence mode signal; the adaptive timing constraint logic sets execution path constraint of a data path according to the timing mode signal, dynamic cooperation is carried out on logic function configuration and physical timing constraint, the inherent static timing enumeration problem of logic folding is solved, a system clock can anchor a fastest task, a slow task is adaptive to a multi-cycle path, and the adaptive timing constraint logic is adaptive to a multi-cycle path. And the peak value processing performance is ensured while hardware multiplexing is realized.

This application relates to the field of shuttle control technology, specifically to a positioning and correction control method for precise docking of mother and daughter shuttles. The method includes: simultaneously laying a QR code reference at each docking station; connecting the incremental encoder pulses of the daughter shuttle's front axle drive motor to the external trigger port of a vision sensor, and obtaining coarse code and micro code readings respectively based on the encoder pulse triggers the vision sensor to capture the bottom view image; using the drift increment of the mother shuttle's body relative to the departure time as a state variable, calculating the drift difference observation by combining the pose calculation using micro code and coarse code matrix, calculating the real-time drift, and feeding it into the differential compensation loop for dynamic pose drift filtering and correction; upon entering the area covered by the conventional positioning QR code, determining the closing trigger signal and initiating the exit process, and archiving the drift sequence as a priori compensation value for the next docking. This method effectively improves the continuity and accuracy of positioning and correction during the gap crossing process.

The invention discloses a command address transmission method and device of an NAND flash memory, a controller and a solid state disk, and relates to the technical field of data storage, the method is applied to the NAND flash memory controller, and the method comprises the steps that when the NAND flash memory controller is in an SCA mode, a first preset signal in a microcode to be executed is detected; if the first preset signal is a head identifier, executing a head shift operation by using an RTL circuit, and transmitting head information corresponding to the microcode to be executed to NAND flash memory particles through a CA bus; if the first preset signal is a command address identifier, executing a command address shift operation by using an RTL circuit, and transmitting command address information corresponding to the microcode to be executed to NAND flash memory particles through a CA bus; according to the invention, the conversion operation of the CA bus in the SCA mode is transferred to the RTL circuit from the microcode, so that the number of microcodes required for transmitting each command or address is greatly reduced, the loading speed of the microcodes is improved, and the working efficiency of the NAND flash memory controller is improved.

The embodiment of the invention discloses an inter-particle short-range acting force cooperative calculation method and device, equipment and a medium. The method comprises the following steps: for any reference particle, storing reference particle information and to-be-screened particle information in a memory in the form of a data block; the hardware filter obtains the data blocks from the memory, and screens out screened particles from the to-be-screened particles according to the data blocks and a preset distance range when each data block is obtained; the hardware filter stores the particle information of the reference particles and the screened particles into a target address of a memory, and sends a calculation instruction to a vector processor based on the storage content in the address; and the vector processor determines the short-range acting force between the reference particle and each screened particle according to the calculation instruction and the acting force calculation microcode. On the basis, particle screening and acting force calculation are decoupled, screening while calculation is achieved through a memory, the calculation efficiency is improved, the number of particle pairs obtained after screening and calculation is reduced, the calculation efficiency is further improved, and consumption of calculation resources is reduced.

The embodiment of the invention provides a data processing method and device, a processor, computer equipment, a medium and a program, and the processor comprises a decoder which responds to a microcode of an elliptic curve cryptographic algorithm and decodes a plurality of instructions, and at least one part of the instructions are basic instructions; the logical operation unit comprises a basic instruction operation subunit used for operating the basic instruction; wherein part or all of the basic instruction is a modular operation instruction obtained by taking a prime number p as a modulus. According to the embodiment of the invention, the complexity and deployment cost of hardware operation can be remarkably reduced.

Embodiments of the present application relate to the field of fault detection, and provide a processor fault detection method and apparatus, a device, a medium, and a product. The method is applied to a basic input / output system of a server, and comprises: in a power-on self-test stage of a basic input / output system, reading a processor type and processor microcode; when the processor type is inconsistent with a preset type, or when the processor microcode is not read, or when the processor microcode fails to be loaded, determining that a processor is faulty, reporting error information corresponding to the described problem to a baseboard management controller of a server, and displaying an error information result by means of a screen, or parsing the result by means of the baseboard management controller of the server. By means of the method, when a processor fault occurs, the problem of the processor fault can be efficiently and quickly detected, and a detection result displayed to a user, thereby not only improving work efficiency, but also improving the use experience of the user.

The invention belongs to the technical field of cryptographic algorithm hardware implementation, and particularly discloses a post quantum cryptographic algorithm acceleration method and device based on an ASIP architecture, and the method comprises the steps: obtaining a program code of a Kyber algorithm; continuously executing the microcode instruction of the Kyber algorithm until the Kyber algorithm is completely executed; executing the microcode instruction of the Kyber algorithm, wherein the microcode instruction to be executed is obtained; analyzing the microcode instruction to be executed to obtain instruction analysis information; acquiring data of a source operand address as source data; on the basis of the operation code, an operation object is determined in hardware resources, input of the operation object is configured on the basis of the source data, and the hardware resources comprise an ALU and a Hash and sampling module; and configuring the data of the target operand address based on the data output by the operation object. According to the method and the device, the operation efficiency of the Kyber algorithm can be improved through hardware acceleration.

The invention discloses a power business operation method and device and a storage medium, and the method comprises the steps: carrying out the instantiation of a node corresponding to a hardware carrier according to the feature information of a message, and obtaining a hardware microcode instruction; in the process of executing the hardware microcode instruction, if a control logic relationship exists between the node corresponding to the hardware carrier and the node corresponding to the software carrier, generating a software microcode instruction for the node corresponding to the software carrier; and executing the remaining hardware microcode instructions and the generated software microcode instructions according to the control logic relationship so as to complete business operation under the power business. The execution sequence and the incidence relation of the hardware microcode instruction and the software microcode instruction are determined through the control logic relation, the execution logic of the hardware microcode instruction and the software microcode instruction is standardized, disordered task execution of software and hardware is avoided, cooperative promotion of hardware execution and software execution is achieved, and the software and hardware coordination of a power system is improved. The smooth completion of business operation under the power business is ensured, and the stable operation of the power system is further ensured.

The invention discloses a self-evolution computing system and a self-evolution computing method, which realize millisecond-level online optimization and minute-level continuous evolution through a sensing-diagnosis-decision-execution-control five-layer closed-loop architecture (as shown in attached drawings of the abstract). The system has causal diagnosis, strategy self-learning and microcode level reconfiguration capabilities, the actually measured energy consumption is reduced by more than or equal to 18%, the delay is reduced by more than or equal to 25%, the decision process is completely explained, the maintenance cost of the system is remarkably reduced, and the comprehensive performance is improved.

There is provided a data processing system configured to perform data processing of a data flow application. The data processing system includes a control processor having access to memory. The data processing system further includes a plurality of programmable Processing Elements, PEs, organized in multiple clusters. Each cluster comprises a multitude of the programmable PEs, the functionality of each programmable Processing Element being defined by internal microcode in a microprogram memory associated with the Processing Element. The multiple clusters of programmable Processing Elements are arranged in a Network on Chip, NoC, connected to the control processor, which is provided as a central hub, i.e. a root, for the Network on Chip, and the multiple clusters of programmable Processing Elements being arranged at peripheral nodes, also being referred to as cluster nodes, of the Network on Chip.

A Network on Chip, NoC, processing system configured to perform data processing. The NoC processing system is configured for interconnection with a control processor connectable to said NoC processing system. The NoC processing system comprises a plurality of microcode-programmable Processing Elements, PEs, organized in multiple clusters, each cluster comprising a multitude of said programmable PEs, the functionality of each microcode-programmable PE being defined by internal microcode in a microprogram memory associated with the PE. The clusters of programmable PE are arranged on a Network on Chip, NoC, the NoC having a root and a plurality of peripheral nodes, wherein the clusters of PE are arranged at peripheral nodes of the NoC, and the NoC is connectable to the control processor. Each cluster further includes a Cluster Controller, CC, and an associated Cluster Memory, CM, shared by the multitude of programmable PE within the cluster.