9 results about "Microcode" patented technology

This invention relates to a method for verifying a memory device. The method includes verifying a second memory device based on one or more first microcode instructions stored in a predetermined portion of the verification of a first memory device to detect the operating state of the second memory device. Furthermore, the method includes receiving one or more second microcode instructions after verifying the second memory device. Finally, the first memory device is verified based on the one or more second microcode instructions stored in the second memory device to detect the operating state of the first memory device.

This application provides a scene graph-based light recipe compilation method, bridge compiler, medium, and system. The method includes: acquiring user scene requirements and converting them into a directional, loop-free scene graph; detecting conflicts in each scene segment based on the node-edge relationships and preset constraints of the scene graph and resolving these conflicts according to constraint priority; grouping all scene segments based on the node-edge relationships of the scene graph, the grouping including parallel groups that can be executed simultaneously and sequential groups that need to be executed in sequence; converting the operations of each parallel group and sequential group into corresponding microcode segments according to timing, wherein each microcode segment corresponds to a set of parallel or sequential operations; compressing and verifying the microcode segments before sending them to the lighting terminal for execution. This application resolves power and parameter conflicts in advance during compilation, avoiding operational anomalies and safety hazards.

This application relates to the field of shuttle control technology, specifically to a positioning and correction control method for precise docking of mother and daughter shuttles. The method includes: simultaneously laying a QR code reference at each docking station; connecting the incremental encoder pulses of the daughter shuttle's front axle drive motor to the external trigger port of a vision sensor, and obtaining coarse code and micro code readings respectively based on the encoder pulse triggers the vision sensor to capture the bottom view image; using the drift increment of the mother shuttle's body relative to the departure time as a state variable, calculating the drift difference observation by combining the pose calculation using micro code and coarse code matrix, calculating the real-time drift, and feeding it into the differential compensation loop for dynamic pose drift filtering and correction; upon entering the area covered by the conventional positioning QR code, determining the closing trigger signal and initiating the exit process, and archiving the drift sequence as a priori compensation value for the next docking. This method effectively improves the continuity and accuracy of positioning and correction during the gap crossing process.

The application discloses a hardware-level AI implicit operation link blockade and offline communication global detection system and belongs to the technical field of hardware bottom-layer security protection. The application adopts a hardware-level global scanning and physical blocking core architecture, supports various compatible implementation modes such as external scanning, chip microcode auditing, electromagnetic monitoring and power consumption monitoring and is fully compatible with various existing basic protection systems. The application fills the bottom-layer control blank of the traditional protection system through bottom-layer hardware state global scanning, multi-dimensional feature recognition and secret communication physical blocking, is suitable for various bottom-layer security reinforcement technical evolution scenes and is suitable for the bottom-layer security reinforcement of various offline intelligent devices and edge AI terminals.

The present disclosure provides a microcode splitting method and device of RVV instructions, electronic equipment and storage medium, by further introducing a sub-MOP splitting mechanism on the basis of ordinary MOP splitting, a single MOP corresponding to a special vector instruction is further split into multiple sequentially executed sub-MOPs, so that the execution unit can gradually complete the target operation by using the intermediate results generated by the previous sub-MOP, thereby realizing the execution of the special vector instruction without greatly modifying the existing execution unit structure. Thus, the hardware modification cost can be effectively reduced, the reuse degree of the existing vector microarchitecture can be improved, the register port pressure can be reduced, and the compatibility and engineering implementation feasibility of the processor for special RISC-V vector instructions can be improved.

A kind of coprocessor and operation system for implementing elliptic curve cryptography algorithm, the coprocessor includes instruction memory and multiple microcode type coprocessor cores, instruction memory is used to store instruction flow written according to preset instruction set, and the instruction set is the set of instructions that microcode type coprocessor core can identify and execute;Multiple microcode type coprocessor cores are used to obtain instruction flow, and the mathematical operation required by elliptic curve cryptography algorithm is executed in parallel according to the instruction in instruction flow.This application can be written according to the algorithm needs instruction flow, improve the algorithm flexibility;Multiple microcode type coprocessor cores parallel operation, improve the algorithm performance.

This application relates to the field of chip register event processing technology, and discloses a firmware parallel event processing method based on a programmable microcode coprocessor. The method includes the firmware establishing a register semantic table, a version table, and an access token table in shared memory, and writing a task descriptor to the coprocessor. The coprocessor determines the target register based on the task descriptor, acquires an access token and performs a real read when controlled sampling is required, forming a mirror record; subsequently, a write intent is generated based on the mirror record, and conflict detection is performed using the version number and the current register value before submission. If the conditions are met, a bit-level write-back is performed and the version table is updated; otherwise, resampling, partial commit, or reporting processing is performed. This method improves the consistency and reliability of register operations in parallel access scenarios.

This invention discloses a low-instruction-overhead, reconfigurable normalization operator implementation method based on SIMD vector processing, relating to deep learning algorithm model technology and electronic information technology. The invention first divides the normalization operator into reduction and scalar operations, compiles the operations into a fixed sequence of M microcodes, preloads them into a microcode sequence memory, and configures a SIMD vector processing unit consisting of an instruction decoding unit, a hardware autonomous execution engine, and a memory access address generator. It continuously performs sequence length token and channel group scanning, performing P×N iterations on P groups of channels and N tokens, physically reusing the microcode sequence. The microcode pointer is automatically reset to zero, and intermediate result fusion is adaptively completed by scalar microcode operator encoding. Compared with existing GPU solutions, this method has better reconfigurability, lower execution cycle, and lower instruction overhead.