Apparatus and method for using checking instructions in a floating-point execution unit
a floating-point execution unit and instruction technology, applied in the field of microprocessors, can solve the problems of reducing the amount of constant rom storage required, requiring additional microprocessor resources, and producing undesirable execution latencies
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Turning now to FIG. 3, a block diagram of one embodiment of a microprocessor 10 is shown. Microprocessor 10 includes a prefetch / predecode unit 12, a branch prediction unit 14, an instruction cache 16, an instruction alignment unit 18, a plurality of decode units 20A-20C, a plurality of reservation stations 22A-22C, a plurality of functional units 24A-24C, a load / store unit 26, a data cache 28, a register file 30, a reorder buffer 32, an MROM unit 34, and a floating-point unit (FPU) 36, which in turn comprises multiplier 50. Note that elements referred to herein with a particular reference number followed by a letter may be collectively referred to by the reference number alone. For example, decode units 20A-20C may be collectively referred to as decode units 20.
Prefetch / predecode unit 12 is coupled to receive instructions from a main memory subsystem (not shown), and is further coupled to instruction cache 16 and branch prediction unit 14. Similarly, branch prediction unit 14 is cou...
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