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Apparatus and method for using checking instructions in a floating-point execution unit

a floating-point execution unit and instruction technology, applied in the field of microprocessors, can solve the problems of reducing the amount of constant rom storage required, requiring additional microprocessor resources, and producing undesirable execution latencies

Inactive Publication Date: 2001-06-12
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Detecting and handling special and exceptional cases, however, generally requires additional microprocessor resources and produces undesirable execution latencies.
Furthermore, checking instructions may reduce the amount of constant ROM storage required to hold the possible results of special and exceptional cases.

Method used

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  • Apparatus and method for using checking instructions in a floating-point execution unit
  • Apparatus and method for using checking instructions in a floating-point execution unit
  • Apparatus and method for using checking instructions in a floating-point execution unit

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Embodiment Construction

Turning now to FIG. 3, a block diagram of one embodiment of a microprocessor 10 is shown. Microprocessor 10 includes a prefetch / predecode unit 12, a branch prediction unit 14, an instruction cache 16, an instruction alignment unit 18, a plurality of decode units 20A-20C, a plurality of reservation stations 22A-22C, a plurality of functional units 24A-24C, a load / store unit 26, a data cache 28, a register file 30, a reorder buffer 32, an MROM unit 34, and a floating-point unit (FPU) 36, which in turn comprises multiplier 50. Note that elements referred to herein with a particular reference number followed by a letter may be collectively referred to by the reference number alone. For example, decode units 20A-20C may be collectively referred to as decode units 20.

Prefetch / predecode unit 12 is coupled to receive instructions from a main memory subsystem (not shown), and is further coupled to instruction cache 16 and branch prediction unit 14. Similarly, branch prediction unit 14 is cou...

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PUM

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Abstract

The use of checking instructions to detect special and exceptional cases of a defined data format in a microprocessor is disclosed. Generally speaking, a checking instruction is included with the microcode of floating-point instructions to detect special and exceptional cases of operand values for the floating-point instructions. A checking instruction is configured to set one or more flags in a flags register if it detects a special or exceptional case for an operand value. A checking instruction may also set the result or results of a floating-point instruction to a result value if a special or exceptional case is detected. In addition, a checking instruction may be configured to set one or more bits in status register if a special or exceptional case is detected. After a checking instruction completes execution, a subsequent microcode instruction can be executed to determine if one or more flags were set by the checking instruction. If one or more flags have been set by the checking instruction, the subsequent microcode instruction can branch to a non-sequential microcode instruction to handle the special or exceptional case detected by the checking instruction.

Description

1. Field of the InventionThis invention relates generally to the field of microprocessors and, more particularly, to floating-point execution units within microprocessors.2. Description of the Related ArtMicroprocessors are typically designed with a number of "execution units" that are each optimized to perform a particular set of functions or instructions. For example, one or more execution units within a microprocessor may be optimized to perform memory accesses, i.e., load and store operations. Other execution units may be optimized to perform general arithmetic and logic functions, e.g., shifts and compares. Many microprocessors also have specialized execution units configured to perform more complex floating-point arithmetic operations including multiplication and reciprocal operations. These specialized execution units typically comprise hardware that is optimized to perform one or more floating-point arithmetic functions.Most microprocessors must support multiple data types. ...

Claims

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Application Information

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IPC IPC(8): G06F9/302G06F9/318G06F9/22
CPCG06F9/226G06F9/30192G06F9/30014
Inventor JUFFA, NORBERT
Owner ADVANCED MICRO DEVICES INC
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