27results about "Microinstruction function" patented technology

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.

The invention provides an interface for a counting or timing function of flight control software and an implementation method of the interface, and belongs to the technical field of flight control software. According to the method, a unified counter function is defined and comprises a counting array and a small frame number array which can be used by a plurality of counters, the counting array and the small frame number array are packaged, and the counting or timing function of the flight control software is obtained; when a new counter is added, a new global variable does not need to be defined, only a static subscript variable needs to be defined at the code position of the counter needing to be used in the flight control software to indicate elements in a counting array corresponding to the currently used counter, the address of the static subscript variable is transmitted to a counter function through a formal parameter, and then the counter function is added. In this way, counting accumulation or zero clearing can be automatically achieved when a counter function is called, and coupling use of counters is avoided. Due to the fact that the counting function of the counter function is achieved through the internal static counting array, and the counting array is packaged in the counter function, the risk that the counter is tampered by the outside is avoided to the maximum extent.

A vector processing unit contains an operation cache and a separate micro-op cache. The operation cache tracks state and logic of instructions, and is responsible for splitting instructions into micro-ops. The micro-op cache tracks state and logic of micro-ops. Having a separate micro-op cache provides power and area benefits, as well as allowing instructions to be split out of order.

A system-integrated solution for input / output device extended-control without operating system driver involvement is provided. In examples, systems and methods include receiving an out-of-band request from a human interface device, receiving an in-band request from the human interface device, and sending a signal directly to a peripheral device, via a micro-control unit, to honor the out-of-band request. In examples, the out-of-band request is received via an inter-integrated circuit.

Embodiments include systems and methods for processing sensor data and generating operational instructions of hardware of egos (e.g., autonomous vehicles, robots). The ego includes any number of machine-learning architectures, often neural network architectures, for processing sensor data and recognizing the environment around the ego and making decisions on the ego's behavior. The neural network architectures of the ego ingest sensor data and execute any number of operations related to a particular domain or task, such as object recognition or path planning, using the sensor data. A graph partitioner is trained to assign functions in the software of the neural networks and the sensor data to certain hardware processing units. Several compilers are used to generate the instructions based upon the assigned type of processing unit.

A multi-purpose programmable input / output (I / O) circuit is disclosed. The programmable I / O circuit includes a microcontroller and an interface circuit communicatively coupled to each other. The interface circuit comprises an input circuit, a pull-up circuit, a pull-down circuit and a measurement circuit. The microcontroller is configured to generate a first input signal and a second input signal provided to the input, and is further configured to receive a measurement signal on a measurement input. In response to a setting of the first input signal, the input circuit activates the pull-up circuit to generate a pull-up voltage on the output pin of the interface circuit. In response to a setting of the second input signal, the input circuit activates the pull-down circuit to generate a pull-down voltage on the output pin. The microcontroller may also measure a value of an electrical parameter (e.g., current or voltage) based on a measurement signal received from the measurement circuit.

The present invention relates to the field of instruction scheduling of DSP, and discloses an adaptive weighted greedy instruction scheduling system and method for DSP, wherein the system comprises a ready instruction queue input module, a greedy scoring decision module, an adaptive weight adjustment module, a scheduling queue generation module, a scheduling termination check module, a ready queue update module, and a post-scheduling instruction queue output module. The system and method disclosed by the present invention comprehensively consider factors such as instruction delay, register pressure, and critical path, introduce an adaptive weight dynamic adjustment mechanism, weigh multi-objective optimization on the basis of a greedy strategy, can flexibly adapt to different program characteristics, efficiently utilize hardware resources, improve scheduling quality in complex scenarios, and improve overall program performance. At the same time, the algorithm is improved on the basis of the original algorithm, reuses a large part of the content, has moderate complexity, is easy to implement and integrate in a compiler, and has strong practicality and engineering value.

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.

Methods and systems for debugging microservices in a containerized service-based application are disclosed. The method may include obtaining a request to establish a communication pipeline between a microservice subject to debugging and a replicated instance of the microservice hosted by a debugging system. To establish a communication pipeline, a portion of traffic may be intercepted and redirected based on the request. The communication pipeline and the replicated instance of the microservice may allow the debugging system to extract information from the microservice relevant to debugging and correct an undesired operation of the microservice.

Disclosed herein are methods and systems for using artificial intelligence modeling techniques to train and execute an artificial intelligence model to analyze camera feed received from an ego to predict surface data for various surfaces surrounding the ego. A method comprises inputting, using one or more cameras of an ego object, image data of a space around the ego object into an artificial intelligence model; predicting, by executing the artificial intelligence model, a surface attribute of one or more surfaces of the space around the ego object; and generating a dataset based on the one or more surfaces and their corresponding surface attribute.

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.

Systems and methods are provided for configuring publication / subscription (pub / sub) system to perform alternative pub / sub tasks. According to one implementation, a publisher operating within a pub / sub system includes multiple modules arranged in a tree structure. A subscriber interface is arranged at a top root of the tree structure, wherein the subscriber interface is configured for communicating with one or more subscribers. Each module of a first group of the modules includes a microservice. Each module of a second group of the modules, located above a lowest level of the tree structure, acts as an intermediary pub / sub proxy module. Also, each module of the first group is configured to self-publish a telemetry message by capturing a metric and pushing the metric upward through one or more intermediary pub / sub proxy modules to the subscriber interface for publication to the one or more subscribers.

The present disclosure provides an instruction transmitting unit, an instruction executing unit, related devices and methods. The instruction transmitting unit comprises: an instruction splitter configured to split a vector instruction to be executed into micro-instructions; a micro-instruction index obtainer configured to obtain an effective element number index of the micro-instruction based on an element range involved by the split micro-instruction; an index comparison subunit configured to compare the obtained effective element number index with a first index, the first index being an effective element number index of a fault-only-first micro-instruction which has not been processed completely; and a micro-instruction transmitting controller configured to transmit the split micro-instruction to a vector executing unit for execution in a case where the effective element number index is smaller than the first index. The present disclosure improves the running efficiency of subsequent vector instructions when a fault-only-first vector load instruction is involved in chain execution.

The present disclosure includes apparatuses and methods related to microcode instructions indicating instruction types. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.

The present disclosure provides a packet modification method and apparatus, a computer device, and a storage medium. The method includes: dividing a field to be modified that is related to packet encapsulation information into M containers; performing instruction extraction on a very long instruction word executing a modification command, to obtain N groups of initial instructions, where 2≤N≤M; processing the N groups of initial instructions to obtain N groups of source operands and N groups of modification field configuration information; determining, according to the N groups of modification field configuration information, N containers matched with the N groups of source operands, respectively; and modifying, according to the N groups of source operands, the N matched containers, respectively.

A multi-programmable input / output (I / O) circuit is disclosed. A programmable I / O circuit includes a microcontroller and an interface circuit communicatively coupled to one another. The interface circuit includes an input circuit, a pull-up circuit, a pull-down circuit, and a measurement circuit. The microcontroller is configured to generate first and second input signals that are provided to the input, and further configured to receive, on a measurement input, the measurement signal. In response to assertion of the first input signal, the input circuit activates the pull-up circuit to generate a pull-up voltage on an output pin of the interface circuit. In response to assertion of the second input signal, the input circuit activates the pull-down circuit to generate a pull-down voltage on the output pin. The microcontroller may also measure the value of an electrical parameter (e.g., a current or a voltage) based on the measurement signal received from the measurement circuit.

To visualize graphics functions in a host computer emulating a target system.SOLUTION: A host computer 200 includes a memory 208, a CPU 202, and a GPU 206. The memory 208 stores a library 218 of graphics functions, and a VM 216. The VM 216: executes a target code 124 configured to operate on a target system; intercepts a graphics function call in the target code 124; and redirects the graphics function call to a corresponding graphics function in the library 218 of the graphics functions stored in the memory 208. The GPU 206 executes the corresponding graphics function, for determining at least one feature to be rendered in a display 212.SELECTED DRAWING: Figure 2

The present disclosure includes apparatuses and methods related to microcode instructions indicating instruction types. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.

The invention belongs to the field of basic electronic circuits. Belongs to the field of digital signal processors for streaming audio applications, audio reproduction signal paths comprising digital signal processors (DSPs) for streaming, integrated circuits comprising the digital signal processors, and devices comprising the digital signal processors or the integrated circuits.

Vector instructions are processed in a vector processing unit VPU 101 with an operation cache OC 102 and a separate micro-op cache uOC 103. The OC receives an instruction to be processed and stores as

A host computer for emulating a target system includes a host memory, a CPU, and a host GPU. The host memory is configured to store a library of graphics functions and a VM. The VM includes a section of emulated memory storing target code configured to execute on the target system. The CPU is configured to execute the VM to emulate the target system. The VM is configured to execute the target code and intercept a graphics function call in the target code. The VM is further configured to redirect the graphics function call to a corresponding graphics function in the library of graphics functions stored in the host memory. The host GPU is configured to execute the corresponding graphics function to determine at least one feature configured to be rendered on a display coupled to the host GPU.

An instruction execution circuit operable to reduce two or more micro-operations into one by producing multiple permutation and merge results in one execution cycle. The execution circuit includes a permutation and merge switching fabric and a bank of multiplexers. For a fetched instruction, a decoder decodes an opcode to generate a set of control indications used to control the multiplexers to select bytes from the respective inputs that are destined for each of the multiple results. In this manner, multiple permutation results can be output from the execution circuits in one micro-operation.

The application provides an interface for flight control software counting or timing function and an implementation method thereof, and belongs to the technical field of flight control software. The method defines a unified counter function, which includes a counting array and a small frame number array that can be used by multiple counters, and encapsulates the counting array and the small frame number array. When a new counter is added, a new global variable does not need to be defined. A static subscript variable is only needed to be defined at a code position where the counter is needed in the flight control software, and the static subscript variable is used to indicate an element in a counting array corresponding to the currently used counter. The address of the static subscript variable is transmitted to the counter function through a parameter. When the counter function is called, the accumulation or zero clearing of the counting is automatically implemented, and the coupled use of the counter is avoided. Since the counter function implements the counting function through the internal static counting array, the counting array is encapsulated in the counter function, and the risk of external tampering of the counter is maximally avoided.

A system-integrated solution for input / output device extended-control without operating system driver involvement is provided. In examples, systems and methods include receiving an out-of-band request from a human interface device, receiving an in-band request from the human interface device, and sending a signal directly to a peripheral device, via a micro-control unit, to honor the out-of-band request. In examples, the out-of-band request is received via an inter-integrated circuit.

The present invention is in the field of basic electronic circuitry, in particular of a digital signal processor for streaming audio applications, an audio reproduction signal path comprising the Digital Signal Processor (DSP) for streaming, an integrated circuit comprising said digital signal processor, and a device comprising said digital signal processor or said integrated circuit.

Deployments of microservices executing in a cloud are automatically managed. Some microservices are deployed on dedicated nodes, others in serverless configurations. Rates of invocation and runtime data of microservices are monitored. Responsive to the monitored rate of invocation of a microservice running serverless exceeding a given threshold, the microservice is automatically redeployed to a dedicated node. A microservice executing on a dedicated node may be redeployed serverless if the infrequency with which it is called is sufficient. Microservices can be automatically redeployed between different dedicated nodes with different capacities based on monitored usage. The underlying cloud service provider may be automatically monitored for changes in serverless support functionality. Responsive to these changes, the thresholds at which microservices are redeployed can be automatically adjusted. Microservices may also be redeployed, and thresholds adjusted, in response to serverless microservice failures resulting from insufficient support provided by the underlying cloud service provider.