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10results about "Microinstruction function" patented technology

Processing Instructions

PendingUS20260111227A1Instruction analysisMicroinstruction functionProcessing InstructionMicro-operation
A vector processing unit contains an operation cache and a separate micro-op cache. The operation cache tracks state and logic of instructions, and is responsible for splitting instructions into micro-ops. The micro-op cache tracks state and logic of micro-ops. Having a separate micro-op cache provides power and area benefits, as well as allowing instructions to be split out of order.
Owner:IMAGINATION TECH LTD

Ai inference compiler and runtime tool chain

PendingUS20260104893A1Image enhancementImage analysis
Embodiments include systems and methods for processing sensor data and generating operational instructions of hardware of egos (e.g., autonomous vehicles, robots). The ego includes any number of machine-learning architectures, often neural network architectures, for processing sensor data and recognizing the environment around the ego and making decisions on the ego's behavior. The neural network architectures of the ego ingest sensor data and execute any number of operations related to a particular domain or task, such as object recognition or path planning, using the sensor data. A graph partitioner is trained to assign functions in the software of the neural networks and the sensor data to certain hardware processing units. Several compilers are used to generate the instructions based upon the assigned type of processing unit.
Owner:TESLA INC

Enabling high-performance scalable matrix extension (SME) instruction issue in processor devices

PCT designated stageWO2026064057A1Register arrangementsConcurrent instruction executionMicro-operationReservation station
Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.
Owner:QUALCOMM INC

Artificial intelligence modeling techniques for vision-based surface determination

Disclosed herein are methods and systems for using artificial intelligence modeling techniques to train and execute an artificial intelligence model to analyze camera feed received from an ego to predict surface data for various surfaces surrounding the ego. A method comprises inputting, using one or more cameras of an ego object, image data of a space around the ego object into an artificial intelligence model; predicting, by executing the artificial intelligence model, a surface attribute of one or more surfaces of the space around the ego object; and generating a dataset based on the one or more surfaces and their corresponding surface attribute.
Owner:TESLA INC

Enabling high-performance scalable matrix extension (SME) instruction issue in processor devices

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.
Owner:QUALCOMM INC

Configuring publication / subscription proxies in a microservice architecture

PendingUS20260064412A1Microinstruction functionComputer networkEngineering
Systems and methods are provided for configuring publication / subscription (pub / sub) system to perform alternative pub / sub tasks. According to one implementation, a publisher operating within a pub / sub system includes multiple modules arranged in a tree structure. A subscriber interface is arranged at a top root of the tree structure, wherein the subscriber interface is configured for communicating with one or more subscribers. Each module of a first group of the modules includes a microservice. Each module of a second group of the modules, located above a lowest level of the tree structure, acts as an intermediary pub / sub proxy module. Also, each module of the first group is configured to self-publish a telemetry message by capturing a metric and pushing the metric upward through one or more intermediary pub / sub proxy modules to the subscriber interface for publication to the one or more subscribers.
Owner:CIENA CORP

Instruction transmitting unit, instruction executing unit, related apparatus and method

ActiveCN114428638BInstruction analysisMicroinstruction functionComputer architectureLoad instruction
The present disclosure provides an instruction transmitting unit, an instruction executing unit, related devices and methods. The instruction transmitting unit comprises: an instruction splitter configured to split a vector instruction to be executed into micro-instructions; a micro-instruction index obtainer configured to obtain an effective element number index of the micro-instruction based on an element range involved by the split micro-instruction; an index comparison subunit configured to compare the obtained effective element number index with a first index, the first index being an effective element number index of a fault-only-first micro-instruction which has not been processed completely; and a micro-instruction transmitting controller configured to transmit the split micro-instruction to a vector executing unit for execution in a case where the effective element number index is smaller than the first index. The present disclosure improves the running efficiency of subsequent vector instructions when a fault-only-first vector load instruction is involved in chain execution.
Owner:C SKY MICROSYST CO LTD

Processing instructions

Vector instructions are processed in a vector processing unit VPU 101 with an operation cache OC 102 and a separate micro-op cache uOC 103. The OC receives an instruction to be processed and stores as
Owner:IMAGINATION TECH LTD

Virtual machine for virtualizing graphics functions

A host computer for emulating a target system includes a host memory, a CPU, and a host GPU. The host memory is configured to store a library of graphics functions and a VM. The VM includes a section of emulated memory storing target code configured to execute on the target system. The CPU is configured to execute the VM to emulate the target system. The VM is configured to execute the target code and intercept a graphics function call in the target code. The VM is further configured to redirect the graphics function call to a corresponding graphics function in the library of graphics functions stored in the host memory. The host GPU is configured to execute the corresponding graphics function to determine at least one feature configured to be rendered on a display coupled to the host GPU.
Owner:THE BOEING CO