Multi-issue processor system and method

Abstract

The invention provides a multi-issue processor system and method. When the multi-issue processor system and method is applied to the field of processors, before a processor core executes an instruction, the instruction is filled into a high speed memory which can be directly accessed by the processor core to achieve an extremely high cache hit rate. According to the technical scheme of the invention, for the multi-issue processor system which needs to carry out instruction transformation, the repeated transformation of an instruction address can be avoided, and the performance of the multi-issue processor is improved.

Description

technical field [0001] The invention relates to the fields of computer, communication and integrated circuit. Background technique [0002] The most advanced processors use multi-issue (multi-issue) technology to improve the performance of the processor. The front end of a multi-issue processor can provide multiple instructions to the processor core in one clock cycle. The multi-issue front-end includes an instruction memory with sufficient bandwidth to provide multiple instructions in one clock cycle, and the instruction pointer (IP) can move to the next location at a time. The front end of a multi-issue processor can handle fixed-length instructions efficiently, but the situation is more complicated when it handles variable-length instructions. A better solution is to convert the variable-length instruction into a fixed-length micro-operation (micro-op), and then send it to the execution unit from the front end. At this time, since the length of the instruction is varia...

AI Technical Summary

Problems solved by technology

[0004] The disadvantage of the above technique is that each instruction block in the L1 cache may correspond to multiple program entry points, and each program entry point will occupy one way in the tag unit 13 and the micro-operation cache 14, so that the tag unit 13 and the micro-operation cache 14 Content in micro-op cache 14 is too fragmented

This cache organization method causes duplicate storage of micro-operation tags in the tag unit 13, and also brings a dilemma

If the block capacity of micro-operation cache 14 is increased, the same micro-operation corresponding to the same instruction will be repeatedly stored in different blocks; if the block capacity of micro-operation cache 14 is reduced, more serious fragmentation will be caused

These disadvantages make the current processor using the above technology, the capacity of its micro-operation cache is smaller than that of the first-level cache, and there are repeated stored micro-operations in the micro-operation cache, which further reduces the effective capacity.

causing its cache miss rate to be generally greater than about 20%

The high micro-operation cache miss rate, the long delay caused by the instruction conversion during the miss, and the repeated conversion of the instruction are the reasons for the high power consumption and low efficiency of this type of processor.

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