8238results about "Memory adressing/allocation/relocation" patented technology

The invention discloses a big data stream-oriented memory cache storage system, relates to the technical field of memory cache storage, and is used for solving the problem of poor memory cache storage management. According to the method, the access frequency, the timeliness and the service importance of the data are evaluated, the priority ranking model is constructed, the cache strategy is optimized based on the ranking result, the data storage and scheduling efficiency is improved, the write-in and read operation of the memory cache is adjusted in real time in combination with the flow prediction model, memory overload is effectively avoided, and the data storage and scheduling efficiency is improved. According to the method, non-emergency data writing is delayed by adopting a delayed writing and lazy loading strategy, data is loaded as required, meanwhile, a cache elimination mechanism is designed according to data priority, access frequency, survival time and size, data migration is carried out when a cache space is insufficient, reasonable resource allocation is ensured, and through a multi-level and dynamic cache management scheme, the cache management efficiency is improved. Therefore, the system performance, the resource utilization rate and the response speed are remarkably improved, the data processing efficiency is optimized, and cache conflicts are reduced.

Embodiments are directed to a file system that include object stores. An object store for write requests may be provided. Write ahead log (WAL) entries that include data blocks may be generated. A WAL object may be generated based on the WAL entries and stored in the object store. An in-memory overlay may be updated to associate the data blocks with the WAL object. A checkpoint operation may be executed to: generate an index object that includes index entries that associate other data blocks with data objects stored in the object store; update the index object to include index entries that associate the data blocks with the WAL object; store the updated index object in the object store; update the in-memory overlay to remove the association of the data blocks and the WAL object and update the in memory WAL to remove records of successfully checkpointed WAL objects.

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

A key-value cache management system processes inference requests of a generative model. An inference request requests a starting virtual memory address and a number of layers in the generative model. In response to receiving an inference request, contiguous virtual memory space is reserved for the key-value cache in accordance with the inference request by assigning the starting virtual memory address in the key-value cache and calculating memory pointers for each layer in the model and each block so that the one or more blocks are written sequentially. The generated memory pointers are outputted to the generative model so that each self-attention layer writes computed key-value pairs at physical addresses in the key-value cache specified by the memory pointers.

The invention relates to the technical field of geographic information systems, in particular to a map tile data efficient access method and system based on hybrid storage and intelligent layering, and the method comprises the following steps: constructing a multi-level storage architecture, carrying out dynamic heat analysis, carrying out intelligent layering scheduling, preloading and space prediction, and carrying out transmission and access optimization. The method has the beneficial effects that the multi-level storage pool is constructed by combining the advantages of object storage and a distributed file system; adopting a dynamic tile popularity analysis model to realize hot data cache acceleration and cold data hierarchical archiving; and meanwhile, a tile request preloading mechanism is introduced, and an access path is optimized in combination with a spatial locality prediction algorithm. According to the method, the storage cost can be remarkably reduced, the tile request delay is reduced, quick response in a high-concurrency scene is supported, and the method is suitable for application scenes such as Internet map services and smart cities.

A system and method for real-time team intent modeling using persistent cognitive machines with federated human profiles which processes individual team member behavioral signals through geometric intent analyzers that generate high-dimensional vector representations of individual objectives and preferences. A team intent orchestrator aggregates individual vectors into collective representations within a dynamic geometric manifold that evolves based on team coordination patterns. Federated human profiles enable privacy-preserving knowledge sharing across teams through geometric abstraction techniques that preserve coordination utility while protecting individual privacy. The system implements proactive conflict detection through trajectory analysis that identifies potential coordination issues before performance impact, and provides real-time synchronization mechanisms that maintain team coordination coherence despite individual behavioral changes. Cross-team learning capabilities enable organizational intelligence development through pattern abstraction and context-aware adaptation of successful coordination strategies. The persistent cognitive architecture maintains coordination patterns across sessions and team composition changes, enabling continuous improvement through accumulated team experience.

The invention discloses a processor, a chip product, computer equipment and a tensor processing method, and relates to the technical field of processors. A first tensor having a plurality of elements arranged according to a first arrangement order is stored in the first storage unit; the tensor storage engine is used for reading the plurality of elements from the first storage unit to the second storage unit according to a second arrangement sequence to obtain a rearranged tensor; the tensor calculation engine is used for executing logical operation on the rearranged tensor to obtain an operation result; the format conversion unit is used for converting the data format of each element in the operation result into a target data format to obtain an operation result after format conversion, and storing the operation result after format conversion into a third storage unit, the operation result after format conversion comprises the operation results of the multiple elements, and the third storage unit is used for storing the operation results after format conversion. A third arrangement sequence of the operation results of the plurality of elements in the third storage unit is the same as the first arrangement sequence. The development cost of the processor can be reduced.

Embodiments are directed to a file system that include object stores. An object store for write requests may be provided. Write ahead log (WAL) entries that include data blocks may be generated. A WAL object may be generated based on the WAL entries and stored in the object store. An in-memory overlay may be updated to associate the data blocks with the WAL object. A checkpoint operation may be executed to: generate an index object that includes index entries that associate other data blocks with data objects stored in the object store; update the index object to include index entries that associate the data blocks with the WAL object; store the updated index object in the object store; update the in-memory overlay to remove the association of the data blocks and the WAL object and update the in memory WAL to remove records of successfully checkpointed WAL objects.

The invention discloses a memory access method, a program product, equipment and a medium, and relates to the technical field of computers, firmware is utilized to determine to-be-reserved physical memory information, the to-be-reserved physical memory information is analyzed and continuously split to obtain physical memory segments, and the physical memory segments are divided and aligned; dividing the virtual address space, and performing alignment processing on the divided virtual address space; performing memory mapping on the processed physical memory segment and a physical address space corresponding to the processed virtual address space; generating a page table by utilizing a physical address space corresponding to the mapped and processed virtual address space; when an access instruction of a user is obtained, the corresponding target physical address space is screened from the page table to determine the mapped target physical memory segment, so that the user accesses the target physical memory segment based on the user mode process, the range and capacity of the memory segment are dynamically configured, the stability of the memory during key load operation is guaranteed, and the memory access performance is improved.

This invention pertains to a system optimized for reutilizing allocated underutilized or unused allocated DRAM, comprising a first host, a second host, and a resource composer, interconnected via CXL. Both hosts run packaged computing environments (PCEs), which may be containers or virtual machines, and are equipped to handle respective processes, P1 and P2. The resource composer is tasked with receiving data related to P1's memory usage from a kernel module on the first host, identifying underutilized DRAM mapped to P1, and subsequently remapping it to P2's address space on the second host. This process involves the use of CXL.mem commands, which are then translated into appropriate CXL.cache or CXL.io commands for DRAM access based on the mapping.

Techniques are described for enabling concurrent cross-region replications and garbage collection while maintaining consistency and data integrity among file systems. In some embodiments, techniques for garbage collection fencing utilize a system-level garbage fencing key (GC fencing key) and one or more job-level GC fencing keys in a source file system that perform one or more cross-region replications with one or more target file systems, one replication and one job-level GC fencing key per target file system. In some embodiments, one job-level GC fencing key in a source file system and one job-level GC fencing key in a source file system together provide garbage fencing for a cross-region replication. In certain embodiments, the metadata information in a GC fencing key can inform, instruct, or be used to configure garbage collectors to skip garbage collection for a range of snapshots in a file system.

An apparatus is provided that includes a network interface to transmit and receive data packets over a network; a memory including one or more buffers; an arithmetic logic unit to perform arithmetic operations for organizing and combining the data packets; and a circuitry to receive, via the network interface, data packets from the network; aggregate, via the arithmetic logic unit, the received data packets in the one or more buffers at a network rate; and transmit, via the network interface, the aggregated data packets to one or more compute nodes in the network, thereby optimizing latency incurred in combining the received data packets and transmitting the aggregated data packets, and hence accelerating a bulk data allreduce operation. One embodiment provides a system and method for performing the allreduce operation. During operation, the system performs the allreduce operation by pacing network operations for enhancing performance of the allreduce operation.

The invention discloses a large language model reasoning performance optimization method and device oriented to a resource-constrained environment, and the method comprises the steps: dynamically adjusting a calculation thread and memory resources of a large language model reasoning service based on the condition of available resources in the resource-constrained environment in a layer-by-layer reasoning process of the large language model reasoning service; model parameters stored in an SSD or a PM are gradually and asynchronously read and loaded into a memory by adopting an assembly line loading mechanism combined with the dynamic memory; and in the off-peak use period of the system, the memory space is released by actively identifying and deleting unimportant KV cache items for the cache KV Cache aiming at the key value stored in the memory and used for caching the model intermediate calculation result of the large language model. The method aims at solving the problems of memory limitation, non-uniform resource allocation and low reasoning efficiency when a large language model is efficiently deployed and executed on personal equipment, and the performance of the large model in a limited resource environment is optimized.

Methods and apparatus for application aware memory patrol scrubbing techniques. The method may be performed on a computing system including one or more memory devices and running multiple applications with associated processes. The computer system may be implemented in a multi-tenant environment, where virtual instances of physical resources provided by the system are allocated to separate tenants, such as through virtualization schemes employing virtual machines or containers. Quality of Service (QoS) scrubbing logic and novel interfaces are provided to enable memory scrubbing QoS policies to be applied at the tenant, application, and / or process level. This QoS policies may include memory ranges for which specific policies are applied, as well as bandwidth allocations for performing scrubbing operations. A pattern generator is also provided for generating scrubbing patterns based on observed or predicted memory access patterns and / or predefined patterns.

The invention discloses a cross-host memory sharing method, system and device and a medium, the memory sharing system comprises a master node and a plurality of slave nodes, the memory sharing method is applied to the master node, and the method comprises the steps that a memory application request of a target slave node is received; applying for a target memory in a target memory sharing area according to a memory size requirement corresponding to the request, feeding back memory information of the target memory to a target slave node, so that the target slave node judges a corresponding memory type according to the memory information, and if a process corresponding to the target slave node executes a memory mapping method, sending the target memory to the target slave node. If yes, the target memory can be mapped to the proceeding virtual address space according to the target type and the offset corresponding to the target memory, so that the process can use the distributed target memory. Therefore, it can be guaranteed that when one node writes the memory, other nodes cannot synchronously write the memory, and then the data consistency of the shared memory accessed by multiple hosts is guaranteed.

An example method includes receiving, by a data streaming platform from a client, a write request to write data to a data stream; storing, by the data streaming platform and based on the receiving the write request, the data in a particular partition of a plurality of partitions of the data stream and on a particular cluster of a plurality of clusters of the data streaming platform; translating, by the data streaming platform, an actual offset specifying the particular cluster and the particular partition into a virtual offset defining an ordering of the data relative to other data in the data stream stored across the plurality of partitions and the plurality of clusters; and storing, by the data streaming platform, a mapping of the virtual offset to the actual offset.

The embodiment of the invention provides a memory recovery method and device, electronic equipment and a storage medium, and relates to the technical field of data storage. Under the condition that both the file system and the storage device support the perceptual garbage collection function, the device state of the storage device is obtained in response to the starting of the perceptual garbage collection function; according to the equipment state, determining whether an execution condition for sensing a garbage collection function is met or not; and if the execution condition of the garbage collection sensing function is met, the file system is linked to perform memory collection on the storage device, so that the file system can know the data blocks moved by the storage device, the file system is prevented from moving the data blocks moved by the storage device again, and the efficiency of the file system is improved. In addition, invalid blocks in the file system and the storage device can be synchronized, the situation that invalid data blocks in the file system are moved when the storage device executes memory recovery is avoided, and therefore the service life expenditure of the storage device and the write-in amplification value of the storage device are reduced.

Examples described herein include one or more processors; a network interface; and a direct memory access (DMA) engine communicatively coupled to the one or more processors. In some examples, the DMA engine is to receive a DMA data access request and based on an address in the DMA data access request corresponding to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device. In some examples, if the source address corresponds to a local memory device and the destination address corresponds to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device.

This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

The invention relates to the technical field of electrical digital data processing, and discloses a statistical entropy and multi-factor fused text similarity data processing method, which comprises the following steps that: a processor extracts substring sets which do not contain maximum common values of a first data sequence and a second data sequence, and calculates the quadratic sum of the lengths of substrings to generate local statistical entropy; traversing the maximum common substring set to obtain storage address indexes of the maximum common substring set in the first data sequence memory space and the second data sequence memory space, and constructing a topological mapping vector of a mapping structure displacement relationship; calculating the total number of inverted pairs of the topology mapping vector by using a merge sorting algorithm, and generating a normalized topology dissipation index; and by taking the local statistical entropy as an information carrier and taking the topological dissipation index as a structural damping factor, executing nonlinear damping modulation operation to obtain a final similarity score, and solving the technical problem that the block-level displacement cannot be identified by linear scanning logic by quantizing topological entropy increase of data distributed in a storage space.

A system and method for compressing and restoring multi-modal data utilizing a variational autoencoder to enable homomorphic compression techniques is disclosed. Multi-modal input data, comprising at least two different data types, is compressed into a unified latent space using an encoder network of a multi-modal variational autoencoder. Homomorphic operations are performed on compressed data in the latent space. The latent space compressed data is decompressed using a decoder network of the multi-modal variational autoencoder. The system utilizes modality-specific layers and cross-modal attention mechanisms to effectively process diverse data types. The homomorphic operations enable performing computations while the data is in a compressed form, preserving results of those operations in the decompressed output. This approach allows for efficient storage, transmission, and analysis of multi-modal data while maintaining privacy and data integrity across different modalities.

The invention relates to the technical field of computer aided design, in particular to a large-volume BIM model optimization method and system based on intelligent loading, and the method comprises the following steps: carrying out the interval judgment based on the central point of a component and the boundary value of a bounding box, carrying out the dual classification according to the type coding, and generating a block structure according to the surface number and mapping layering; included angle distance judgment sorting is performed by combining view cone vectors to generate a loading sequence, and cosine similarity is calculated based on view angle translation and rotation division behavior segments to screen similar components to generate a preloading list. According to the method, block structures are generated based on double classification of component center points and bounding box boundary values, visual angle priority loading visual areas are dynamically matched in combination with visual cone included angle distance sorting, potential areas are predicted through user visual angle translation and rotation parameters to generate a preloading list, and the precision grade of non-core components is dynamically adjusted according to terminal resource parameters. And inefficient resources are identified by using the timestamp, the stay duration and the frame rate difference value, and synchronous optimization of the loading efficiency and the system performance is realized.

The invention belongs to the field of memory control, and provides a mapping table management method and a storage device.The method comprises the steps that a write-in instruction from a host system is received; judging an access mode of the write-in instruction according to an access feature of a logic address corresponding to the write-in instruction; if the access mode of the write-in instruction is judged to be a continuous access mode, updating a mapping relation from a logic address to a physical address corresponding to the write-in instruction to a main mapping table; and if it is judged that the access mode of the write-in instruction is a random access mode, recording and managing a mapping relation from a logic address to a physical address corresponding to the write-in instruction through a temporary mapping table arranged in a buffer memory, and delaying updating of a main mapping table. Therefore, the random write-in performance of the storage device is improved, and the service life is prolonged.

A method for managing data items includes: obtaining a query log; initiating performance of a first recommendation cycle (RC) by analyzing the query log to generate a recommendation list (RL) including at least a data item with a high-level cache reward; providing the RL to an administrator via a graphical user interface (GUI); providing an administrator-confirmed recommendation list (ACRL) to a cache engine, in which the ACRL is received from the administrator in response to the RL being provided to the administrator; receiving a refreshment policy of the data item included in the ACRL from the administrator; storing, based on the ACRL, the data item as a cached data item in a storage device.

The invention discloses a data processing method, device and equipment and a readable storage medium, and the method comprises the steps: running a business application in a virtual machine, and obtaining a business application instruction set; the instruction type of the business application instruction set is an instruction type supported by a processor of the host machine; writing a service application instruction set in a virtual memory of the virtual machine into a shared physical memory in a virtual interaction device corresponding to the virtual machine, and generating writing notification information used for representing a writing completion state of the service application instruction set; the shared physical memory is a physical memory used for being jointly read and written by the virtual machine and the management program in the host machine; and in the management program, obtaining write-in notification information, obtaining the business application instruction set in the shared physical memory through the write-in notification information, and executing the business application instruction set through a processor of the host machine to obtain instruction execution data corresponding to the business application instruction set. By adopting the method and the device, the performance of running the business application by the virtual machine in the host machine can be improved.

The embodiments of the present disclosure provide data processing methods, a computer system, a computer-readable storage medium and a computer program product. A data processing method comprises: acquiring a first control command transmitted by a second service program, and determining a physical address region; applying for a virtual address region from a second virtual address space to which a service data storage region is mapped, and on the basis of the virtual address region, generating a second control command; and establishing a mapping relationship between the virtual address region and the physical address region for a first service program to access the physical address region on the basis of the virtual address region in the second control command acquired from a control command storage region. The technical solution provided in the embodiments of the present disclosure realizes high-speed data transmission between service programs.

Provided in the embodiments of the present description are a data reclamation method and apparatus, a computing device and a computer-readable storage medium. The data reclamation method comprises: acquiring state indicators of a storage unit, the state indicators comprising a utilization rate indicator and a garbage data proportion indicator of the storage unit; according to the utilization rate indicator, determining a storage pressure level; acquiring a data reclamation pressure level classification policy on the basis of the storage pressure level, the data reclamation pressure level classification policy comprising a level classification parameter used for determining data reclamation pressure levels, wherein the higher a storage pressure level, the higher a data reclamation pressure level determined by the level classification parameter; according to the garbage data proportion indicator and the data reclamation pressure level classification policy, determining a data reclamation pressure level; and, on the basis of the data reclamation pressure level, predicting a data reclamation bandwidth of the storage unit. The present disclosure ensures the rationality of data reclamation bandwidth setting, thus remarkedly improving the data reclamation performance and the read-write performance.

The invention discloses a high-speed camera data self-adaptive two-stage caching system and method and a storage medium, and relates to the technical field of machine vision high-speed imaging and high-speed data storage, a preprocessing unit is used for performing deserialization and parallel connection, ROI cutting and gain adjustment on collected item number data, and writing incremental FrameID and cyclic redundancy check codes into each frame; the DDR annular cache unit comprises a monitoring module, a decision module and an execution module; the decision module is used for calculating an instantaneous cache demand Cnew and a dynamic cache occupancy U; the execution module expands and shrinks an annular buffer space in a single shot through a DDR4 controller, and outputs a Hi / Lo mark in real time through an occupancy rate comparator to drive an NVMe queue manager. According to the invention, on the premise of zero extra burden in a normal working condition, millisecond-level automatic capacity expansion and high-speed flood discharge can be realized in a sudden working condition, and real-time frame-level integrity verification can be completed on a local FPGA (Field Programmable Gate Array) side. The patent is subsidized by national key research and development plans, and the project number is 2023YFF0719700.

A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.