11612results about "Memory adressing/allocation/relocation" patented technology

A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.

Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

The invention discloses a big data stream-oriented memory cache storage system, relates to the technical field of memory cache storage, and is used for solving the problem of poor memory cache storage management. According to the method, the access frequency, the timeliness and the service importance of the data are evaluated, the priority ranking model is constructed, the cache strategy is optimized based on the ranking result, the data storage and scheduling efficiency is improved, the write-in and read operation of the memory cache is adjusted in real time in combination with the flow prediction model, memory overload is effectively avoided, and the data storage and scheduling efficiency is improved. According to the method, non-emergency data writing is delayed by adopting a delayed writing and lazy loading strategy, data is loaded as required, meanwhile, a cache elimination mechanism is designed according to data priority, access frequency, survival time and size, data migration is carried out when a cache space is insufficient, reasonable resource allocation is ensured, and through a multi-level and dynamic cache management scheme, the cache management efficiency is improved. Therefore, the system performance, the resource utilization rate and the response speed are remarkably improved, the data processing efficiency is optimized, and cache conflicts are reduced.

This disclosure provides techniques for managing writes of data useful for storage systems that do not permit overwrite of a logical address. One implementation provides a nonvolatile memory storage drive, such as a flash memory drive, that provides support for zoned drive and / or Open Channel-compliant architectures. Circuitry on the storage drive tracks storage location release metadata for addressable memory space, optionally providing to a host system information upon which maintenance decisions or related scheduling can be based. The storage drive can also provide buffering support for accommodating receipt of out-of-order writes and unentanglement and performance of out of order writes, with buffering resources being configurable according to any one of a number of parameters. The disclosed storage drive facilitates reduced error rates and lower request traffic in a manner consistent with newer memory standards that mandate that writes to logical addresses be sequential.

Embodiments are directed to a file system that include object stores. An object store for write requests may be provided. Write ahead log (WAL) entries that include data blocks may be generated. A WAL object may be generated based on the WAL entries and stored in the object store. An in-memory overlay may be updated to associate the data blocks with the WAL object. A checkpoint operation may be executed to: generate an index object that includes index entries that associate other data blocks with data objects stored in the object store; update the index object to include index entries that associate the data blocks with the WAL object; store the updated index object in the object store; update the in-memory overlay to remove the association of the data blocks and the WAL object and update the in memory WAL to remove records of successfully checkpointed WAL objects.

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

A key-value cache management system processes inference requests of a generative model. An inference request requests a starting virtual memory address and a number of layers in the generative model. In response to receiving an inference request, contiguous virtual memory space is reserved for the key-value cache in accordance with the inference request by assigning the starting virtual memory address in the key-value cache and calculating memory pointers for each layer in the model and each block so that the one or more blocks are written sequentially. The generated memory pointers are outputted to the generative model so that each self-attention layer writes computed key-value pairs at physical addresses in the key-value cache specified by the memory pointers.

A method, computer program product, and computing system for receiving a metadata page for storage within a log-structured metadata store. An entry may be generated within a translation table page of a translation table within the log-structured metadata store, wherein each entry of a plurality of entries within the translation table page is associated with a separate metadata page. One or more metadata page deltas for the metadata page may be recorded in the log-structured metadata store. The one or more metadata page deltas for the metadata page may be flushed to a persistent memory storage. In response to flushing the one or more metadata page deltas for the metadata page, the entry within the translation table page that is associated with the metadata page may be updated without accessing any other entry within the translation table page associated with other metadata pages.

The invention relates to the technical field of geographic information systems, in particular to a map tile data efficient access method and system based on hybrid storage and intelligent layering, and the method comprises the following steps: constructing a multi-level storage architecture, carrying out dynamic heat analysis, carrying out intelligent layering scheduling, preloading and space prediction, and carrying out transmission and access optimization. The method has the beneficial effects that the multi-level storage pool is constructed by combining the advantages of object storage and a distributed file system; adopting a dynamic tile popularity analysis model to realize hot data cache acceleration and cold data hierarchical archiving; and meanwhile, a tile request preloading mechanism is introduced, and an access path is optimized in combination with a spatial locality prediction algorithm. According to the method, the storage cost can be remarkably reduced, the tile request delay is reduced, quick response in a high-concurrency scene is supported, and the method is suitable for application scenes such as Internet map services and smart cities.

A memory management method and apparatus, and a computing device. The method is executed by a GMEM system. When receiving a physical memory range, a memory management unit operation function, and an accelerator device address of an accelerator device, the GMEM system configures a memory management unit operation function interface for the accelerator device, and a device where the GMEM system is located is enabled to use a driver of the accelerator device to manage a memory management unit and a physical memory of the accelerator device by means of the memory management unit operation function interface for the accelerator device, so as to read and write data. In the present application, the GMEM system extends a native memory management interface of an operating system into a heterogeneous memory management interface, supporting programming based on a unified virtual address space, and memory management unit operation function interfaces are configured for different types of accelerator devices, so that the device where the GMEM system is located can support the use of different types of accelerator devices, without the need to consider the compatibility of memory interfaces of different types of accelerator devices.

A system and method for real-time team intent modeling using persistent cognitive machines with federated human profiles which processes individual team member behavioral signals through geometric intent analyzers that generate high-dimensional vector representations of individual objectives and preferences. A team intent orchestrator aggregates individual vectors into collective representations within a dynamic geometric manifold that evolves based on team coordination patterns. Federated human profiles enable privacy-preserving knowledge sharing across teams through geometric abstraction techniques that preserve coordination utility while protecting individual privacy. The system implements proactive conflict detection through trajectory analysis that identifies potential coordination issues before performance impact, and provides real-time synchronization mechanisms that maintain team coordination coherence despite individual behavioral changes. Cross-team learning capabilities enable organizational intelligence development through pattern abstraction and context-aware adaptation of successful coordination strategies. The persistent cognitive architecture maintains coordination patterns across sessions and team composition changes, enabling continuous improvement through accumulated team experience.

The invention discloses a processor, a chip product, computer equipment and a tensor processing method, and relates to the technical field of processors. A first tensor having a plurality of elements arranged according to a first arrangement order is stored in the first storage unit; the tensor storage engine is used for reading the plurality of elements from the first storage unit to the second storage unit according to a second arrangement sequence to obtain a rearranged tensor; the tensor calculation engine is used for executing logical operation on the rearranged tensor to obtain an operation result; the format conversion unit is used for converting the data format of each element in the operation result into a target data format to obtain an operation result after format conversion, and storing the operation result after format conversion into a third storage unit, the operation result after format conversion comprises the operation results of the multiple elements, and the third storage unit is used for storing the operation results after format conversion. A third arrangement sequence of the operation results of the plurality of elements in the third storage unit is the same as the first arrangement sequence. The development cost of the processor can be reduced.

Embodiments are directed to a file system that include object stores. An object store for write requests may be provided. Write ahead log (WAL) entries that include data blocks may be generated. A WAL object may be generated based on the WAL entries and stored in the object store. An in-memory overlay may be updated to associate the data blocks with the WAL object. A checkpoint operation may be executed to: generate an index object that includes index entries that associate other data blocks with data objects stored in the object store; update the index object to include index entries that associate the data blocks with the WAL object; store the updated index object in the object store; update the in-memory overlay to remove the association of the data blocks and the WAL object and update the in memory WAL to remove records of successfully checkpointed WAL objects.

A new system architecture for servers used in supercomputers uses an on-chip switch fabric with backpressure to improve performance. A server-on-a-chip includes one or more of the on-chip switch fabrics coupling one or more processing cores enabled to respond to the backpressure. Optionally, one or more ports of the on-chip switch fabrics are used to provide (external) ports of the server-on-a-chip to enable seamless communication with other server-on-a-chip instances. Various instances of the server-on-a-chip use the seamless communication to communicate with each other over a single printed circuit board and / or with each other across a plurality of printed circuit boards. Optional smart memory and / or multi-homed memory techniques improve memory efficiency by posting all writes, hiding DRAM maintenance operations (e.g., refresh, scrubbing, error correction and / or error logging), and / or reducing attack vectors, such as via secure booting of encrypted boot images.

Described techniques provide addressing schemes that account for address differences between active and inactive memory banks in dual bank memory architectures used in software over the air (SOTA) updates implemented using address swapping between the dual memory banks, including providing address translations where needed to obtain one standard addressing scheme for purposes of SOTA updates. A timing and implementation of authentication and booting techniques may ensure that signature authentication and boot processes use correct memory addresses across the dual memory banks to enable updates of both an application and a bootloader to occur. Swapping techniques are described that enable robust, secure swapping between the banks, and that enable SOTA updates to hardware security manager (HSM) software, while ensuring use of such HSM software in dual bank scenarios.

The invention discloses a memory access method, a program product, equipment and a medium, and relates to the technical field of computers, firmware is utilized to determine to-be-reserved physical memory information, the to-be-reserved physical memory information is analyzed and continuously split to obtain physical memory segments, and the physical memory segments are divided and aligned; dividing the virtual address space, and performing alignment processing on the divided virtual address space; performing memory mapping on the processed physical memory segment and a physical address space corresponding to the processed virtual address space; generating a page table by utilizing a physical address space corresponding to the mapped and processed virtual address space; when an access instruction of a user is obtained, the corresponding target physical address space is screened from the page table to determine the mapped target physical memory segment, so that the user accesses the target physical memory segment based on the user mode process, the range and capacity of the memory segment are dynamically configured, the stability of the memory during key load operation is guaranteed, and the memory access performance is improved.

This invention pertains to a system optimized for reutilizing allocated underutilized or unused allocated DRAM, comprising a first host, a second host, and a resource composer, interconnected via CXL. Both hosts run packaged computing environments (PCEs), which may be containers or virtual machines, and are equipped to handle respective processes, P1 and P2. The resource composer is tasked with receiving data related to P1's memory usage from a kernel module on the first host, identifying underutilized DRAM mapped to P1, and subsequently remapping it to P2's address space on the second host. This process involves the use of CXL.mem commands, which are then translated into appropriate CXL.cache or CXL.io commands for DRAM access based on the mapping.

Techniques are described for enabling concurrent cross-region replications and garbage collection while maintaining consistency and data integrity among file systems. In some embodiments, techniques for garbage collection fencing utilize a system-level garbage fencing key (GC fencing key) and one or more job-level GC fencing keys in a source file system that perform one or more cross-region replications with one or more target file systems, one replication and one job-level GC fencing key per target file system. In some embodiments, one job-level GC fencing key in a source file system and one job-level GC fencing key in a source file system together provide garbage fencing for a cross-region replication. In certain embodiments, the metadata information in a GC fencing key can inform, instruct, or be used to configure garbage collectors to skip garbage collection for a range of snapshots in a file system.

A data processing method and a storage apparatus are disclosed. The data processing method includes: receiving, by an NVMe storage device, an NVMe write command sent by a host, where the NVMe write command carries a key and a value pointer, the value pointer points to first storage space, and the first storage space is used to store a value; obtaining, by the NVMe storage device, the key from the NVMe write command and a value length, and allocating second storage space to the value according to the value length, where the second storage space is in the NVMe storage device; and obtaining, by the NVMe storage device, the value from the host, and storing the value in the second storage space.

An apparatus is provided that includes a network interface to transmit and receive data packets over a network; a memory including one or more buffers; an arithmetic logic unit to perform arithmetic operations for organizing and combining the data packets; and a circuitry to receive, via the network interface, data packets from the network; aggregate, via the arithmetic logic unit, the received data packets in the one or more buffers at a network rate; and transmit, via the network interface, the aggregated data packets to one or more compute nodes in the network, thereby optimizing latency incurred in combining the received data packets and transmitting the aggregated data packets, and hence accelerating a bulk data allreduce operation. One embodiment provides a system and method for performing the allreduce operation. During operation, the system performs the allreduce operation by pacing network operations for enhancing performance of the allreduce operation.

A heterogeneous processing system including a host processor, a first processor with a first memory and a first data transfer resource, a second processor with a second memory, and switch and bus circuitry that communicatively couples the processors and the data transfer resource. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to perform one memory to memory transfer operation between the first and second memories using the data transfer resource. The first processor may be configured to program the first data transfer resource. A method including mapping virtual addresses of the second memory to physical addresses of the switch and bus circuitry, and configuring the first processor to perform one memory to memory transfer operation between the first and second memories using the first data transfer resource.

The invention discloses a large language model reasoning performance optimization method and device oriented to a resource-constrained environment, and the method comprises the steps: dynamically adjusting a calculation thread and memory resources of a large language model reasoning service based on the condition of available resources in the resource-constrained environment in a layer-by-layer reasoning process of the large language model reasoning service; model parameters stored in an SSD or a PM are gradually and asynchronously read and loaded into a memory by adopting an assembly line loading mechanism combined with the dynamic memory; and in the off-peak use period of the system, the memory space is released by actively identifying and deleting unimportant KV cache items for the cache KV Cache aiming at the key value stored in the memory and used for caching the model intermediate calculation result of the large language model. The method aims at solving the problems of memory limitation, non-uniform resource allocation and low reasoning efficiency when a large language model is efficiently deployed and executed on personal equipment, and the performance of the large model in a limited resource environment is optimized.

Methods and apparatus for application aware memory patrol scrubbing techniques. The method may be performed on a computing system including one or more memory devices and running multiple applications with associated processes. The computer system may be implemented in a multi-tenant environment, where virtual instances of physical resources provided by the system are allocated to separate tenants, such as through virtualization schemes employing virtual machines or containers. Quality of Service (QoS) scrubbing logic and novel interfaces are provided to enable memory scrubbing QoS policies to be applied at the tenant, application, and / or process level. This QoS policies may include memory ranges for which specific policies are applied, as well as bandwidth allocations for performing scrubbing operations. A pattern generator is also provided for generating scrubbing patterns based on observed or predicted memory access patterns and / or predefined patterns.

Content describing an intended usage of a storage system is received. The content is analyzed by a generative artificial intelligence (AI) model to identify the intended usage described by the content. One or more configurations of the storage system are identified that support the intended usage described by the content. A response including the one or more configurations of the storage system is generated.

Examples described herein and includes at least one processor and a direct memory access (DMA) device. In some examples, the DMA device is to: access a command from a memory region allocated to receive commands for execution by the DMA device, wherein the command is to access content from a local memory device or remote memory node. In some examples, the DMA device is to: determine if the content is stored in a local memory device or a remote memory node based on a configuration that indicates whether a source address refers to a memory address associated with the local memory device or the remote memory node and whether a destination address refers to a memory address associated with the local memory device or the remote memory node. In some examples, the DMA device is to: copy the content from a local memory device or copy the content to the local memory device using a memory interface.

The invention discloses a cross-host memory sharing method, system and device and a medium, the memory sharing system comprises a master node and a plurality of slave nodes, the memory sharing method is applied to the master node, and the method comprises the steps that a memory application request of a target slave node is received; applying for a target memory in a target memory sharing area according to a memory size requirement corresponding to the request, feeding back memory information of the target memory to a target slave node, so that the target slave node judges a corresponding memory type according to the memory information, and if a process corresponding to the target slave node executes a memory mapping method, sending the target memory to the target slave node. If yes, the target memory can be mapped to the proceeding virtual address space according to the target type and the offset corresponding to the target memory, so that the process can use the distributed target memory. Therefore, it can be guaranteed that when one node writes the memory, other nodes cannot synchronously write the memory, and then the data consistency of the shared memory accessed by multiple hosts is guaranteed.

Systems and methods for demand-based storage are disclosed. A first storage device is coupled to a first computing device over a first link. The first storage device includes a storage medium and a processing circuit connected to the storage medium. The processing circuit may be configured to: receive a first request for a first storage capacity; transmit a second request for allocating at least a portion of the first storage capacity on a second storage device configured to communicate with the first storage device over a second link; receive a first storage command from the first computing device; generate a second storage command based on the first storage command; and transmit the second storage command to the second storage device for execution of the second storage command by the second storage device.

The invention relates to a self-adaptive partition circulation storage method and device suitable for a flash memory, and the method comprises the steps: obtaining an equipment parameter set and partition rule information of flash memory equipment, carrying out logic partition division on the equipment parameter set based on the partition rule information, and obtaining corresponding initial partition configuration information; obtaining a type identifier of the write-in data and cache mapping data, and carrying out association processing on the type identifier and the cache mapping data to obtain a corresponding target storage partition; performing storage planning analysis on the target storage partition and the target write-in block position according to a preset one-time programming perception data distribution algorithm to obtain a corresponding initial partition adjustment scheme; and performing comprehensive processing on the initial partition adjustment scheme and the dynamic partition information according to a preset Dynamic-FTL algorithm to obtain a corresponding global storage optimization strategy. According to the invention, the storage management strategy can be flexibly adjusted according to the characteristics and demand changes of different data.

In at least one embodiment, processing can include: recording, in a metadata (MD) log, a metadata (MD) update to a MD page having a logical address LA1; flushing MD updates, including the MD update, from the MD log; applying at least the MD update to the MD page to generate an updated version; storing the updated version of the MD page at a storage location PA2 different from a first location of the MD page prior to updating; recording, in a translation table (TT) log, a TT update that updates entry E1 of a TT to map LA1 of the MD page to PA2 rather than the first location; flushing TT updates from the TT log; applying at least the TT update to the TT to generate an updated version; and storing the updated TT version at a storage location different from a prior location of the TT prior to updating.

A data storage device includes a first partition having memory blocks of a first type and a second partition having memory blocks of a second type. The second partition also includes hybrid memory blocks. A storage balancing system monitors a state of each partition and determines whether to initiate a garbage collection process. The storage balancing system also determines whether hybrid memory blocks, if included in the garbage collection process, are replaceable by allocating memory blocks of the second type as new hybrid memory blocks. If the storage balancing system determines the hybrid memory blocks are not replaceable, the storage balancing system dynamically determines a ratio of memory blocks of the first type and hybrid memory blocks to include in the garbage collection process.