6543results about "Memory adressing/allocation/relocation" patented technology

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

A system and method for real-time team intent modeling using persistent cognitive machines with federated human profiles which processes individual team member behavioral signals through geometric intent analyzers that generate high-dimensional vector representations of individual objectives and preferences. A team intent orchestrator aggregates individual vectors into collective representations within a dynamic geometric manifold that evolves based on team coordination patterns. Federated human profiles enable privacy-preserving knowledge sharing across teams through geometric abstraction techniques that preserve coordination utility while protecting individual privacy. The system implements proactive conflict detection through trajectory analysis that identifies potential coordination issues before performance impact, and provides real-time synchronization mechanisms that maintain team coordination coherence despite individual behavioral changes. Cross-team learning capabilities enable organizational intelligence development through pattern abstraction and context-aware adaptation of successful coordination strategies. The persistent cognitive architecture maintains coordination patterns across sessions and team composition changes, enabling continuous improvement through accumulated team experience.

The invention discloses a memory access method, a program product, equipment and a medium, and relates to the technical field of computers, firmware is utilized to determine to-be-reserved physical memory information, the to-be-reserved physical memory information is analyzed and continuously split to obtain physical memory segments, and the physical memory segments are divided and aligned; dividing the virtual address space, and performing alignment processing on the divided virtual address space; performing memory mapping on the processed physical memory segment and a physical address space corresponding to the processed virtual address space; generating a page table by utilizing a physical address space corresponding to the mapped and processed virtual address space; when an access instruction of a user is obtained, the corresponding target physical address space is screened from the page table to determine the mapped target physical memory segment, so that the user accesses the target physical memory segment based on the user mode process, the range and capacity of the memory segment are dynamically configured, the stability of the memory during key load operation is guaranteed, and the memory access performance is improved.

This invention pertains to a system optimized for reutilizing allocated underutilized or unused allocated DRAM, comprising a first host, a second host, and a resource composer, interconnected via CXL. Both hosts run packaged computing environments (PCEs), which may be containers or virtual machines, and are equipped to handle respective processes, P1 and P2. The resource composer is tasked with receiving data related to P1's memory usage from a kernel module on the first host, identifying underutilized DRAM mapped to P1, and subsequently remapping it to P2's address space on the second host. This process involves the use of CXL.mem commands, which are then translated into appropriate CXL.cache or CXL.io commands for DRAM access based on the mapping.

Techniques are described for enabling concurrent cross-region replications and garbage collection while maintaining consistency and data integrity among file systems. In some embodiments, techniques for garbage collection fencing utilize a system-level garbage fencing key (GC fencing key) and one or more job-level GC fencing keys in a source file system that perform one or more cross-region replications with one or more target file systems, one replication and one job-level GC fencing key per target file system. In some embodiments, one job-level GC fencing key in a source file system and one job-level GC fencing key in a source file system together provide garbage fencing for a cross-region replication. In certain embodiments, the metadata information in a GC fencing key can inform, instruct, or be used to configure garbage collectors to skip garbage collection for a range of snapshots in a file system.

The invention discloses a large language model reasoning performance optimization method and device oriented to a resource-constrained environment, and the method comprises the steps: dynamically adjusting a calculation thread and memory resources of a large language model reasoning service based on the condition of available resources in the resource-constrained environment in a layer-by-layer reasoning process of the large language model reasoning service; model parameters stored in an SSD or a PM are gradually and asynchronously read and loaded into a memory by adopting an assembly line loading mechanism combined with the dynamic memory; and in the off-peak use period of the system, the memory space is released by actively identifying and deleting unimportant KV cache items for the cache KV Cache aiming at the key value stored in the memory and used for caching the model intermediate calculation result of the large language model. The method aims at solving the problems of memory limitation, non-uniform resource allocation and low reasoning efficiency when a large language model is efficiently deployed and executed on personal equipment, and the performance of the large model in a limited resource environment is optimized.

The invention discloses a cross-host memory sharing method, system and device and a medium, the memory sharing system comprises a master node and a plurality of slave nodes, the memory sharing method is applied to the master node, and the method comprises the steps that a memory application request of a target slave node is received; applying for a target memory in a target memory sharing area according to a memory size requirement corresponding to the request, feeding back memory information of the target memory to a target slave node, so that the target slave node judges a corresponding memory type according to the memory information, and if a process corresponding to the target slave node executes a memory mapping method, sending the target memory to the target slave node. If yes, the target memory can be mapped to the proceeding virtual address space according to the target type and the offset corresponding to the target memory, so that the process can use the distributed target memory. Therefore, it can be guaranteed that when one node writes the memory, other nodes cannot synchronously write the memory, and then the data consistency of the shared memory accessed by multiple hosts is guaranteed.

An example method includes receiving, by a data streaming platform from a client, a write request to write data to a data stream; storing, by the data streaming platform and based on the receiving the write request, the data in a particular partition of a plurality of partitions of the data stream and on a particular cluster of a plurality of clusters of the data streaming platform; translating, by the data streaming platform, an actual offset specifying the particular cluster and the particular partition into a virtual offset defining an ordering of the data relative to other data in the data stream stored across the plurality of partitions and the plurality of clusters; and storing, by the data streaming platform, a mapping of the virtual offset to the actual offset.

Examples described herein include one or more processors; a network interface; and a direct memory access (DMA) engine communicatively coupled to the one or more processors. In some examples, the DMA engine is to receive a DMA data access request and based on an address in the DMA data access request corresponding to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device. In some examples, if the source address corresponds to a local memory device and the destination address corresponds to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device.

This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

The invention relates to the technical field of electrical digital data processing, and discloses a statistical entropy and multi-factor fused text similarity data processing method, which comprises the following steps that: a processor extracts substring sets which do not contain maximum common values of a first data sequence and a second data sequence, and calculates the quadratic sum of the lengths of substrings to generate local statistical entropy; traversing the maximum common substring set to obtain storage address indexes of the maximum common substring set in the first data sequence memory space and the second data sequence memory space, and constructing a topological mapping vector of a mapping structure displacement relationship; calculating the total number of inverted pairs of the topology mapping vector by using a merge sorting algorithm, and generating a normalized topology dissipation index; and by taking the local statistical entropy as an information carrier and taking the topological dissipation index as a structural damping factor, executing nonlinear damping modulation operation to obtain a final similarity score, and solving the technical problem that the block-level displacement cannot be identified by linear scanning logic by quantizing topological entropy increase of data distributed in a storage space.

The invention belongs to the field of memory control, and provides a mapping table management method and a storage device.The method comprises the steps that a write-in instruction from a host system is received; judging an access mode of the write-in instruction according to an access feature of a logic address corresponding to the write-in instruction; if the access mode of the write-in instruction is judged to be a continuous access mode, updating a mapping relation from a logic address to a physical address corresponding to the write-in instruction to a main mapping table; and if it is judged that the access mode of the write-in instruction is a random access mode, recording and managing a mapping relation from a logic address to a physical address corresponding to the write-in instruction through a temporary mapping table arranged in a buffer memory, and delaying updating of a main mapping table. Therefore, the random write-in performance of the storage device is improved, and the service life is prolonged.

The embodiments of the present disclosure provide data processing methods, a computer system, a computer-readable storage medium and a computer program product. A data processing method comprises: acquiring a first control command transmitted by a second service program, and determining a physical address region; applying for a virtual address region from a second virtual address space to which a service data storage region is mapped, and on the basis of the virtual address region, generating a second control command; and establishing a mapping relationship between the virtual address region and the physical address region for a first service program to access the physical address region on the basis of the virtual address region in the second control command acquired from a control command storage region. The technical solution provided in the embodiments of the present disclosure realizes high-speed data transmission between service programs.

The invention discloses a high-speed camera data self-adaptive two-stage caching system and method and a storage medium, and relates to the technical field of machine vision high-speed imaging and high-speed data storage, a preprocessing unit is used for performing deserialization and parallel connection, ROI cutting and gain adjustment on collected item number data, and writing incremental FrameID and cyclic redundancy check codes into each frame; the DDR annular cache unit comprises a monitoring module, a decision module and an execution module; the decision module is used for calculating an instantaneous cache demand Cnew and a dynamic cache occupancy U; the execution module expands and shrinks an annular buffer space in a single shot through a DDR4 controller, and outputs a Hi / Lo mark in real time through an occupancy rate comparator to drive an NVMe queue manager. According to the invention, on the premise of zero extra burden in a normal working condition, millisecond-level automatic capacity expansion and high-speed flood discharge can be realized in a sudden working condition, and real-time frame-level integrity verification can be completed on a local FPGA (Field Programmable Gate Array) side. The patent is subsidized by national key research and development plans, and the project number is 2023YFF0719700.

A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

The invention discloses a hot page threshold adjusting method and device, a medium, a product and a memory system, and relates to the technical field of memory management.The current load index is calculated by introducing multiple load parameters of the memory system, the running state of the system is dynamically reflected, preset hyper-parameters are matched according to the load index, and the hot page threshold is adjusted according to the hyper-parameters. Comprising a first factor influencing the bandwidth and a second factor inhibiting the ping-pong phenomenon, and according to the hyper-parameters, a hot page threshold value is calculated in a self-adaptive mode, so that dynamic classification of the hot page and the cold page is achieved. Compared with a mode of determining the hot page and the cold page by adopting a static threshold, the method has the advantages that the change of the load of the memory system can be responded in real time, the phenomena of resource waste and repeated page migration caused by a pseudo hot page are inhibited, the technical problems of hot page misjudgment and frequent page migration caused by improper hot page threshold setting are solved, and the page migration efficiency is improved. The technical effects of improving the access efficiency and improving the flexibility of memory management and the overall performance of the system are achieved.

A system includes a plurality of memory devices and a processing device operatively coupled with the plurality of memory devices, to perform operations including: receiving a request to perform a memory access operation at a first memory region of a first memory device; determining, based on a data structure referencing a namespace, a mapping between an identifier of the first memory region and an identifier of a metadata region associated with the first memory region; identifying, based on an operation type of the memory access operation, one or more corresponding actions associated with the metadata region; and, responsive to causing the memory access operation to be performed on a first plurality of memory cells at the first memory device, causing at least one of the one or more corresponding actions to be performed on a second plurality of memory cells corresponding to the metadata region.

The invention relates to the technical field of data processing, and particularly discloses an intelligent cache replacement method and system based on application awareness, and the method comprises the steps: sensing a cache state of an application scene, and determining a candidate cache replacement strategy according to a cache replacement strategy matching rule; the method comprises the following steps: collecting data of a storage node data access mode, a cache access state, a capacity state and a power consumption state of an application scene, and preprocessing the data to generate historical data; according to historical data, training a GRU model to predict future cache hit information, and determining a cache hit rate of the application scene; calculating strategy benefits according to the cache hit rate and the evaluation index of the cache hit rate, and comparing the candidate cache replacement strategy with the current cache replacement strategy; and when the cache hit rate is lower than a preset threshold value and a strategy benefit comparison result exceeds a set value, configuring the candidate cache replacement strategy as a current cache replacement strategy.

Apparatuses, systems, and methods for adjustable write timing. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent / received across the first terminal and a second set of data and a second set of metadata may be sent / received across the second terminal. When a first setting is enabled, the first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other. When disabled, the metadata may be stored in a single location. A second setting may be used to adjust a write delay to account for different timing when the first setting is enabled vs disabled.

Embodiments are directed to a file system that include object stores. An object store for write requests may be provided. Write ahead log (WAL) entries that include data blocks may be generated. A WAL object may be generated based on the WAL entries and stored in the object store. An in-memory overlay may be updated to associate the data blocks with the WAL object. A checkpoint operation may be executed to: generate an index object that includes index entries that associate other data blocks with data objects stored in the object store; update the index object to include index entries that associate the data blocks with the WAL object; store the updated index object in the object store; update the in-memory overlay to remove the association of the data blocks and the WAL object and update the in memory WAL to remove records of successfully checkpointed WAL objects.

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for flexible and contextualized multi-agent AI and human collaboration at scale. The system provides a universal multi-modal key-value subsystem for sharing partial computations across agents, implements a hybrid greedy / non-greedy placement strategy for dynamic memory management, orchestrates dynamic computational workflows and tensor workflows using hierarchical tensor-fragment scheduling, enables cross-agent orchestration with policy-based privacy preservation, and incorporates quantum-resistant secure memory enclaves. The architecture supports continuous learning without catastrophic forgetting, compositional reasoning across modalities, and secure task execution in distributed environments. This integration enables unprecedented computational efficiency, secure collaboration, and adaptive intelligence in high-dimensional decision-making environments while supporting incremental adoption through modular interfaces.

A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.

The invention relates to the technical field of artificial intelligence, and provides a data processing method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining to-be-processed data, the to-be-processed data comprises a plurality of data blocks, and each data block comprises a plurality of elements; traversing the plurality of data blocks, and determining the position of the current data block in the to-be-processed data based on the initial coordinate of the traversed current data block; and processing each element in the current data block based on the position of the current data block in the to-be-processed data. According to the method, the position of the data block in the to-be-processed data can be determined only according to the initial coordinate of each data block, then each element in the data block is processed based on the position information, coordinate calculation and position judgment are not required to be performed in each data block element by element, the calculation overhead is remarkably reduced, and the data processing efficiency is improved.

The invention is suitable for the technical field of electronic power, and provides a wave recording method based on an FPGA and a wave recording system based on the FPGA, and the wave recording method based on the FPGA comprises the following steps: carrying out the parallel real-time sampling of a plurality of paths of driving signals through the FPGA; circularly writing the sampled driving signal into a data cache module; in response to a preset triggering condition, stopping writing the driving signal into the data caching module, and freezing cached data of the data caching module; adding a timestamp to the cache data, and analyzing the cache data to generate analysis protocol data; and transferring the cache data added with the timestamps and the analysis protocol data to an external nonvolatile storage module and transmitting the cache data and the analysis protocol data to an upper computer. According to the technical scheme of the invention, continuous high-fidelity wave recording, fault backtracking and long-term data storage can be carried out on transient signals.

Some embodiments provide a neural network inference circuit (NNIC) for executing a neural network (NN) that includes computation nodes at multiple layers. The NNIC includes a set of processing circuits for executing the computation nodes of the NN, a set of memories for storing data used by the processing circuits to execute the NN layers, and a read controller for retrieving the data from the memories for use by the processing circuits. The data is stored in the memories as multiple varying-size blocks. The read controller receives read instructions for a requested block of data to be used by the processing circuits for one or more computation nodes. The read instructions include a base memory address for multiple blocks of data, a size of the requested block of data, and a location of the requested block of data within the multiple blocks of data.

A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.

The invention belongs to the technical field of semiconductors, and discloses a multi-core GPU interconnection architecture and a self-adaptive cache allocation method thereof.The multi-core GPU interconnection architecture comprises a plurality of GPU clusters and a global cluster, the global cluster comprises a global router, a global scheduler, a directory, a memory and a plurality of GPU clusters, each GPU cluster is composed of a plurality of GPU cores, and the GPU cores are arranged in the global router. Each GPU core grain comprises a plurality of independent primary data caches, secondary data caches, a local router and a network interface, and the network interface judges whether a current request is processed by the GPU core grains in a GPU cluster or not according to whether a target address in a target node belongs to the GPU cluster or not, so that a high-level multi-core grain interconnection architecture supporting cross-cluster communication is formed. According to the method, performance is optimized by adapting to different access modes, private and shared cache modes are switched in real time, single data access delay is reduced, the overall system efficiency is improved, and the method is used for a multi-core-particle heterogeneous system with a plurality of GPUs.

The invention discloses a memory allocation method and device, electronic equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that when a memory application of a requester is received, the memory size requested by the memory application is determined; if the memory size is smaller than or equal to the first threshold value, responding to the memory application based on the memory page which is not completely allocated; wherein the size of the memory page is larger than or equal to a preset value, and the first threshold value is smaller than the size of the memory page; if the memory size is greater than the first threshold and less than or equal to a second threshold, responding to the memory application based on an idle memory page in a preset memory page set; wherein the second threshold value is larger than the size of the memory page; and if the memory size is greater than the second threshold value, responding to the memory application based on the unreleased idle memory page of the cache and / or the idle memory page in the operating system. The memory allocation efficiency is improved.

To reduce noise for compute in memory vector-matrix multiplications using non-volatile memory, such in large language models or other neural networks, the matrix of values is independently programmed in multiple arrays. The input vector is then independently applied to the multiple arrays to generate a corresponding set of multiple results. The independent results can then be combined by ensemble algorithms, as an averaging, to generate the output. The combined output can then be used as input to a subsequent layer of weights, which can again be independently written in to multiple arrays.

The present invention provides a control method of a flash memory controller. The control method includes: after the flash memory controller is powered on, determining whether the flash memory controller encountered an abnormal power failure; if the flash memory controller encounters the abnormal power failure, determining a first block of a flash memory module having an open state; moving a portion of valid data within the first block to a specific block; setting the first block to have a close state; determining if a number of blank blocks within the flash memory module is less than a threshold value; and if the number of blank blocks within the flash memory module is less than the threshold value, selecting a second block having the close state and a lowest number of valid pages, and moving all valid data of the second block into the specific block.