80 results about "Page table" patented technology

Various aspects relate to a memory system including: a memory configured to store respective page data for each of a plurality of pages; a non-volatile first-in first-out, FIFO, buffer; a controller configured to carry out a checkpoint operation in response to a checkpoint command; a storage configured to store a page table including a page table entry for each page, the page table entry indicating whether the page was updated after receiving the checkpoint command; the checkpoint operation including: generating a page table copy of the page table; in response to receiving data that are to be written to a page, if, in the page table copy, the page table entry of the page indicates that the page was not updated: storing the data in the hardware FIFO buffer, generating a page data copy of the page data of the page, and merging the data with the page data copy.

A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

The present application relates to a kind of file cross-page table restoration method and device, belong to data processing technical field, by column topological feature matching and line index benchmark offset algorithm, realize the seamless logical reorganization of physical fragmentation table in global data structure, restore the logical continuity of business data;Adaptive modal shunt mechanism is constructed, accurately distinguish electronic and visual modal and call exclusive processing path, avoid the waste of computing power and secondary error caused by blindly calling visual model;Strong geometric constraint processing is applied to the preliminary extraction result of double-path heterogeneous, which is forced to be normalized to standard closed physical grid structure, greatly enhance the robustness of system to deal with complex layout such as broken line and dashed line, decouple the front-end extraction mode and the spatial logic mapping of rear end, significantly reduce the engineering integration difficulty of system, so as to realize the high-quality, automated restoration of complex cross-page table in mixed document scene.

The disclosure provides a memory exchange method and device, computer equipment and a storage medium. The method comprises: in response to an out request of a memory block, splitting the memory block into a plurality of memory pages, establishing a page table entry corresponding to each memory page, performing a data out operation on the memory page, and recording a data out position in the page table entry corresponding to the memory page; in response to a page fault request initiated by a process, determining a target memory page corresponding to a virtual address carried in the page fault request, and exchanging data into a memory space of the process according to the data out position recorded in a target page table entry corresponding to the target memory page, so as to be accessed by the process.

A physical address determining method and apparatus, a computing device, and a storage medium, where the method includes generating an input tag based on a virtual page number in a first virtual address, which is matched with a plurality of entries in a page table cache. If the input tag successfully matches a first entry in the plurality of entries, and a combination flag bit in the first entry indicates that a page table entry corresponding to the first entry is a combined entry, a physical address corresponding to the first virtual address is determined based on the virtual page number in the first virtual address and an entry tag and a physical page number in the first entry.

The application provides a memory performance test method and device, a microprocessor architecture and a storage medium, and is applied to the technical field of computers. After obtaining a memory mapping request of a user state program, the method obtains target page table attributes associated with a target file descriptor carried by the memory mapping request and allocates target physical memory. Then, the method configures page table entries of a memory page table according to the target page table attributes, establishes address mapping between the target physical memory and a virtual address space in the memory page table, and finally feeds back address information of the virtual address space to the user state program, so that the user state program performs memory testing based on the obtained address information. The file descriptor is associated with target page table attributes preconfigured by the user state program. By initiating a memory mapping request carrying different file descriptors, virtual address spaces mapped according to different page table attributes can be obtained, the test process is greatly simplified, the flexibility of the test process is improved, and the test efficiency is improved.

The present application relates to a kind of transparent large page performance monitoring method and electronic equipment, belong to computer technology field, the method includes: in each sampling period, in kernel state, obtain memory alignment performance data by memory alignment start and end trace point, obtain direct memory recovery performance data by direct memory recovery start and end trace point, obtain large page split performance data by probe and carry out transparent large page split monitoring;In each sampling period, user state program collects and records page table cache miss performance data, records continuous free block performance data;The block size of free block is the integer multiple of the page size of transparent large page;After sampling period ends, user state program reads memory alignment performance data, direct memory recovery performance data and large page split performance data from mapping, and is associated with page table cache miss performance data and continuous free block performance data and is shown.This application realizes the accurate acquisition of transparent large page performance monitoring result.

The invention discloses a computing power resource dynamic slicing and isolation method for an artificial intelligence target range, and the method comprises the following modules: S1, business feature perception and dynamic resource slicing: carrying out the analysis and modeling of an artificial intelligence attack and defense task through a mechanism, and mapping a task demand into a corresponding computing power slicing specification; s2, a driving-level video memory firewall, which monitors the video memory usage behavior of the virtual instance in real time on a driving layer of an execution node, and prevents attack behaviors such as abnormal occupation of the video memory; and S3, carrying out atomized rollback based on the model state of the shared memory. According to the mechanism, rapid recovery of the environment is realized through page table resetting. The method is oriented to an artificial intelligence target range, and the problems of static low efficiency, insufficient safety and isolation, lack of a quick recovery mechanism and the like of resource scheduling are solved through the mechanisms.

Provided are a storage management apparatus, a processor, related apparatuses and related methods. The storage management apparatus comprises: a first-level storage management unit configured to translate a specified virtual address to a corresponding virtual physical address according to a first-level page table cache table item matching the specified virtual address, the first-level page table cache table item storing a mapping relationship between a virtual address frequently accessed by a process in an operation domain and a virtual physical address; and a second-level storage management unit configured to translate the specified virtual physical address to a physical address according to a second-level page table cache table item matching the specified virtual physical address, thereby realizing translation of the virtual address to the physical address, the second-level page table cache table item storing a mapping relationship between the virtual physical address corresponding to the virtual address frequently accessed by the process in the operation domain and the physical address. The embodiments of the present disclosure improve communication efficiency between processes in different operation domains and reduce a large amount of processor computing resources and bus bandwidth.

A cache device, an operation method of the cache device, a processor, a device and a medium. The cache device comprises a plurality of cache spaces, and the plurality of cache spaces comprise a first cache space for caching a page table entry according to a page table entry caching rule. The operation method for the cache device comprises: receiving a first cache request; and in response to an operation object of the first cache request comprising a first page table entry, writing the first page table entry into the first cache space according to the page table entry caching rule. The operation method of the cache device can prevent a processor page table access miss caused by cache flushing, and improve the memory access performance of the processor.

This application provides a method, electronic device, and storage medium for obtaining memory access permissions. The method includes: checking the management domain to which the transaction belongs and the physical address accessed based on permissions; performing a multi-level MTT cache parallel lookup operation to obtain the hit results of the multi-level MTT cache; and determining the memory access permissions based on the hit results of the multi-level MTT cache. The memory access permission acquisition method of this application first caches the multi-level page table results of IO-side device transactions under a specific management domain. In subsequent access permission checks, a multi-level page table cache parallel lookup strategy replaces the traditional serial page table process, allowing IO-side device transactions to simultaneously determine the hit results of the multi-level page table cache and obtain access permissions based on the hit results. This strategy not only significantly improves the speed of permission checks but also reduces the frequency of memory access and bandwidth consumption. Furthermore, it efficiently adapts to access scenarios of IO-side devices in different management domains, further improving the overall efficiency of permission checks.

This invention discloses a RAID remapping method, comprising the following steps: obtaining the position of each data block constituting the data to be remapped on the RAID disk array; determining the disk where each data block resides based on its position on the RAID disk array; reading a plurality of corresponding data blocks from each disk; and sequentially placing the plurality of data blocks read from each disk into a page table in memory according to the disk number. This invention also discloses a system, a computer device, and a readable storage medium. The proposed solution calculates the actual data page size of each disk and, when reading and writing data to each RAID disk according to stripes, performs reading and writing according to the actual data size in the stripe size of each RAID disk and in page table address order.

This application is directed to accessing data in a memory system of an electronic system. The memory system a storage-side DRAM and one or more memory channels. The memory system receives a memory access request for target data stored in the memory system, and the memory access request includes a target virtual address of the target data. In response to the memory access request, the memory system searches a page table of the storage-side dynamic random-access memory (DRAM) for a target physical address mapped to the target virtual address of the target data. The page table includes mappings between a plurality of virtual addresses and a plurality of physical addresses of the storage-side DRAM. Based on a search result, the memory system extracts the target data stored in one of the storage-side DRAM and the one or more memory channels according to the target physical address.

This application discloses a method and apparatus for writing buffer data in a memory management unit, relating to the field of chip verification technology, and is invented to shorten verification time and improve verification efficiency. The method includes: traversing a page table to obtain the mapping relationship between virtual addresses and physical addresses recorded in the page table; filtering the mapping relationship according to a predetermined strategy to obtain a target mapping relationship; converting the target mapping relationship into a predetermined format to obtain a target mapping relationship; and writing the predetermined format target mapping relationship into a substitution bypass buffer in the memory management unit through a backdoor access function. This application is applicable to verification related to substitution bypass buffers.

Embodiments of the present application provide a cross-page table data integration output method and device, equipment and medium. The method comprises: in response to a received first operation, obtaining table data in a selected range of each of a plurality of pages, the selected range of each of one or more pages of the plurality of pages being used to represent a partial data area in a table of the page; the first operation comprises a selection operation of selecting a selected range in at least one page through at least one in-page interaction mode in at least two pages of the plurality of pages switched out through a navigation operation; the at least one in-page interaction mode comprises a box selection operation based on dragging; obtaining summary table data based on the table data in the selected range of each page; and generating an output file in a predetermined format according to the summary table data. The technical scheme of the embodiments of the present application solves the problems of complicated and error-prone operation of cross-page table data integration output in related technologies.

This application discloses a memory page table caching method and apparatus, a storage medium, and a computer program product, relating to the field of computer technologies. The method includes: A process applies for a memory page with a specific size as required, where the size of the memory page that is applied for is not limited to a page size of an any-level page table. Correspondingly, a compute device can create, based on the request of the process, a memory page with a corresponding size for the process by merging page table entries, and store, in a page table cache, a cache table entry obtained through merging. To be specific, a large memory page is actively created for the process from a source by merging the page table entries, so that a cache table entry in the page table cache can cover a plurality of page table entries in a memory page table, to increase a hit rate of the page table cache, reduce page table walks, and reduce memory access latency and memory access overheads.

This application relates to the field of memory, providing a refresh control circuit, a memory, and a refresh control method. The refresh control circuit includes a page table, a first comparison circuit, and a second comparison circuit. The page table is configured to store multiple row addresses and their activation counts. The first comparison circuit, connected to the page table, is configured to receive the currently active row address and its activation count, and compare the currently active row address and its activation count with the multiple row addresses and their activation counts stored in the page table. When a first preset condition is met, the currently active row address and its activation count are stored in the page table. The second comparison circuit, connected to the page table, is configured to compare the activation counts of the multiple row addresses in the page table and output the row address with the highest activation count as a candidate row address.

A preloading MMU is provided. The MMU includes a first TLB, a burst buffer, a second TLB, and control logic. The first TLB is configured to retrieve a first set of one or more page table entries from the first page, based at least in part on a virtual address, before a request to access a client address is received. The burst buffer stores multiple page table entries from the corresponding page table associated with a page table address on the first page. A second TLB is configured to retrieve a first set of one or more page table entries from the plurality of page table entries in the second page burst buffer, based at least in part on the virtual address, before a request to access a client address is received.

The invention discloses a server-free remote memory access performance optimization method based on cross-process memory tracking, and belongs to the technical field of computer memory management. The method comprises the following steps: designing a memory state table as a unified perception layer for remote memory access of homologous server-free containers, and realizing cross-process tracking of memory page states among different containers; a memory state table query process is embedded into hardware page table traversal, page state query is completed by hardware acceleration, and extra overhead on a memory access key path is eliminated; the remote memory access is merged and optimized based on the memory state table, cached local memory pages are reused in the container creation stage, the same remote memory access requests are merged in the operation stage, and the page missing exception frequency and the network bandwidth contention are reduced. According to the method, extra overhead caused by remote memory access in a server-free environment is effectively reduced, page missing abnormity and network bandwidth contention in a concurrent scene are greatly reduced, and the running performance and the system expandability of memory-intensive server-free applications are remarkably improved.

An electronic device may include: a processor including a first core and a second core, the first core and the second core being configured to execute a process; and a main memory configured to store a page table corresponding to the process. The first core includes: a first translation lookaside buffer (TLB) configured to store a first portion of the page table; a page table walker configured to perform a page table walk operation to look up the page table; and a TLB check predictor configured to store a check weight table and, based on the check weight table, transmit a TLB check request to the second core. The second core includes a second TLB configured to store a second portion of the page table.

This application provides a unified adaptation method for multi-vendor switches and an SDN controller, including: allocating CMA physical pages for each switch model; establishing a model page table and a shadow bitmap byte array; the model page table records the CMA physical page base address of the switch model; and each bit of each byte in the array represents the existence status of the encoding / decoding context of each firmware version within the corresponding CMA physical page; when an encoding / decoding context of a firmware version for a switch model is generated, it is written to the corresponding slot in the CMA physical page, and the corresponding bit is set to valid; in response to a packet from the target switch, the model identifier and firmware version number are extracted; the target CMA physical page base address is obtained from the model page table based on the model identifier, the firmware version number is read from the shadow bitmap byte array, and the context address is calculated to obtain the encoding / decoding context. This application can avoid memory fragmentation, ensure the resident nature of the context in memory, and achieve fast context determination and latency addressing.

This application discloses a method, apparatus, electronic device, and computer-readable medium for determining memory regions, applied to an electronic device. The method includes: obtaining the virtual address space of the electronic device when the electronic device executes a process, the virtual address space including at least one virtual address segment; dividing the virtual address space into a specified number of virtual address segments to obtain at least one first-level page table; if at least two target virtual address segments exist in the first-level page table, using the first-level page table as the target page table, the data stored in the physical address segment of the target virtual address segment cannot be successfully retrieved; if the target virtual address segment does not have a corresponding physical address segment, then re-matching a physical address segment for the target virtual address; and using the physical address segment corresponding to each virtual address segment in the target page table as a hot segment. This allows for quick and efficient identification of hot segments within physical address segments.

The application discloses a memory compression management system for embedded device table storage, and has the characteristics that the system comprises an evicted page compression selector, a partition design and a repeated page filter, the evicted page compression selector uses an entropy sampling algorithm to estimate the compression rate of the evicted page and determines the compressed page, the partition design uses zRAM memory space for frequently swapped-in / swept-out pages and uses auxiliary storage space for infrequently swapped-in / swept-out pages, and the repeated page filter adds two design page tables, namely, a Swap Index Table and a Swap Page Table, to construct a Swap page index. Compared with the prior art, the application has the advantages of high memory utilization, reduced system energy consumption caused by the swap partition, reduced influence on application caused by the swap, further improved storage performance of the table storage system, relieved memory pressure of the embedded device, and good application prospect and commercial value.

The disclosure provides a heterogeneous computing scheduling method, system, device and storage medium, and relates to the technical field of artificial intelligence. In some embodiments of the disclosure, according to the task descriptor, the page table mapping relationship of the input-output memory management unit is configured without the participation of the system core, and address translation preprocessing is completed; the virtual address interval accessed subsequently by the neural network processing unit is predicted; before the neural network processing unit initiates a memory access request, according to the virtual address interval, the page table hardware traversal of the input-output memory management unit is triggered, the page table entry is obtained, and the page table entry is loaded into the input-output conversion buffer; a start signal is sent to the neural network processing unit, so that the neural network processing unit accesses the shared main memory through the input-output memory management unit based on the page table mapping relationship. Through the dual-core division of the system core and the control core, the system overhead caused by the participation of the operating system in the underlying scheduling is reduced, and the additional power consumption overhead is reduced.

A method and system for providing memory functions during a low power mode of a portable computing device (“PCD”) may include creating a main page table during a first state of the PCD in a main memory device of the PCD. The main memory device is operational during the first state. The method and system may also include creating a low power mode page table in a first low power memory device during the first state of the PCD. The method and system may also include placing the PCD into a second state such that the first low power memory device and the second low power memory device are operational while the main memory is inoperational during the second state. One or more memory requests may be processed during the second state by using the low power mode page table in the first low power memory device.

This application discloses a request processing method and apparatus, electronic device, chip, and storage medium. It relates to the field of computer processing technology, and its main objective is to solve the problem of low efficiency in PTW request merging. The method includes: obtaining virtual address information and page table hierarchy identifiers of the page table query request to be merged; querying a target merging interval from multiple merging intervals according to the virtual address information and the page table hierarchy identifiers, wherein the multiple merging intervals include parent merging intervals and / or child merging intervals, the parent merging interval and the child merging interval are obtained by merging separately at each level, and the child merging interval is determined after the parent merging interval does not meet the merging conditions; and merging the page table query request into the target request merging group corresponding to the target merging interval if the attribute information of the target merging interval matches the hierarchy attribute of the page table query request.

Root trusted client memory page management is described. The root trusted client is loaded and authenticated by the hardware platform. The root trusted client is configured to manage memory operations of different clients via special permissions that allow it to perform memory operations using clients' private memory pages. To this end, the client page table includes a novel "T bit" in each entry, indicating whether the root trusted client or a different client owns the associated memory page. Each entry in the root trusted client's client page table additionally includes a "C bit," indicating whether the corresponding memory page is a protected page. The combined C and T bit values ​​of the page table entry indicate whether the operation performed as part of processing a client's memory request is offloaded from the hardware platform to the root trusted client.

The application relates to the technical field of data processing, and discloses a computing power server system layer optimization method and system for a high-load scene. The method comprises the following steps: collecting micro-performance indexes such as CPU instruction cycle numbers and page table missing times, constructing a three-layer causal directed acyclic graph through Granger causality test, reducing a parameter search space based on a bottleneck node reverse backtracking, and generating an interpretable optimization decision with a causal path and contribution quantification, so as to solve the problems that an existing technology cannot accurately locate a performance bottleneck root cause and an optimization result lacks transparency. The application performs bottleneck node reverse backtracking and parameter space pruning based on a causal graph, and solves the problems that the existing technology cannot accurately locate the performance bottleneck root cause and blind exploration of the parameter space leads to low optimization efficiency.