565 results about "Page table" patented technology

The invention discloses a memory access method, a program product, equipment and a medium, and relates to the technical field of computers, firmware is utilized to determine to-be-reserved physical memory information, the to-be-reserved physical memory information is analyzed and continuously split to obtain physical memory segments, and the physical memory segments are divided and aligned; dividing the virtual address space, and performing alignment processing on the divided virtual address space; performing memory mapping on the processed physical memory segment and a physical address space corresponding to the processed virtual address space; generating a page table by utilizing a physical address space corresponding to the mapped and processed virtual address space; when an access instruction of a user is obtained, the corresponding target physical address space is screened from the page table to determine the mapped target physical memory segment, so that the user accesses the target physical memory segment based on the user mode process, the range and capacity of the memory segment are dynamically configured, the stability of the memory during key load operation is guaranteed, and the memory access performance is improved.

The invention relates to the field of computer vision, and particularly provides a table recognition reconstruction method and system, a terminal and a medium, and the method comprises the steps: firstly decomposing a large-size table image into a plurality of overlapped sub-images, and carrying out the table structure detection and OCR character recognition of each sub-image through parallel recognition; then, sub-graph recognition results are integrated through a coordinate mapping and confidence coefficient weighted fusion algorithm, and boundary errors are eliminated; then, automatically distinguishing common cells based on an area clustering algorithm, merging the cells and a header region, and reconstructing a complete table logic structure; further understanding header semantics through a natural language model and repairing identification errors; and finally, realizing intelligent splicing and standardized output of the cross-page table. According to the method, the memory limitation of the traditional OCR technology is broken through, an oversized table can be processed, the recognition accuracy of a complex structure is improved, and the digitization efficiency of professional documents such as financial statements and engineering drawings is improved.

The invention discloses a large language model low-delay reasoning method based on dynamic reasoning graph optimization, and provides a low-delay reasoning method based on dynamic reasoning graph optimization. Constructing a template inference graph which can be rewritten and replayed, and establishing a template library according to input shape vectors; during reasoning, a template is matched with a distance threshold value, and only the attention / feedforward sub-graph is locally recaptured when the distance threshold value exceeds the threshold value; executing a forward execution graph, injecting a key value cache page pointer, numerical value precision and an adapter identifier, and performing playback; dividing the pre-filling and decoding sub-graphs to implement graph-level scheduling; switching the key operator when the key operator operates between a standard / fast kernel and different precisions; page-level backspacing of speculative branches is achieved through a shadow page table and reference counting, and batch and template selection is adjusted in a self-adaptive mode based on online indexes; compared with the prior art, the method has the advantages that the recapture and start overhead is reduced, tail delay and jitter are inhibited, and the hardware utilization rate and the service stability are improved.

According to the system memory management method and system, the electronic equipment and the storage medium provided by the invention, the virtual address information in the access information is extracted, and the virtual address information comprises the target virtual address; under the condition that the target virtual address is determined to be in a first preset virtual address range according to the virtual address information, determining an initial physical address corresponding to an initial virtual address in the first preset virtual address range according to a preset address mapping table; performing physical address calculation processing according to the target virtual address, the initial virtual address and the initial physical address to obtain a target physical address corresponding to the target virtual address; and accessing a system memory based on the target physical address and performing memory management on the system memory. By quickly returning the conversion relation from the virtual address to the physical address in the specified range, the conversion efficiency from the virtual address to the physical address can be improved, a conversion page table does not need to be configured according to MMU granularity, waste of storage space can be reduced, and the address conversion efficiency can be improved.

The invention provides a multi-level page table traversal acceleration method, system and device and a medium, and belongs to the technical field of computers. The method comprises the following steps: inputting a virtual address into a path predictor and a dynamic weight hierarchical cache, and collecting an instruction access proportion, a TLB hit rate and a pre-fetching success rate in real time; performing hash calculation according to a preset bit of the virtual address through a path predictor, and querying a historical record table to obtain a prediction path and a confidence level so as to determine a query range; when the cache is hit, scores of hit entries are calculated, priority ranking and elimination decision making of the cache entries are carried out, and meanwhile, the cache entries are managed by adopting a hybrid replacement algorithm; under a preset condition, starting a prefetch operation through an adaptive prefetch engine, calculating and dynamically expanding a prefetch step length, and preventing memory bandwidth contention through two-stage monitoring; when the instruction access proportion, the TLB hit rate and the prefetching success rate meet conditions, an instruction priority mode is activated, and scores of hit entries are updated by adjusting related calculation parameters.

The invention relates to the technical field of computer system structures and storage, in particular to a non-volatile memory quick recovery method based on metadata priority and on-demand loading. The method comprises the following steps: in response to a system fault signal detected by a voltage monitoring unit, freezing a processor context and traversing a page table structure to extract system configuration information; writing the system configuration information and business data codes in the volatile memory into a nonvolatile medium to generate a persistent state mirror image; analyzing the persistent state mirror image, extracting address conversion metadata, and reconstructing a mapping relation from a virtual address to a physical page frame in a volatile memory; and generating an address mapping table, wherein the physical page frame pointed by the address mapping table is set to be in an existing state but is not associated with the effective service data. According to the method, decoupling of the control flow and the data flow is realized by constructing a virtual ready state, and quick starting of the system and immediate response of key services are realized on the premise of not depending on the total capacity of a memory.

The invention relates to the technical field of GPUs, in particular to a GPU virtualization video memory management method and device, a storage medium and a program product. The method comprises the steps that a virtual machine transmits a page table root address corresponding to a target application program running in the virtual machine to a host machine; the virtual machine calls the non-memory operation type API in response to the target application program, intercepts calling of the non-memory operation type API and forwards the calling to the host machine; and in the host machine, accessing a video memory area corresponding to a target application program based on the page table root address through the drive of the non-memory operation type API, executing an instruction of the non-memory operation type API, and returning a processing result of the instruction of the non-memory operation type API to the virtual machine. According to the method and the device, the rear-end driver in the host machine can directly access the video memory resources allocated by the virtual machine, so that the resource utilization rate and the task execution efficiency are improved.

The invention relates to a memory management method and device applied to a server-free data center, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: in response to a virtual memory application instruction, performing virtual memory allocation in a local computing resource pool to obtain a virtual address space; in response to the virtual address access instruction, acquiring cache information of the computing resource pool, and triggering missing page interruption under the condition that data corresponding to the virtual address is not hit in the cache information; the cache information comprises locally cached cache data and page table information; acquiring physical memory resources in a memory resource pool according to the virtual address and the page table information under the condition of triggering missing page interruption of the anonymous page; and updating the page table information and the cache information according to the physical memory resources. By adopting the method, the processing delay of the data center can be reduced while the decoupled memory management logic is used for improving the resource utilization rate.

The invention provides a hot upgrade method for a virtual machine monitor (VMM), which comprises the following steps of: pausing the operation of a virtual machine, storing state information of an original VMM, and reserving a kernel-based virtual machine KVM extension page table and a memory management structure of the original VMM; reserving a page global directory and a virtual memory area VMA corresponding to a virtual machine RAM area according to the memory management structure, and refreshing a process address space described by the memory management structure into a new VMM execution program so as to complete switching of the original VMM into the new VMM; and executing the new VMM, recovering the state information to the new VMM, and inheriting the KVM extension page table by the new VMM to recover the operation of the virtual machine. The invention further provides computer equipment, a computer readable medium and a computer program product.

The invention discloses a memory access method and device, a storage medium and a program product, and relates to the technical field of memory access, comprising: monitoring memory access information of a target memory; the memory access information comprises a missing page address sequence during memory access, an address distribution characteristic when an address conversion failure event occurs in an address conversion lookaside buffer, a cross-node access event and a virtual memory access frequency; determining corresponding target feature information; the target feature information comprises spatial locality, thermal density, access dispersion and unbalance degree data; and determining a current memory access mode based on the target feature information, and determining a target access strategy from preset memory access strategies configured with different memory page table prefetching rules to access the memory. The memory access feature information is quantified through the memory access information, the corresponding memory access mode is determined, and the corresponding memory page table prefetching rule is executed, so that the traversal delay of the multi-level page table can be reduced, and the memory access performance is improved by fully utilizing the memory bandwidth.

The invention relates to a video memory management method and device, electronic equipment and a storage medium, the method is applied to a GPU drive in a virtual machine, and the method comprises the steps that when it is detected that the remaining amount of a GPU video memory is lower than a set remaining amount threshold value, cold pages in a GPU page table are recognized; wherein the cold page is a page table item which is not accessed in a recent preset time interval; and under the condition that the cold page is a video memory, replacing a physical address corresponding to the virtual address in the cold page to a physical address in a system memory so as to replace video memory data corresponding to the cold page to the system memory. The embodiment of the invention can improve the overall utilization rate of the video memory.

The embodiment of the invention provides a memory management method and device, electronic equipment and a readable storage medium. The method comprises the following steps: based on a client virtual address to be accessed, accessing a page table corresponding to the client virtual address; under the condition that the currently accessed current page table item belongs to the large page table item, determining a client physical memory large page corresponding to the client virtual address as a target physical memory page based on the current page table item; under the condition that the current page table item does not belong to the large page table item, determining a next-level page table item pointed by the current page table item as a new current page table item, and executing the operation of determining the client physical memory large page corresponding to the client virtual address as a target physical memory page based on the current page table item again; obtaining a memory access state of the target physical memory page; if the memory access state represents that the target physical memory page meets the preset memory access requirement, the memory access attribute of the target physical memory page is written into a preset cache table. And the address conversion efficiency of the translator is improved.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

The invention discloses an ARMv8-based virtual machine interrupt through routing method, which comprises the following steps that: a Hypervisor directly routes a physical interrupt to an EL1 through configuration, sets a top page table address of a vCPU (Virtual Central Processing Unit) and a Hypervisor control register at the same time, and sets a vcpudid flag bit for indicating whether the vCPU adopts a virtual interrupt injection mechanism or a physical interrupt through routing mechanism; and judging whether an interrupt through routing condition is met or not so as to determine whether an interrupt through routing mechanism or a virtual interrupt injection mechanism is adopted, periodically judging whether a switching condition is met or not when the interrupt through routing mechanism is adopted, and switching from the interrupt through routing mechanism to the virtual interrupt injection mechanism if the switching condition is met. The method is compatible with two interrupt controller specifications of GICv2 and GICv3, supports the virtual machine and the hypervisor to respectively and independently respond to respective corresponding interrupt requests, and meanwhile, the method has the capability of dynamically switching an interrupt routing mechanism during the system operation period, so that the flexibility of interrupt processing and the expandability of the system are improved.

The embodiment of the invention provides a memory allocation method and device.The method comprises the steps that under the condition that page table page allocation is determined to be conducted on a target page table of a target process, a resource binding mechanism corresponding to the target process is obtained; according to a memory node binding constraint in the resource binding mechanism, determining a target memory node corresponding to the target process, and allocating a page table page for the target page table at the target memory node; when it is determined that the local memory of the target memory node is insufficient, so that the page table page allocation fails, a target physical page in the local memory is migrated to a first remote memory node, and the step of allocating the page table page to the target page table at the target memory node continues to be executed until the page table page allocation succeeds. By forcibly distributing the pages of the page table at the target memory node and combining with an intelligent memory migration mechanism, the performance loss caused by remote access of the page table is fundamentally eliminated.

The invention discloses a heterogeneous memory page migration device and method and a readable storage medium, and relates to the technical field of data processing, the heterogeneous memory page migration device comprises a first computing unit, a migration unit and a memory unit, and the migration unit comprises a communicator and a processor; a communicator configured to receive an address translation request; the processor is configured to transmit page contents of a remote page to a local memory frame according to a remote physical frame number in a first page table item when determining that the target page in the address conversion request is the remote page, and replace the remote physical frame number in the first page table item with a local physical frame number; and the communicator is further configured to return the second page table item to the first computing unit, so that the problem of relatively long time consumption when the computing unit accesses a remote page and triggers a page error in the related technology is solved, and the time consumption for migrating the heterogeneous memory page is saved.

The embodiment of the invention discloses a system startup memory detection method and device, equipment and a storage medium, and the method comprises the steps: calculating the maximum value of a Hypervisor early virtual address mapping range according to the initial address of Hypervisor operation before a final page table takes effect; when the dynamic allocation pool is utilized to allocate the memory page, determining a virtual address range of the allocated memory page by utilizing a base address of the allocated memory page, and detecting whether the virtual address range of the allocated memory page exceeds a maximum value of a Hypervisor early virtual address mapping range or not; and when the maximum value of the Hypervisor early virtual address mapping range is exceeded, outputting an error prompt, and returning a memory error. Compared with a traditional estimation mode, the probability that estimation is inaccurate due to the fact that dynamic allocation changes is reduced, the memory errors can be accurately detected in advance before the system crashes, and a developer can conveniently locate the reason of crashes.

The invention relates to a video memory management method and device, electronic equipment, a storage medium and a program product. The method comprises the steps that a target user memory context corresponding to a target user process is created, and the target user memory context is used for managing a target virtual address space corresponding to the target user process and a target video memory space corresponding to the target user process; for at least two pieces of GPU firmware used for executing a task of the target user process, virtual address subspaces in the target virtual address space are distributed to the at least two pieces of GPU firmware; and for any one of the at least two pieces of GPU firmware, the GPU firmware updates the page table information of the firmware memory context corresponding to the GPU firmware according to the page table information of the target user memory context and the virtual address subspace corresponding to the GPU firmware.

The invention relates to the technical field of computer system structures, in particular to a unified memory and data transmission system and management method for an FPGA heterogeneous platform, and the system comprises a CPU component which is used for detecting and initializing an FPGA component, constructing a globally unified virtual address space view, managing a global page table, maintaining a mapping table, managing PCIe communication and processing exceptions; the FPGA component is used for PCIe DMA data transmission, conversion from a virtual address to a physical address, striped on-chip storage and storage of user acceleration function logic implementation; and the PCIe bus is used for data transmission of the CPU component and the FPGA component. Physical memory resources of the CPU component and the FPGA component are integrated and dynamically mapped to a unified virtual address space in a software and hardware cooperation mode, a simple, safe and flexible unified memory system and management method are provided, and efficient memory management and data transmission between the CPU and the FPGA are achieved.

The invention discloses a memory allocation method and device for a direct access memory device, and relates to the technical field of servers. The method comprises the following steps: in response to a memory access request of a user process, allocating virtual address information to the user process; obtaining a physical address range of the direct access memory device, wherein the physical address range comprises physical address sub-regions corresponding to a plurality of memory channels respectively; establishing an interleaving mapping relationship between the virtual address information and physical address sub-regions corresponding to the memory channels respectively; and writing an interleaving mapping relationship between the virtual address information and the plurality of physical address sub-regions into a page table, and processing a memory access request of the user process according to the interleaving mapping relationship in the page table. The method can improve the memory access speed of the server.

The invention discloses a method for accelerating secure metadata access in a secure memory system, a memory controller and a system, and belongs to the field of secure memory systems, and the method comprises the following steps: when a page table item corresponding to a logic page where data accessed by a processor is located does not hit a TLB, obtaining the page table item from a memory page table, extracting a physical page address from the page table item, and storing the physical page address in a memory; a counter corresponding to a physical page where the data to be accessed is located and a father node of the counter in the integrity tree are prefetched through the physical page address; adding a replacement dirty block address in a miss request sent by the last level of cache, after receiving the miss request containing a field of the replacement dirty block address, executing conventional memory reading and decryption, positioning a counter corresponding to the replacement dirty block address, and performing prefetching by using an idle memory bandwidth; in addition to the secure metadata cache, the prefetching queue is maintained to temporarily store the prefetched metadata. The cache hit rate of the security metadata in the security memory system can be improved, and the performance overhead caused by the cache miss can be reduced.

The embodiment of the invention provides a memory system, a memory controller, a garbage collection method and a storage medium. The method comprises the following steps: acquiring a first bitmap corresponding to a first source data block to an Nth bitmap corresponding to an Nth source data block; n is an integer greater than or equal to 2; obtaining a combined bitmap based on the first bitmap to the Nth bitmap; reading a page table item table according to the combined bitmap; and writing the effective data corresponding to the first source data block to the Nth source data block in the page table entry table into the target data block. According to the garbage collection method, garbage collection operation can be performed on a plurality of source data blocks. And merging the bitmaps corresponding to the plurality of source data blocks to obtain a merged bitmap. And the corresponding page table item table is read through the merged bitmap, so that response delay caused by repeatedly reading the page table item table among the source data blocks is avoided, and the processing efficiency of the whole garbage collection process is improved.

The invention discloses a memory management unit, a processor and a page table caching method, and belongs to the technical field of computers. The memory management unit comprises a cache management module, a conversion backup buffer TLB module and a page table traversal PTW module; the TLB module is configured to cache a page table item; the PTW module is configured to query the page table according to the first virtual address under the condition that the TLB module is queried through the first virtual address and the TLB module is not hit; the cache management module is configured to merge 2n page table entries including a target page table entry to obtain a merged page table entry if the target page table entry corresponding to the first virtual address in the page table is valid and the page size indicated by the target page table entry is smaller than or equal to a merging threshold value; and caching the merged page table entry into a TLB module. The memory management unit provided by the invention can merge the effective page table entries corresponding to the pages smaller than or equal to the merge threshold, so that the utilization rate and hit rate of the TLB module are improved.

Provided in the embodiments of the present disclosure are an address translation method, a fast mapping table construction method, a device, a storage medium and a program product. In an embodiment of the present disclosure, the address translation method comprises: constructing a first RMAP table adapted to an EPT, the first RMAP table storing address information of the last-level page table entry respectively corresponding to at least one GPA in the EPT; establishing a fast mapping relationship from GPAs to HPAs on the basis of first RMAP table so as to implement fast address translation from the GPAs to the HPAs; and further, creating a second RMAP table for the EPT, the second RMAP table storing address translation information from at least one HPA to a corresponding GPA to establish a fast mapping relationship from the HPAs to the GPAs so as to implement fast address translation from the HPAs to the GPAs. Bidirectional fast mapping can be implemented on the basis of the first RMAP table and the second RMAP table, so as to improve address translation efficiency.

The invention belongs to the technical field of artificial intelligence and multi-modal data processing, and provides a cross-page table analysis method and system based on visual and semantic analysis. The method comprises the steps that S1, a table bounding box and row and column lines are obtained through recognition by means of a target detection model and a neural network model; s2, performing visual feature extraction on the table bounding box and the row and column lines obtained through identification, and extracting semantic features between cells; s3, constructing a knowledge graph according to the extracted visual features and semantic features, and judging whether to carry out cross-page header inheritance; s4, for the table inherited by the cross-page header, establishing geometric and semantic association of cross-page cells and performing table reconstruction to obtain a reconstructed table; s5, performing data consistency verification on the reconstructed table; and S6, analyzing and outputting the verified overall table to an interactive interface. According to the method, the accuracy of table fuzzy boundary scene detection and cross-page table recognition can be improved.

The embodiment of the invention provides a data reading method and computing equipment, and the method comprises the steps: under the condition that a process reads a first memory object through a target memory virtual address, if it is recognized that an uncorrectable error fault exists in a first memory, replacing a current page table with a target page table; a first memory object is stored in the first memory; the first memory is located in a physical memory in a main memory of the computing device; the main memory is a local memory; the current page table is used for indicating a mapping relation between the target memory virtual address and the first memory; the target page table is used for indicating a mapping relation between the target memory virtual address and a second memory; the second memory is located in a backup memory; the backup memory is physically isolated from the main memory; reading a second memory object from the second memory based on the target page table; wherein the second memory object is a copy of the first memory object, and according to the embodiment of the invention, the effect of improving the business processing efficiency can be realized.

The invention discloses a compiling optimization device and method supporting Page Attention and a medium, and belongs to the field of compiling optimization devices.The device comprises a multi-core AI accelerator, and each calculation core comprises a tensor component, a vector component, a DMA component and an IMM component; the compiling optimization device is optimized through the following modules: (a) a KV Cache management module, which is used for storing page table items corresponding to different KV Cache blocks according to a batch sequence and generating standardized page table items; (b) a DMA control module which supports a linear reading and remapping mode, carries discrete KV Cache blocks from an external memory to an on-chip weight buffer area in a segmented manner according to an index table, and hides data loading delay by adopting a double-buffer technology; and (c) a multi-batch reasoning scheduling module which dynamically allocates computing resources according to the data scale in a code stage. According to the invention, through deep cooperation of a hardware architecture and functional logic, the problems of low KV Cache management efficiency, complex multi-batch dynamic scheduling and insufficient computing resource utilization rate on an ASIC platform are solved.

Embodiments herein describe a computer architecture including at least one core including a first cache and a second cache, a shared cache, and an accelerator comprising circuitry configured to manage data and instructions transferred between the first and second caches and the shared cache, wherein the accelerator platform is configured to allow an implementation of a user task to perform multi-level prefetching to timely obtain address translation mappings. Address translation mappings are mappings between virtual addresses and physical addresses stored in a page table. The multi-level prefetching includes a first prefetching request (far request), a second prefetching request (near request), and a third prefetching request (now request).

The invention discloses a memory management method, which comprises a two-stage CXL memory sub-page sensing step based on pre-splitting: scanning a large transparent page based on a coarse-grained page table scanning mechanism, determining a large thermally transparent page, and putting the large thermally transparent page into a pre-splitting queue for management; pre-splitting a memory range related to the thermal transparent large page into a plurality of small pages; the page table items of the split small pages are utilized to achieve fine-grained scanning of the page table, and hot pages in the page table are obtained; migrating the hot page to a DDR memory node; and pushing the address area of the transparent large page out of a queue, and updating the page table item of each hot page.

The embodiment of the invention provides a video memory control method, device, equipment and system and a computer storage medium. The method comprises the steps that in response to an obtained drive upgrading request of an image processing unit (GPU), a before-upgrading page table corresponding to the GPU is obtained, and the before-upgrading page table comprises a mapping relation between a physical address and a virtual address of a GPU video memory; determining a data cleaning queue corresponding to the GPU, wherein the data cleaning queue is used for performing global cleaning on data in a GPU video memory; under the condition that the data cleaning queue is locked, driving upgrading operation is carried out on the GPU based on the driving upgrading request, an upgraded page table corresponding to the GPU is obtained, and the upgraded page table comprises a mapping relation between a physical address and a virtual address of a GPU video memory; and regulating and controlling data in the GPU video memory based on the pre-upgrading page table and the post-upgrading page table. In the embodiment of the invention, the driver upgrading operation of the GPU can be realized without operations such as video memory backup, shutdown, restart and the like.