365 results about "Page table" patented technology

The invention relates to the field of computer vision, and particularly provides a table recognition reconstruction method and system, a terminal and a medium, and the method comprises the steps: firstly decomposing a large-size table image into a plurality of overlapped sub-images, and carrying out the table structure detection and OCR character recognition of each sub-image through parallel recognition; then, sub-graph recognition results are integrated through a coordinate mapping and confidence coefficient weighted fusion algorithm, and boundary errors are eliminated; then, automatically distinguishing common cells based on an area clustering algorithm, merging the cells and a header region, and reconstructing a complete table logic structure; further understanding header semantics through a natural language model and repairing identification errors; and finally, realizing intelligent splicing and standardized output of the cross-page table. According to the method, the memory limitation of the traditional OCR technology is broken through, an oversized table can be processed, the recognition accuracy of a complex structure is improved, and the digitization efficiency of professional documents such as financial statements and engineering drawings is improved.

The invention discloses a large language model low-delay reasoning method based on dynamic reasoning graph optimization, and provides a low-delay reasoning method based on dynamic reasoning graph optimization. Constructing a template inference graph which can be rewritten and replayed, and establishing a template library according to input shape vectors; during reasoning, a template is matched with a distance threshold value, and only the attention / feedforward sub-graph is locally recaptured when the distance threshold value exceeds the threshold value; executing a forward execution graph, injecting a key value cache page pointer, numerical value precision and an adapter identifier, and performing playback; dividing the pre-filling and decoding sub-graphs to implement graph-level scheduling; switching the key operator when the key operator operates between a standard / fast kernel and different precisions; page-level backspacing of speculative branches is achieved through a shadow page table and reference counting, and batch and template selection is adjusted in a self-adaptive mode based on online indexes; compared with the prior art, the method has the advantages that the recapture and start overhead is reduced, tail delay and jitter are inhibited, and the hardware utilization rate and the service stability are improved.

The invention relates to the technical field of computer system structures and storage, in particular to a non-volatile memory quick recovery method based on metadata priority and on-demand loading. The method comprises the following steps: in response to a system fault signal detected by a voltage monitoring unit, freezing a processor context and traversing a page table structure to extract system configuration information; writing the system configuration information and business data codes in the volatile memory into a nonvolatile medium to generate a persistent state mirror image; analyzing the persistent state mirror image, extracting address conversion metadata, and reconstructing a mapping relation from a virtual address to a physical page frame in a volatile memory; and generating an address mapping table, wherein the physical page frame pointed by the address mapping table is set to be in an existing state but is not associated with the effective service data. According to the method, decoupling of the control flow and the data flow is realized by constructing a virtual ready state, and quick starting of the system and immediate response of key services are realized on the premise of not depending on the total capacity of a memory.

The invention relates to a memory management method and device applied to a server-free data center, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: in response to a virtual memory application instruction, performing virtual memory allocation in a local computing resource pool to obtain a virtual address space; in response to the virtual address access instruction, acquiring cache information of the computing resource pool, and triggering missing page interruption under the condition that data corresponding to the virtual address is not hit in the cache information; the cache information comprises locally cached cache data and page table information; acquiring physical memory resources in a memory resource pool according to the virtual address and the page table information under the condition of triggering missing page interruption of the anonymous page; and updating the page table information and the cache information according to the physical memory resources. By adopting the method, the processing delay of the data center can be reduced while the decoupled memory management logic is used for improving the resource utilization rate.

The invention relates to a video memory management method and device, electronic equipment and a storage medium, the method is applied to a GPU drive in a virtual machine, and the method comprises the steps that when it is detected that the remaining amount of a GPU video memory is lower than a set remaining amount threshold value, cold pages in a GPU page table are recognized; wherein the cold page is a page table item which is not accessed in a recent preset time interval; and under the condition that the cold page is a video memory, replacing a physical address corresponding to the virtual address in the cold page to a physical address in a system memory so as to replace video memory data corresponding to the cold page to the system memory. The embodiment of the invention can improve the overall utilization rate of the video memory.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

The embodiment of the invention provides a memory allocation method and device.The method comprises the steps that under the condition that page table page allocation is determined to be conducted on a target page table of a target process, a resource binding mechanism corresponding to the target process is obtained; according to a memory node binding constraint in the resource binding mechanism, determining a target memory node corresponding to the target process, and allocating a page table page for the target page table at the target memory node; when it is determined that the local memory of the target memory node is insufficient, so that the page table page allocation fails, a target physical page in the local memory is migrated to a first remote memory node, and the step of allocating the page table page to the target page table at the target memory node continues to be executed until the page table page allocation succeeds. By forcibly distributing the pages of the page table at the target memory node and combining with an intelligent memory migration mechanism, the performance loss caused by remote access of the page table is fundamentally eliminated.

The invention discloses a memory allocation method and device for a direct access memory device, and relates to the technical field of servers. The method comprises the following steps: in response to a memory access request of a user process, allocating virtual address information to the user process; obtaining a physical address range of the direct access memory device, wherein the physical address range comprises physical address sub-regions corresponding to a plurality of memory channels respectively; establishing an interleaving mapping relationship between the virtual address information and physical address sub-regions corresponding to the memory channels respectively; and writing an interleaving mapping relationship between the virtual address information and the plurality of physical address sub-regions into a page table, and processing a memory access request of the user process according to the interleaving mapping relationship in the page table. The method can improve the memory access speed of the server.

The invention discloses a method for accelerating secure metadata access in a secure memory system, a memory controller and a system, and belongs to the field of secure memory systems, and the method comprises the following steps: when a page table item corresponding to a logic page where data accessed by a processor is located does not hit a TLB, obtaining the page table item from a memory page table, extracting a physical page address from the page table item, and storing the physical page address in a memory; a counter corresponding to a physical page where the data to be accessed is located and a father node of the counter in the integrity tree are prefetched through the physical page address; adding a replacement dirty block address in a miss request sent by the last level of cache, after receiving the miss request containing a field of the replacement dirty block address, executing conventional memory reading and decryption, positioning a counter corresponding to the replacement dirty block address, and performing prefetching by using an idle memory bandwidth; in addition to the secure metadata cache, the prefetching queue is maintained to temporarily store the prefetched metadata. The cache hit rate of the security metadata in the security memory system can be improved, and the performance overhead caused by the cache miss can be reduced.

The invention belongs to the technical field of artificial intelligence and multi-modal data processing, and provides a cross-page table analysis method and system based on visual and semantic analysis. The method comprises the steps that S1, a table bounding box and row and column lines are obtained through recognition by means of a target detection model and a neural network model; s2, performing visual feature extraction on the table bounding box and the row and column lines obtained through identification, and extracting semantic features between cells; s3, constructing a knowledge graph according to the extracted visual features and semantic features, and judging whether to carry out cross-page header inheritance; s4, for the table inherited by the cross-page header, establishing geometric and semantic association of cross-page cells and performing table reconstruction to obtain a reconstructed table; s5, performing data consistency verification on the reconstructed table; and S6, analyzing and outputting the verified overall table to an interactive interface. According to the method, the accuracy of table fuzzy boundary scene detection and cross-page table recognition can be improved.

The invention discloses a memory management method, which comprises a two-stage CXL memory sub-page sensing step based on pre-splitting: scanning a large transparent page based on a coarse-grained page table scanning mechanism, determining a large thermally transparent page, and putting the large thermally transparent page into a pre-splitting queue for management; pre-splitting a memory range related to the thermal transparent large page into a plurality of small pages; the page table items of the split small pages are utilized to achieve fine-grained scanning of the page table, and hot pages in the page table are obtained; migrating the hot page to a DDR memory node; and pushing the address area of the transparent large page out of a queue, and updating the page table item of each hot page.

The embodiment of the invention provides a video memory control method, device, equipment and system and a computer storage medium. The method comprises the steps that in response to an obtained drive upgrading request of an image processing unit (GPU), a before-upgrading page table corresponding to the GPU is obtained, and the before-upgrading page table comprises a mapping relation between a physical address and a virtual address of a GPU video memory; determining a data cleaning queue corresponding to the GPU, wherein the data cleaning queue is used for performing global cleaning on data in a GPU video memory; under the condition that the data cleaning queue is locked, driving upgrading operation is carried out on the GPU based on the driving upgrading request, an upgraded page table corresponding to the GPU is obtained, and the upgraded page table comprises a mapping relation between a physical address and a virtual address of a GPU video memory; and regulating and controlling data in the GPU video memory based on the pre-upgrading page table and the post-upgrading page table. In the embodiment of the invention, the driver upgrading operation of the GPU can be realized without operations such as video memory backup, shutdown, restart and the like.

The invention discloses a memory fault processing method and device during writing, a terminal and a storage medium, and belongs to the field of memorys.The method comprises the steps that when a memory unrecoverable fault processing method is executed, whether a memory synchronization fault exists or not is judged, and when the memory synchronization fault exists, context register information of an interrupted process is obtained, and a value of a program counter is obtained; determining an address of the interrupted instruction, reading a binary code corresponding to the interrupted instruction based on the address of the interrupted instruction, and analyzing an operation code in the binary code; determining whether the currently interrupted process is in a write operation stage or not according to the analysis result of the operation code, and when the currently interrupted process is in the write operation stage, determining that a memory fault occurs during writing; when anonymous mapping is carried out, a new physical page frame is distributed, and the new physical page frame is used for replacing an original faulty physical page frame; determining all page table items related to the original fault physical page frame; and replacing the original information in all the page table entries with new physical page frame information.

The invention relates to the technical field of data processing, and discloses a computing power server system layer optimization method and system oriented to a high-load scene. The method comprises the steps of collecting micro performance indexes such as the CPU instruction cycle number and the page table missing frequency, constructing a three-layer causal directed acyclic graph through Granger causal inspection, reducing a parameter search space based on bottleneck node reverse backtracking, generating an interpretable optimization decision with a causal path and contribution degree quantification, and carrying out optimization on the basis of the interpretable optimization decision. The problems that the performance bottleneck root cause cannot be accurately positioned and the optimization result lacks transparency in the prior art are solved. According to the method, bottleneck node reverse backtracking and parameter space pruning are performed based on the causal atlas, so that the problem of low optimization efficiency caused by incapability of accurately positioning a performance bottleneck root cause and blind exploration of a parameter space in the prior art is solved.

Provided in the embodiments of the present disclosure are an address translation method and apparatus, and an electronic device and a storage medium. The address translation method is applied to an address translation apparatus, the apparatus comprising multiple sets of translation lookaside buffers, wherein each of the multiple sets of translation lookaside buffers is configured to store page table information for translating a virtual address into a physical address. The address translation method comprises: in response to obtaining a first virtual address translation request, determining a target translation lookaside buffer from multiple sets of translation lookaside buffers on the basis of a first mapping algorithm, wherein the first virtual address translation request comprises an object virtual address; and accessing page table information in the target translation lookaside buffer, in order to translate the object virtual address into an object physical address. The method further comprises: acquiring access frequency information for each of the multiple sets of translation lookaside buffers; on the basis of the access frequency information, determining whether the first mapping algorithm is required to be updated; and in response to the first mapping algorithm being required to be updated, updating the mapping algorithm to a second mapping algorithm.

The invention relates to the technical field of storage control, in particular to a memory control method, a storage device, a medium and computer equipment, a three-level index structure is arranged, only a first-level root table resides in a cache, an index is rapidly extracted through bit operation so as to reduce cache occupation and invalid IO overhead, the search range is narrowed through a hash bucket of a three-level page table, and the search efficiency is improved. Conflicts are solved through a linked list, and the mapping efficiency and the system stability can be improved through a fixed structure; and the second-level block table and the third-level page table are loaded in a non-blocking manner without occupying a CPU, so that the bandwidth is saved, and the concurrency performance and the cache hit rate are improved. Through the overall scheme of three-level index, chained hash table, loading on demand and bit operation, the delay of the whole process from logic address input to physical address output is remarkably reduced, and the low delay requirement of a high-performance storage system is met; the three-level index structure supports flexible adjustment of the sizes of a root table, a block table and a page table, adapts to storage devices with different capacities, and has good expandability.

The invention relates to an image rendering method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the steps of receiving rendering information; the rendering information is generated when the graphic application sends a rendering request; analyzing the rendering information, and creating a graphic task; the graphic task comprises a plurality of cache objects; the cache object is used for storing image data in the rendering process; the cache object carries a virtual address; when the physical space is allocated to each cache object, mapping the virtual address of each cache object to a physical address to obtain a page table mapping relation; generating a to-be-written page table item based on the page table mapping relation of each cache object, and sending the to-be-written page table item to the GPU; and the GPU writes the page table mapping relation into the corresponding page table item according to the to-be-written page table item so as to establish an access path between the GPU and the physical address, and the GPU executes the graphic task based on the access path. By adopting the method, the mapping efficiency can be improved.

The present application discloses a memory management method and an electronic device. The method is executed by an electronic device. In the method, a hardware accelerator detects a first event, the first event indicating that the probability of a page fault occurring in a first DMA memory used by a first application is greater than a first threshold; in response to the first event, the hardware accelerator performs one or more of the following operations: checking and killing a first process of the first application; and writing first data of the first application in a disk into the first DMA memory, and updating a first memory page table, the first memory page table comprising a mapping of a virtual address on the hardware accelerator side to a physical address on the first DMA memory side. During implementation of the present application, the hardware accelerator can handle a page fault that may occur in the DMA memory, thereby improving efficiency of memory management.

A neural processing device and a method for using shared page table thereof are provided. The neural processing device including at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to exchange data between the at least one neural processor and the shared memory, comprises at least one processing unit each of which included in each of the at least one neural processor and configured to provide logical addresses, a memory management unit configured to receive and translate the logical addresses into physical addresses, and a physical memory accessible by the physical addresses, wherein the memory management unit comprises a shared page table that has translation information between the logical addresses and the physical addresses and is shared by at least one process with each other.

The embodiment of the invention relates to the technical field of memory management, and provides a container memory protection method and device, electronic equipment and a medium. A pointer authentication code is embedded into a pointer to be accessed to obtain an authentication pointer with authentication information, and the pointer authentication code is generated according to the pointer and context information of the first access request; extracting a pointer authentication code from the authentication pointer, and verifying the authentication pointer based on the pointer authentication code; and when the verification is passed, temporarily inserting a mapping item which allows access to the memory of the target container in an expansion page table allocated for the target container, and performing access control on the memory of the target container through the mapping item. Consequently, container memory protection with light weight and low performance influence is achieved.

A data processing system (DPS) uses platform protection technology (PPT) to protect some or all of the code and data belonging to certain software modules. The PPT may include a virtual machine monitor (VMM) to enable an untrusted application and a trusted application to run on top of a single operating system (OS), while preventing the untrusted application from accessing memory used by the trusted application. The VMM may use a first extended page table (EPT) to translate a guest physical address (GPA) into a first host physical address (HPA) for the untrusted application. The VMM may use a second EPT to translate the GPA into a second HPA for the trusted application. The first and second EPTs may map the same GPA to different HPAs. Other embodiments are described and claimed.

The invention provides a memory management method, a memory management unit, a chip and electronic equipment. The memory management method comprises the following steps: receiving a command from main equipment; matching the command with a tag array to obtain a matching result; if matching succeeds, corresponding read address information is generated according to the hit tag, a first memory is accessed according to the read address information to obtain corresponding cache line page table information, and the virtual address information is converted into physical address information according to the cache line page table information; and if the matching fails, initiating a page table reading command for accessing the second memory to obtain corresponding page table information according to the command, obtaining replacement cache line information corresponding to the page table information in the first memory, writing the page table information into the first memory according to the replacement cache line information, and updating the tag array. According to the method, the cache line replacement strategy is preset, so that the hit rate of the page table is increased, and the power consumption and the area of the IOMMU are effectively reduced while the high-performance application requirement is met.

A system-on-chip and an operation method of the system-on-chip are provided. The system on chip includes: a translation lookaside buffer (TLB) storing a portion of address translation information for translating between a virtual address and a physical address; a core executing the instruction and accessing the TLB; a page table traversal unit that performs a page table traversal operation of searching for a page table storing address translation information; and a static page management (SPM) circuit that, when a physical address is obtained from a virtual address included in static address translation information corresponding to a static page among the address translation information, stops an access to check the TLB or stops a page table traversal operation.

In order to solve the problem that under the condition that a PMON program is not changed, the PMON program cannot provide inter-core memory isolation through two addresses of 0 * 8000000000000000 and 0 * 9000000000000000 configured by a direct mapping configuration window, the AMP architecture multi-core real-time operating system deployment method capable of meeting the inter-core memory isolation is designed on a Loongson platform. According to the multi-core deployment method for the AMP architecture operating system based on the Loongson platform disclosed by the invention, by designing a secondary bootstrap program, the mode that a PMON program directly loads an operating system mirror image is changed into the mode that the secondary bootstrap program is firstly loaded, and the operating system is started by the secondary bootstrap program. The secondary bootstrap program configures the MMU through a page table mapping address translation mode, so that operating systems between different cores can run in different address spaces, and an isolated running environment is provided. Once a certain operating system accesses the address space of other core operating systems, the system will report TLB refilling exceptions to prevent other core memories from being damaged, and therefore the inter-core memory isolation is achieved.

Various aspects relate to a memory system including: a memory configured to store respective page data for each of a plurality of pages; a non-volatile first-in first-out, FIFO, buffer; a controller configured to carry out a checkpoint operation in response to a checkpoint command; a storage configured to store a page table including a page table entry for each page, the page table entry indicating whether the page was updated after receiving the checkpoint command; the checkpoint operation including: generating a page table copy of the page table; in response to receiving data that are to be written to a page, if, in the page table copy, the page table entry of the page indicates that the page was not updated: storing the data in the hardware FIFO buffer, generating a page data copy of the page data of the page, and merging the data with the page data copy.

The embodiment of the invention provides a memory control method, computing equipment, a storage medium and a program product. The method comprises the steps of obtaining a heap expansion request for a heap memory of an application program; in response to the heap expansion request, allocating a virtual memory page with a large page size for the application program based on the heap memory; wherein the initial address of the virtual memory page is aligned according to the size of the large page; the virtual memory page is used for mapping to a physical memory page corresponding to the large page size, and generating a page table item according to a mapping result. According to the technical scheme provided by the embodiment of the invention, the virtual memory page with the large page size is allocated, and the initial address of the virtual memory page is aligned according to the large page size, so that the system performance is effectively improved, and the memory access efficiency is improved.

A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

The application is suitable for the technical field of processors, and particularly relates to a random generation method and system of address mapping relationship and related equipment. The method comprises the following steps: establishing a virtual address space, a guest physical address space and a real physical address space; randomly allocating address segments to the virtual address space, the guest physical address space and the real physical address space according to an address start position and an address segment length of external parameters; obtaining a paging mode configuration of a current computer system, and constraining the virtual address space and the guest physical address space according to the paging mode configuration; establishing a random mapping relationship among the virtual address space, the guest physical address space and the real physical address space according to the paging mode configuration, and obtaining an address mapping result. Compared with the prior art, the application can quickly and randomly generate a one-level or two-level address mapping relationship without constructing a complete set of page tables on the basis of meeting the paging rules defined in the RISC-V specification.

The invention provides a knowledge base retrieval method and device based on a page type storage architecture, and relates to the technical field of artificial intelligence, and the method comprises the following steps: receiving a knowledge retrieval request sent by a current large model; matching a semantic vector corresponding to the knowledge retrieval request with a semantic vector of each knowledge block in a page table, and determining memory block numbers and page numbers of a plurality of target knowledge blocks; reading each target knowledge block in the memory based on the memory block number of each target knowledge block, and combining each target knowledge block based on the page number of each target knowledge block to generate a knowledge retrieval result corresponding to the knowledge retrieval request; and sending a knowledge retrieval result to the current large model. According to the method and the device provided by the invention, through an innovative index construction mode and a retrieval mechanism, in combination with a page type storage architecture and a vector distance retrieval technology, the knowledge acquisition efficiency of a large model is improved, efficient processing, rapid retrieval and flexible updating of knowledge data are realized, and the overall performance of a knowledge base is improved.

The present application relates to a kind of file cross-page table restoration method and device, belong to data processing technical field, by column topological feature matching and line index benchmark offset algorithm, realize the seamless logical reorganization of physical fragmentation table in global data structure, restore the logical continuity of business data;Adaptive modal shunt mechanism is constructed, accurately distinguish electronic and visual modal and call exclusive processing path, avoid the waste of computing power and secondary error caused by blindly calling visual model;Strong geometric constraint processing is applied to the preliminary extraction result of double-path heterogeneous, which is forced to be normalized to standard closed physical grid structure, greatly enhance the robustness of system to deal with complex layout such as broken line and dashed line, decouple the front-end extraction mode and the spatial logic mapping of rear end, significantly reduce the engineering integration difficulty of system, so as to realize the high-quality, automated restoration of complex cross-page table in mixed document scene.