1532 results about "Memory address" patented technology

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

A generative artificial intelligence (AI) system includes a generative AI model configured to generate outputs based on a training data set. The AI system additionally includes a secure data vault system. The secure data vault system additionally includes a sandbox system storing the generative AI model and operatively coupled to the generative AI model to send inputs to generate the outputs from the generative AI model, wherein the sandbox system comprises an execution environment configured to restrict execution of the generative AI model to a predefined memory address range. The secure data vault system further includes a secure network service communicatively coupled to the sandbox system and configured to authenticate a connection to an external system and to download from the external system an update package for the generative AI model when the connection is authenticated.

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

The invention relates to the technical field of network communication, and discloses a vehicle-mounted edge computing data recording system and method based on protocol adaptive analysis, and the system comprises a multi-protocol network access controller which is used for capturing an original data frame and extracting a physical feature triple; the identification analysis engine is used for executing hash operation on the triple to generate a physical feature code and retrieving a physical logic address mapping table; the direct memory access controller is used for responding to a target memory address pointer hit by retrieval and directly writing a data load into an input buffer area of the functional operation module, and by constructing a direct addressing mechanism based on Hash mapping, thorough decoupling of vehicle-mounted heterogeneous network physical topology and edge computing logic is achieved.

The embodiment of the invention provides a memory access method and device, electronic equipment and a readable storage medium. The method comprises the following steps: receiving a cache line access request; extracting label information from a target memory address corresponding to the cache line access request, wherein the label information comprises a shared label, a private label, a group index, inter-block offset and intra-block offset; querying whether the cache line access request hits the L1 cache or not based on the label information; the group index is used for determining a target group, the shared tag and the private tag are used for determining a target cache line in the target group, and the inter-block offset is used for determining a target cache block in the target cache line; and if the cache line access request hits the L1 cache, determining a target data position in a hit target cache block based on the in-block offset, and executing a corresponding memory access request based on the target data position. According to the embodiment of the invention, on the basis of ensuring the data access efficiency, the storage space of the cache line is fully utilized, and the waste of the cache space is reduced.

A method includes receiving a machine learning (ML) network model in high-level code; generating an internal representation (IR), the IR is mapped to components in a multi-processing tile device; determining whether a first processing tile with a first on-chip memory (OCM) has a same dimension for an input / output tensor data as a second processing tile with a second OCM performing a same primitive function based on the IR; allocating a same memory address range within the first and the second OCM for the same primitive function if the first processing tile has the same dimension for the input / output tensor data as the second processing tile for the same primitive function; linking the memory address range of the first OCM to the memory address range of the second OCM to form a grouped memory space within the first and the second OCM respectively; and compiling low-level instructions based on the linking.

The invention relates to a matrix storage operator optimization method and device, computer equipment and a readable storage medium. The method comprises the following steps: allocating memory resources for target data; determining a logic structure corresponding to the source data, establishing a first mapping relation between each logic index in the logic structure and a register address of the source data, and establishing a second mapping relation between each logic index in the logic structure and a memory address of the target data; and determining a corresponding relationship between a memory address of the target data and a register address of the source data based on the first mapping relationship and the second mapping relationship, and storing the source data stored in a register into a memory resource corresponding to the target data based on the corresponding relationship. By adopting the method, the generalization ability of the matrix storage operator can be improved.

The invention discloses a memory partition-based dynamic instruction conversion memory access conflict optimization method, which comprises the following steps of: allocating memory sub-regions for each computing core according to a load condition in an ARM (Advanced RISC Machines) many-core system to establish a first mapping relation table; when the executable file is loaded and executed in a dynamic instruction conversion mode, obtaining a second mapping relation table between the thread and the calculation core, and obtaining a thread and a memory address corresponding to a to-be-converted instruction of a memory access instruction class, obtaining a converted first ARM virtual address and a related first address space according to the first mapping relation table and the second mapping relation table, and determining an adjustment mode of the converted instruction according to the relation between the first ARM virtual address and the first address space to complete instruction conversion. The memory access conflict in the dynamic conversion process from the x86 instruction to the ARM instruction on an ARM many-core system is effectively reduced, and the execution performance of a program after dynamic instruction conversion is improved.

The invention provides a DPU (Data Processing Unit)-based RDMA (Remote Direct Memory Access) virtualized memory address conversion and data transmission method and a DPU-based RDMA virtualized memory address conversion and data transmission system. The method comprises the following steps that: a user process specifies a client virtual address and a corresponding memory The virtual machine kernel generates a first memory conversion table, and the first memory conversion table records conversion from the client virtual address to the client physical address. When the drive program of the remote direct memory access device obtains the first memory conversion table, a preset instruction is triggered to enable the execution control right to be switched to the virtual machine supervision program from the virtual machine kernel. The customer physical address is converted into the host virtual address in the switching process. The virtual machine supervision program obtains mapping from the host virtual address to the host physical address through the host system information, and a second memory conversion table containing the conversion relation from the client virtual address to the host physical address is obtained. The execution control right is switched back to the kernel of the virtual machine, and the second memory conversion table is configured to the remote direct memory access device DPU. According to the method, address conversion can be simplified, hardware dependence is reduced, and RDMA performance is improved.

The invention provides a CPU scheduling method and related equipment, and relates to the technical field of computers. The method comprises the following steps: in response to execution of a load process, sampling a last-stage cache failure event of the load process to obtain a memory access hotspot address corresponding to the load process; wherein the last-stage cache failure event is related to a memory access address, and the memory access hotspot address is a first memory address of which the memory access frequency is greater than a first preset threshold value; determining a CPU corresponding to the memory access hotspot address as a first CPU candidate set of the load process; in the first CPU candidate set, determining a target CPU of the load process; and adding the load process into the process scheduling queue of the target CPU. According to the method and the device, the hotspot address is identified by sampling the last-stage cache failure event, the candidate set and the target CPU are determined, the load process is enabled to preferentially run on the CPU with high affinity with the memory hotspot, and the load performance can be effectively improved under a non-uniform cache architecture.

Systems and methods are provided. A system includes a display and camera. The system additionally includes a secure data vault system. The secure data vault system includes a sandbox system operatively coupled to the camera and configured to receive camera data from the camera, wherein in operation of the sandbox system, the camera only sends camera data to the sandbox system, and wherein the sandbox system comprises an execution environment configured to restrict execution of instructions to a predefined memory address range. The secure data vault system additionally includes a display and rendering system operatively coupled to the sandbox system and configured to render an image based on the camera data processed via the instructions and to display the image via the display, wherein the display and rendering system is configured to blur sections of the image based on private information derived from the image.

An apparatus is described having processing circuitry to perform vector processing operations, a set of vector registers, and an instruction decoder to decode vector instructions to control the processing circuitry to perform the required operations. The instruction decoder is responsive to a given vector memory access instruction specifying a plurality of memory access operations, where each memory access operation is to be performed to access an associated data element, to determine, from a data vector indication field of the given vector memory access instruction, at least one vector register in the set of vector registers associated with a plurality of data elements, and to determine, from at least one capability vector indication field of the given vector memory access instruction, a plurality of vector registers in the set of vector registers containing a plurality of capabilities. Each capability is associated with one of the data elements in the plurality of data elements and provides an address indication and constraining information constraining use of that address indication when accessing memory. The number of vector registers determined from the at least one capability vector indication field is greater than the number of vector registers determined from the data vector indication field. The instruction decoder controls the processing circuitry: to determine, for each given data element in the plurality of data elements, a memory address based on the address indication provided by the associated capability, and to determine whether the memory access operation to be used to access the given data element is allowed in respect of that determined memory address having regard to the constraining information of the associated capability; and to enable performance of the memory access operation for each data element for which the memory access operation is allowed.

The invention relates to the technical field of SOC chips, and discloses an efficient memory management method and system based on an SOC chip, which are used for constructing a complete topological graph and calculating access delay distribution by comprehensively analyzing an internal physical structure of the chip. According to the method, the memory access behavior of each processing core is monitored in real time, dynamic memory partitioning is executed according to the access characteristics and the physical topological structure, and the optimal access area is distributed for the processing core. And when an access hot spot is detected, triggering a data migration mechanism to copy hot spot data to a relatively close memory area. According to the method, a memory address space is recombined by adopting a topology-aware address mapping algorithm, a multi-level cache collaboration mechanism is established, and the working mode of a memory controller is dynamically adjusted according to an application type. Through load balancing monitoring and periodic memory recombination, the memory access delay is effectively reduced, the bandwidth utilization rate is improved, and the overall memory access performance of the SOC chip is optimized.

The invention relates to the technical field of artificial intelligence, and provides a tensor management method, electronic equipment, a storage medium and a program product.The method comprises the steps that based on attribute information of tensors needed by a current operator, whether a corresponding tensor queue exists or not is searched from a tensor pool, and instance objects of all the tensors are stored in the tensor queue; under the condition that the corresponding tensor queue exists in the tensor pool, based on the storage sequence of each tensor in the tensor queue, extracting a target tensor from the tensor queue; and based on the current operator, using the target tensor to participate in model training, and automatically putting the target tensor back to the tensor queue after the use is completed. According to the method, the tensor pool and the tensor queue are introduced, so that the tensor can be taken out from the queue when the tensor is used and can be automatically put back into the queue after the tensor is used, an operator can obtain the tensor of the same memory address in each iteration of model training, and the performance of model training is improved.

The invention relates to an optimization method of a data type conversion operator, computer equipment, a readable storage medium and a computer program product. The method comprises the following steps: allocating memory resources for target data; establishing a read mapping relationship between each logic index in the logic structure of the source data and the memory address of the source data, and establishing a write mapping relationship between each logic index in the logic structure and the memory address of the target data; traversing the logic structure, aiming at any traversed logic index, determining a read address corresponding to the logic index based on the read mapping relationship, performing data reading from the memory resource corresponding to the source data based on the read address, converting the read data element from the first data type to the second data type, and storing the converted data element in the memory resource. And writing the data elements subjected to data type conversion into memory resources corresponding to the target data according to the write mapping relationship. By adopting the method, the calculation capability of the data type conversion operator can be improved.

The invention relates to the technical field of computers, in particular to an incentive generation method and device and a medium, and the incentive generation method comprises the following steps: distributing a first number of multiple physical addresses, and distributing a second number of multiple page table entry addresses; for each virtual address in a third number of virtual addresses needing to be generated, selecting a corresponding target physical address from the plurality of physical addresses and selecting at least one target page table entry address for the target physical address from the plurality of page table entry addresses, determining page table item data and storing the page table item data in a target page table item to generate a corresponding virtual address; and generating excitation for verifying the memory management unit. According to the excitation generation method and device disclosed by the embodiment of the invention, the medium can realize dynamic simulation of flexible allocation of the memory address, strengthen randomized verification of the address and improve the verification coverage rate of the mapping relationship between the page table entries at all levels.

The embodiment of the invention provides a memory management method and device, equipment and a readable storage medium, and the method comprises the steps: obtaining a to-be-applied first memory capacity, and determining a first offset sequence corresponding to the first memory capacity; a positive correlation exists between the first memory capacity and the number of offsets in the first offset sequence; starting from a first offset in the first offset sequence, according to the first offset, offsetting a bit of a preset register, and based on the register value before offset and the register value after offset, obtaining a register update value; each bit is used for representing that the corresponding memory area is in an idle state or an occupied state; on the basis of the register update value, continuing the next offset until the first offset sequence is traversed, and determining a final first register value; and encoding the first register value to obtain a first memory address corresponding to the first register value. The memory management efficiency can be improved.

Embodiments of the present application relate to the technical field of computer storage, and provide a resource allocation method and apparatus, an electronic device, and a storage medium. The method comprises: in response to a memory acquisition request sent by a target host, a memory management unit in a resource allocation system acquiring demanded memory capacity and a memory starting address carried by the memory acquisition request; on the basis of a memory allocation unit in the resource allocation system, selecting from among at least two memory modules a target memory module matching the demanded memory capacity; and on the basis of a memory address router in the memory allocation unit and the memory starting address, performing address translation on the target memory module, and allocating to the target host the target memory module having undergone address translation, thereby achieving dynamic resource allocation of the target host. In this way, the interaction between a memory management unit and a memory allocation unit ensures rapid allocation of idle memory modules in a system, thereby improving the utilization rate of memory resources, and reducing costs of usage of the memory resources.

The invention relates to a multi-channel parallel virtual machine online migration method and system based on memory layering, and belongs to the technical field of cloud computing. According to the method, a to-be-migrated virtual machine memory is divided into a static data layer and a dynamic data layer, and the static data layer is directly transmitted to a target end through shared storage; the dynamic data layer is divided into a plurality of areas according to memory addresses, independent transmission channels are distributed for parallel migration, and the sizes of the partitions are dynamically adjusted according to the dirty page rate; calculating an iteration convergence factor in real time, and switching to a post-copy mode and backing up dirty pages to a shared storage when continuous iteration is not converged for multiple times; and recovering data from the shared storage when the network fails, and finally finishing the migration of the remaining dirty pages. Through memory hierarchical optimization, parallel transmission acceleration and a network fault-tolerant mechanism, the problems of low efficiency, iteration divergence and service interruption risks of large-memory and high-write-dirty-rate virtual machine migration in an AI scene are solved, the migration speed and success rate are remarkably improved, and continuous execution of an AI task is guaranteed.

The present specification provides a method and an apparatus for creating a shared remote direct memory access link, which are applied to a local terminal. The method includes: receiving a first creating request for a first shareable remote direct memory access RDMA link initiated by a first application process on the local terminal, where an associated memory address indicated by the first creating request for the first shareable RDMA link is a shared memory address of the first application process and a second application process on the local terminal; creating the first shareable RDMA link between the local terminal and an opposite terminal according to the first creating request, so that the shared memory address is registered to an RDMA device on the local terminal as the associated memory address of the first shareable RDMA link.

The embodiment of the invention provides a memory access method and device and a storage medium. In an equipment straight-through scene, a duplicate page is constructed for a target physical memory page where index information in an available ring is located, by maintaining the duplicate page, the index information accessed by straight-through equipment can be lagged behind the index information maintained by a virtual machine, and work such as missing page recovery can be completed in the lagging period. Therefore, it is ensured that preparation of the memory data is completed before the direct connection device obtains the memory address of the virtual machine to be accessed, and it is ensured that the direct connection device normally implements DMA access and does not perceive the page missing problem. Therefore, the memory missing page can be supported in the equipment direct connection scene, on the basis, the physical memory page can be reused as required, the memory access of the direct connection equipment is not influenced, and the utilization rate of the physical memory can be effectively improved.

A generative artificial intelligence (AI) system includes a generative AI model configured to generate outputs based on a training data set. The AI system additionally includes a secure data vault system. The secure data vault system additionally includes a sandbox system storing the generative AI model and operatively coupled to the generative AI model to send inputs to generate the outputs from the generative AI model, wherein the sandbox system comprises an execution environment configured to restrict execution of the generative AI model to a predefined memory address range. The secure data vault system further includes a secure network service communicatively coupled to the sandbox system and configured to authenticate a connection to an external system and to download from the external system an update package for the generative AI model when the connection is authenticated.

The embodiment of the invention provides a memory management method and electronic equipment, which are applied to wearable equipment. When a first application in the wearable device is started, a plurality of memory areas are allocated to the first application in advance according to the first configuration information. Each memory area corresponds to a preset capacity, a plurality of memory blocks are arranged in the memory area, and the memory capacity of the memory blocks is equal to the preset capacity. In the running process of the first application, when the memory is applied, appropriate memory blocks can be matched from a plurality of memory areas, and address information of the memory blocks is returned. The capacity of the memory block is greater than or equal to the capacity required for applying for the memory, and the memory block is in an idle state. Therefore, by planning and managing the memory in advance, the memory address information can be returned at an extremely high speed when the first application applies for the memory. Particularly, under the scenes that equipment hardware resources are limited and the first application frequently applies for the memory in a short time, the time consumed by memory application can be remarkably shortened, and the application running efficiency is improved.

The invention relates to an automatic memory protection method and device, computer equipment and a storage medium, and the automatic memory protection method comprises the steps: responding to a real-time memory read-write instruction, and determining a target memory address corresponding to the memory read-write instruction; determining a pre-stored tag value corresponding to the target memory address and an actual tag value currently embedded in a memory block pointed by the target memory address; and when it is detected that the pre-stored tag value is not matched with the actual tag value, stopping a memory operation associated with the memory read-write instruction. Through the method and the device, the problem that the data-oriented attack cannot be effectively prevented is solved, the data-oriented attack is effectively prevented, and the memory security and the system operation efficiency are improved.

Apparatuses and techniques for logging a memory address associated with faulty usage-based disturbance data are described. In an example aspect, a memory device can detect, at a local-bank level, a fault associated with usage-based disturbance data. This detection enables the memory device to log a row address associated with the faulty usage-based disturbance data. To avoid increasing a complexity and / or a size of the memory device, some implementations of the memory device can perform the address logging at the multi-bank level with the assistance of an engine, such as a test engine. The memory device stores the logged address in at least one mode register to communicate the fault to a memory controller. With the logged address, the memory controller can initiate a repair procedure to fix the faulty usage-based disturbance data.

The invention discloses a simulator detection method and system based on multi-dimensional feature fusion, and relates to the technical field of simulator detection, and the method comprises the steps: collecting the static feature information of a to-be-detected device; reading a memory mapping file of the equipment process in a preset time window, and obtaining a memory address allocation state at each moment to form a time sequence data set; further constructing an address space evolution sequence, and performing domain theory modeling to construct an address space domain; obtaining an address evolution function through a function construction algorithm; generating a regular mark through a natural transformation detection algorithm; performing topological structure analysis and coherence calculation on the address space category to generate address space complexity features; static feature information, regular marks and address space complexity features are integrated through a multi-layer fusion strategy, and simulator detection results are screened, judged and output layer by layer. According to the method, through a complementary collaborative system of static verification, dynamic rules and topology complexity, the anti-avoidance capability and robustness of detection are improved.

The invention provides a performance analysis method and device of an application program, electronic equipment and a storage medium, and is applied to the technical field of computers. Determining a first NUMA node to which the memory address belongs and a second NUMA node to which a target thread initiating the memory access operation belongs, counting the number of times of remote access and the number of times of local access according to the corresponding relationship between the first NUMA node and the second NUMA node, and determining a target source code for accessing the memory address in source codes of the application program, according to the operation characteristics of the application program in the NUMA system, the remote access times, the local access times and the target source code of the access memory address of the application program in the memory access process are counted, the operation process of the application program can be visually reflected, and a reference basis can be provided for performance analysis of the application program.

A method for use in a storage processor, comprising: receiving an I / O request that is associated with a logical block address; allocating a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and executing the I / O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot.

Processing circuitry (4) performs data processing in response to instructions. Memory management circuitry (28) controls access to memory based on page table information capable of associating a given page of memory address space with a read-as-X property indicative that reads to an address in the given page of memory address space should be treated as returning a specified value X. In response to determining, for a read request issued to read a read target value for a read target block of memory address space, that at least part of the read target block corresponds to a page associated with the read-as-X property, the memory management circuitry (28) controls the specified value X to be returned to the processing circuitry (4) as at least part of the read target value. This enables large regions of memory address space to be treated as storing a specified value without needing to commit physical memory for those regions.

The invention discloses a switch, a method and a system for realizing collective communication based on a multicast replication engine, the switch comprises a plurality of ports and a multicast replication engine, and the multicast replication engine comprises a group matcher and a broadcast module; if the multicast replication engine determines that the communication request transmitted by the request port is a broadcast request, the multicast replication engine sends the communication request to a group matcher and receives broadcast data transmitted by a request port target; the group matcher responds to the received broadcast request, determines broadcast ports and corresponding broadcast addresses according to a preset broadcast group table and transmits the broadcast ports and the corresponding broadcast addresses to the broadcast module, the broadcast group table comprises memory addresses configured for all the ports, the broadcast ports are other ports except the request port, and the broadcast addresses are one or more of the memory addresses; and when the broadcast module receives the broadcast ports and the broadcast addresses, each broadcast port is controlled to receive broadcast data through the broadcast addresses. According to the invention, the broadcast operation efficiency can be improved, and the data transmission delay is reduced.