983 results about "Memory address" patented technology

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

The invention relates to the technical field of network communication, and discloses a vehicle-mounted edge computing data recording system and method based on protocol adaptive analysis, and the system comprises a multi-protocol network access controller which is used for capturing an original data frame and extracting a physical feature triple; the identification analysis engine is used for executing hash operation on the triple to generate a physical feature code and retrieving a physical logic address mapping table; the direct memory access controller is used for responding to a target memory address pointer hit by retrieval and directly writing a data load into an input buffer area of the functional operation module, and by constructing a direct addressing mechanism based on Hash mapping, thorough decoupling of vehicle-mounted heterogeneous network physical topology and edge computing logic is achieved.

The invention relates to a matrix storage operator optimization method and device, computer equipment and a readable storage medium. The method comprises the following steps: allocating memory resources for target data; determining a logic structure corresponding to the source data, establishing a first mapping relation between each logic index in the logic structure and a register address of the source data, and establishing a second mapping relation between each logic index in the logic structure and a memory address of the target data; and determining a corresponding relationship between a memory address of the target data and a register address of the source data based on the first mapping relationship and the second mapping relationship, and storing the source data stored in a register into a memory resource corresponding to the target data based on the corresponding relationship. By adopting the method, the generalization ability of the matrix storage operator can be improved.

The invention relates to the technical field of SOC chips, and discloses an efficient memory management method and system based on an SOC chip, which are used for constructing a complete topological graph and calculating access delay distribution by comprehensively analyzing an internal physical structure of the chip. According to the method, the memory access behavior of each processing core is monitored in real time, dynamic memory partitioning is executed according to the access characteristics and the physical topological structure, and the optimal access area is distributed for the processing core. And when an access hot spot is detected, triggering a data migration mechanism to copy hot spot data to a relatively close memory area. According to the method, a memory address space is recombined by adopting a topology-aware address mapping algorithm, a multi-level cache collaboration mechanism is established, and the working mode of a memory controller is dynamically adjusted according to an application type. Through load balancing monitoring and periodic memory recombination, the memory access delay is effectively reduced, the bandwidth utilization rate is improved, and the overall memory access performance of the SOC chip is optimized.

A generative artificial intelligence (AI) system includes a generative AI model configured to generate outputs based on a training data set. The AI system additionally includes a secure data vault system. The secure data vault system additionally includes a sandbox system storing the generative AI model and operatively coupled to the generative AI model to send inputs to generate the outputs from the generative AI model, wherein the sandbox system comprises an execution environment configured to restrict execution of the generative AI model to a predefined memory address range. The secure data vault system further includes a secure network service communicatively coupled to the sandbox system and configured to authenticate a connection to an external system and to download from the external system an update package for the generative AI model when the connection is authenticated.

The invention discloses a simulator detection method and system based on multi-dimensional feature fusion, and relates to the technical field of simulator detection, and the method comprises the steps: collecting the static feature information of a to-be-detected device; reading a memory mapping file of the equipment process in a preset time window, and obtaining a memory address allocation state at each moment to form a time sequence data set; further constructing an address space evolution sequence, and performing domain theory modeling to construct an address space domain; obtaining an address evolution function through a function construction algorithm; generating a regular mark through a natural transformation detection algorithm; performing topological structure analysis and coherence calculation on the address space category to generate address space complexity features; static feature information, regular marks and address space complexity features are integrated through a multi-layer fusion strategy, and simulator detection results are screened, judged and output layer by layer. According to the method, through a complementary collaborative system of static verification, dynamic rules and topology complexity, the anti-avoidance capability and robustness of detection are improved.

A method for use in a storage processor, comprising: receiving an I / O request that is associated with a logical block address; allocating a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and executing the I / O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot.

The embodiment of the invention provides a memory access method, a memory access device, electronic equipment and a storage medium. The memory access method comprises the steps that address processing operation is executed on a first address field of a system memory address, a first memory address comprising a channel selection address field is obtained, and a plurality of memory channels correspond to a plurality of values of the channel selection address field in a one-to-one mode; and accessing the corresponding memory channel according to the plurality of values of the channel selection address field. According to the memory access method, different numbers of memory channel configurations can be flexibly coped with, the load balancing problem of the memory system under the condition of multiple memory channels is improved, and the bandwidth loss caused by memory access imbalance is reduced.

The invention discloses a memory access method and device, electronic equipment and a storage medium. The memory comprises a plurality of memory channels, the plurality of memory channels comprise N memory channels to be accessed, and N is an integer greater than 1. The memory access method comprises the steps that a first address field in a system memory address is selected, and each memory channel corresponds to at least one value of the first address field; based on the number N of the memory channels to be accessed, first address processing is carried out on the first address field to obtain a target address field, and the target address field comprises N first values; and accessing the N memory channels to be accessed based on the N first values. According to the memory access method, the number of the memory channels to be accessed can be flexibly adjusted, so that the chip design can be flexibly compatible with multiple memory channel numbers, the flexibility of the chip design is improved, unnecessary cost waste is reduced, and the memory access method has relatively high practical value.

An apparatus has decoder circuitry within a first processing element to decode instructions, in order to respond to a sequence of instructions by generating control signals. Processing circuitry within the first processing element is responsive to the control signals to perform operations defined by the sequence of instructions. The decoder circuitry is responsive to a stashee hint instruction in the sequence of instructions to issue control signals to cause the processing circuitry to issue a stash interest request via an interface used to couple the first processing element to interconnect circuitry. The stash interest request is arranged to provide a given memory address indication determined from the stashee hint instruction and to trigger stashing control circuitry accessible via the interconnect circuitry to cause updated data associated with the given memory address indication to be made available for stashing in an associated storage structure of the first processing element.

The invention provides a memory access optimization method and device for an aggregate communication operator and computing equipment, and relates to the technical field of graphics processor computing. The method comprises the following steps: identifying a memory access instruction sequence in a to-be-optimized set communication operator, wherein the memory access instruction sequence comprises a standard loading instruction and a standard storage instruction; replacing the standard loading instruction with a batch loading instruction, and replacing the standard storage instruction with a batch storage instruction; the batch loading instruction and the batch storage instruction are configured to execute batch operation on the continuous memory address space at the thread beam level and finally execute the batch loading instruction and the batch storage instruction, so that the emission number of memory access instructions can be reduced, the scheduling burden of a thread beam scheduler is relieved, and the scheduling efficiency is improved. And the execution efficiency and the bandwidth utilization rate of the ensemble communication operator in the distributed training of the graphics processor are effectively improved.

The invention discloses a memory error correction method, a server system, electronic equipment and a storage medium, and relates to the technical field of storage software, and the method comprises the following steps: under the condition that a memory generates a current uncorrectable error, based on an uncorrectable error evolution rule, correcting the current uncorrectable error; a group of target historical correctable errors matched with the memory address of the current uncorrectable error is extracted from a historical error record file, the group of target historical correctable errors are tried to be corrected, and once the group of target historical correctable errors are successfully processed, the current uncorrectable error has an opportunity to be converted into a derivative correctable error, so that the correctable error cannot be corrected. According to the method, the source or mode of the current uncorrectable error is changed, at the moment, the memory error processing mechanism plays a role again, and then the derivative correctable error is corrected, so that the current uncorrectable error is fundamentally solved, and the problem that the multi-bit error cannot be effectively corrected when the uncorrectable error occurs in the memory is solved. And the problems of data loss and server system stability reduction are solved.

The invention provides an instruction synchronization method and an artificial intelligence chip, and relates to the technical field of artificial intelligence chips, and the method comprises the steps: after a processing core sends a calculation instruction, sending a barrier instruction with the same memory address, enabling the calculation instruction and the barrier instruction to enter a cache in an order-preserving manner, and guaranteeing that the cache receives the calculation instruction and achieves calculation; therefore, a large amount of memory fence operation is reduced, and the processing time delay of the memory access instruction is reduced. And for the plurality of processing cores bound with the same target barrier identifier, recording the number of synchronized instructions of the plurality of processing cores in real time. When the number of the synchronized instructions is equal to the expected synchronization number, returning a synchronization success message to the plurality of processing cores so as to realize instruction synchronization of the plurality of processing cores; in the process, each processing core does not need to circularly read the atomic accumulation result, so that the occupation of bandwidth resources such as bus bandwidth and direct interconnection bandwidth is greatly reduced, the instruction synchronization overhead is reduced, and the efficiency of the whole system is improved.

Examples are disclosed herein relating to memory paging. In some examples, a host device is configured to communicate with an expansion device. The expansion device can include first and second memory, and a device virtual memory address (DVA) table. The expansion device can store data that can be requested by the host device. The first memory is a cache for the second memory based on a page presence table (PPT). The PPT can indicate a presence of second memory pages in the first memory cache. The DVA table can include information to locate data in the first memory based on a host physical memory address of a memory request. The device physical memory address can identify a memory location at which the data is stored. The data can be provided from the expansion device to the host device in response to the memory request based on the PPT.

The invention provides an operator execution method and device, equipment, a storage medium and a program product, and relates to the technical field of artificial intelligence, the method comprises the following steps: reading input tensor data in a first memory, and segmenting the input tensor data according to preset operation granularity information to obtain a plurality of tensor data blocks; for each tensor data block, respectively executing the following steps: processing the tensor data block by adopting a basic calculation unit corresponding to the tensor data block in the artificial intelligence chip, and mapping based on position information of the basic calculation unit in the artificial intelligence chip to obtain a source memory address of the tensor data block in the first memory; converting a source memory address of the tensor data block into a target memory address of output tensor data in a second memory; and storing the plurality of tensor data blocks to a second memory according to the target memory addresses of the plurality of tensor data blocks to obtain output tensor data. Complex division operation in layout transformation is avoided, and the performance of a reordering operator is improved.

The invention relates to the technical field of artificial intelligence, and provides a fusion operator execution method, electronic equipment, a storage medium and a program product, and the method comprises the steps: determining a plurality of to-be-fused target operators; according to the tensors of the multiple target operators, a pseudo address mapping table is generated, and the pseudo address mapping table is used for recording the mapping relation between the actual memory addresses of the tensors and pseudo addresses; operator fusion is carried out on the multiple target operators, a fusion operator is obtained, and the memory address of the tensor of the fusion operator is a continuous pseudo address; and executing the fusion operator, converting the pseudo address into an actual memory address according to the pseudo address mapping table in the execution process, and accessing data of the tensor according to the actual memory address. According to the method, a large amount of extra memory copy overhead caused by physical movement and rearrangement of the original tensor in a traditional operator fusion scheme is avoided, and the computing resource utilization rate and the execution efficiency are remarkably improved.

Systems and methods are provided. A system includes a display and camera. The system additionally includes a secure data vault system. The secure data vault system includes a sandbox system operatively coupled to the camera and configured to receive camera data from the camera, wherein in operation of the sandbox system, the camera only sends camera data to the sandbox system, and wherein the sandbox system comprises an execution environment configured to restrict execution of instructions to a predefined memory address range. The secure data vault system additionally includes a display and rendering system operatively coupled to the sandbox system and configured to render an image based on the camera data processed via the instructions and to display the image via the display, wherein the display and rendering system is configured to blur sections of the image based on private information derived from the image.

The invention discloses a data processing method and system, electronic equipment and a medium, and relates to the technical field of storage. The output end of the memory controller unit is connected with the plurality of cache unit groups through a plurality of channels, and the channels are in one-to-one correspondence with the cache unit groups, so that a multi-channel architecture is constructed. When data processing is carried out based on a multi-channel architecture, after a memory address space is divided into different channels in advance, after a request sent by a request sender is received, a channel hit by a request address is determined according to a division result obtained after the memory address space is divided into the different channels in advance, and the channel hit by the request address is determined. And finally, in the memory connected with the channel hit by the request address, responding to the request based on the request address to realize data processing. And secondly, the memory address space is divided into different channels in advance, so that the multiple channels can process different read-write requests at the same time, the requirement for high-speed data processing is met, idle resources are avoided, and the resource utilization rate is increased.

The invention discloses a data processing method and device, electronic equipment and a computer storage medium, and relates to the technical field of data acquisition, the method comprises the following steps: acquiring an acquisition data packet sent by each data acquisition module, and analyzing according to the acquisition data packet to obtain successfully analyzed data, the successfully analyzed data at least comprising an acquisition node identifier; determining a memory address identifier of the successfully analyzed data according to the acquisition node identifier and a preset Hash mapping table, and after the successfully analyzed data is stored in a memory buffer area mapped by the memory address identifier, performing data quality verification according to the successfully analyzed data to obtain a quality verification result; after the data quality verification is completed, data reorganization is carried out according to the successfully analyzed data to obtain reorganized data, data restoration is carried out on the reorganized data according to the quality verification result to obtain final output data, and the method and device aim at improving the processing capacity of large-scale data collection so as to ensure the accuracy and timeliness of data collection.

The invention provides a shared memory communication system and method between processing units, electronic equipment and a medium, and the system comprises the following steps: a first processing unit is used for configuring a memory address of a preset communication flag bit in a shared memory as a specified address, and initiating a memory access request for the specified address to a cache module to poll the communication flag bit; and the cache module is used for receiving the memory access request, acquiring the latest data of a specified address from the shared memory under the condition of determining that the access address in the memory access request is the specified address, and returning the latest data to the first processing unit. The first processing unit can obtain the latest state of the communication flag bit in time, so that communication synchronism and data consistency between the processing units are ensured, communication errors and data errors caused by cache inconsistency are avoided, the reliability and stability of shared memory communication are improved, and the service life of the shared memory is prolonged. Meanwhile, the problem that the efficiency is reduced due to the fact that effective cache lines are cleared in an existing solution is solved.

The invention provides a multi-core processor chip and a storage access method and device of the multi-core processor chip, and relates to the technical field of computer processors, the multi-core processor chip comprises at least one processor core, the processor core comprises a general processor core, a first address space mapping module and a first core interconnection interface, the universal processor core supports high-speed cache consistency; at least one input / output core grain, wherein the input / output core grain comprises a memory interface, a directory, a second address space mapping module and a second core grain interconnection interface; both the first address space mapping module and the second address space mapping module store an address space mapping table, and the address space mapping table stores a mapping relationship between a memory address accessed by a processor core grain and a memory interface of an input / output core grain; the directory stores cache consistency information of the cache blocks corresponding to the memory interfaces of the input / output core grain and other input / output core grains corresponding to the directory.

The invention provides an address mapping method and device, electronic equipment and a chip, and relates to the technical field of memory management, the method comprises the following steps: obtaining a plurality of original memory addresses, at least two original memory addresses in the plurality of original memory addresses including the same memory bank address; based on an original address bit of each original memory address, determining a target address bit of each original memory address, the number of bits of the target address bits being a first preset number, and the first preset number being smaller than the number of bits of the original address bits; determining a mapping result of each original memory address based on the target address bit and a preset mapping relation; target memory addresses corresponding to the original memory addresses are determined based on the mapping result and the memory bank addresses in the original memory addresses, and the memory bank addresses included in the target memory addresses corresponding to different original memory addresses are different.

A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A dispatch unit within the processor core receives a vector memory operation. The dispatch unit sends the vector memory operation to a first vector input queue of multiple vector input queues. The sending is based on the memory addressing mode. A micro-operation sequencer splits the vector memory operation into one or more memory micro-operations, which includes forwarding each micro-operation within the one or more micro-operations to a first memory queue within multiple memory queues. A memory operation is then issued to a load-store unit within the processor core. The issuing includes selecting, from the multiple memory queues, the memory operation. The vector memory operation comprises either a vector load operation or a vector store operation.

In some implementations, a memory system may receive multiple memory requests associated with a memory, wherein the memory is associated with multiple memory ranks, and wherein each memory request, of the multiple memory requests, includes a memory address indicating a memory rank, of the multiple memory ranks, that is to be accessed for that memory request. The memory system may group the multiple memory requests based on the multiple memory ranks. The memory system may transmit, to a memory controller associated with the memory, a scheduled set of memory requests, wherein the scheduled set of memory requests includes memory requests selected from one or more groups of memory requests associated with one or more scheduled memory ranks of the multiple memory ranks.

The invention discloses an Ethernet-based distributed cache coherence protocol, an implementation method, an implementation device and an implementation system. A plurality of computing nodes are connected through a packet switching network. Each computing node comprises a CPU / GPU (Central Processing Unit / Graphics Processing Unit) and a local cache thereof, and is provided with a cache agent. The far-end memory is organized in home nodes, and each home node manages a part of physical address space and is equipped with a directory controller. When the CPU of the computing node accesses a far-end memory address and does not hit in the local cache, the CA of the computing node replaces the far-end memory address and communicates with the DC managing the address through the network so as to maintain the cache consistency of the data among all the nodes. Based on a cache consistency protocol of a directory, the CXL.cache consistency of a plurality of independent computing nodes can be maintained in a low-overhead and high-reliability mode on a high-delay and lossy packet switching network, and broadcast storm caused by a monitoring protocol is avoided.

Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication and augment existing memory systems to allow them to be both high capacity and high bandwidth simultaneously. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and / or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.

The invention provides a chip routing method and device, electronic equipment and a storage medium, and relates to the technical field of chip design and manufacture, and the method comprises the steps: carrying out the first-stage interleaving among a plurality of input and output modules based on a memory address of a current data request, and determining a target input and output module; in the target input and output module, performing second-level interleaving among the plurality of links based on the memory address, and determining a target link; and performing third-level interleaving among the plurality of point-to-point channels of the target link, and determining the point-to-point channel of the current data request. According to the method and the device provided by the invention, a three-level progressive interleaving architecture which performs dynamic calculation completely based on the memory address is constructed, the problem that hardware resource consumption is sharply increased due to chip interconnection scale enlargement is solved, the chip cost and power consumption are remarkably saved, and through a step-by-step refined load balancing mechanism, the load balancing efficiency is greatly improved. The routing efficiency in the chip is improved, and the overall communication bandwidth and system performance of chip interconnection are improved.

A system for managing cache coherency comprises memory areas, processing cores, cache nodes each associated with at least one of the processing cores, and a hardware processor configured to: for each of the memory areas: cluster the processing cores into clusters according to memory access metrics in relation to the memory area; and for each of the clusters, associate the memory area with a caching scheme; and configure the processing cores to: receive from a first core a memory access command comprising a memory address associated with a memory area, where the first core is a member of a first cluster for the memory area; compute a determination of a target cache node according to the memory access command, where the target cache node is associated with a second core; and access the memory area according to the caching scheme associated with the memory area for the first cluster.

A system configured to rearrange and distribute data of an incoming image for processing by a number, K≥4, of processing clusters. The incoming image has a number of scanlines, each scanline being arrangeable as a plurality of data units. The system is configured to logically partition the incoming image into K uniform regions corresponding to the number of processing clusters, wherein the K regions are defined by a number, R≥2, of rows and a number, C≥2, of columns, by i) dividing each scanline into a number, C≥2, of uniform line segments, the length of a line segment being equal to the width of a region, ii) dividing each line segment into a number, W≥2, of data units, each having a number, Q≥2, of bytes, i.e. Q-byte data units, and iii) defining a region height of a number, H≥2, of scanlines for each region. The system is configured to store, in an associated memory, data units from different regions interleaved with respect to each other, while consecutive data units of each line segment of each row of regions of the incoming image are stored with an offset of K memory positions such that the consecutive data units are stored K memory addresses apart. The system is configured to transpose each assembly of K number of Q-byte data units stored in said memory into a transposed assembly of Q number of K-byte words, each K-byte word including one byte per cluster, and transfer the bytes of each K-byte word to said processing clusters in parallel, one byte per cluster.

An opportunistic approach is described to accelerate certain memory copy operations to be performed by a computing engine by executing instructions. An instruction for a memory copy operation can be identified that has a first data type with a smaller number of bits per data element than supported by the computing engine to perform the copy operation. The instruction can be replaced with another instruction that has a second data type with a higher number of bits per data element based on the alignment of the memory addresses for the copy operation and the total number of data elements to be copied. The second data type may not only accelerate the copy operation but also provide better utilization of the underlying hardware of the computing engine.