512 results about "Memory address" patented technology

The invention relates to the technical field of network communication, and discloses a vehicle-mounted edge computing data recording system and method based on protocol adaptive analysis, and the system comprises a multi-protocol network access controller which is used for capturing an original data frame and extracting a physical feature triple; the identification analysis engine is used for executing hash operation on the triple to generate a physical feature code and retrieving a physical logic address mapping table; the direct memory access controller is used for responding to a target memory address pointer hit by retrieval and directly writing a data load into an input buffer area of the functional operation module, and by constructing a direct addressing mechanism based on Hash mapping, thorough decoupling of vehicle-mounted heterogeneous network physical topology and edge computing logic is achieved.

The invention discloses a data processing method and device, electronic equipment and a computer storage medium, and relates to the technical field of data acquisition, the method comprises the following steps: acquiring an acquisition data packet sent by each data acquisition module, and analyzing according to the acquisition data packet to obtain successfully analyzed data, the successfully analyzed data at least comprising an acquisition node identifier; determining a memory address identifier of the successfully analyzed data according to the acquisition node identifier and a preset Hash mapping table, and after the successfully analyzed data is stored in a memory buffer area mapped by the memory address identifier, performing data quality verification according to the successfully analyzed data to obtain a quality verification result; after the data quality verification is completed, data reorganization is carried out according to the successfully analyzed data to obtain reorganized data, data restoration is carried out on the reorganized data according to the quality verification result to obtain final output data, and the method and device aim at improving the processing capacity of large-scale data collection so as to ensure the accuracy and timeliness of data collection.

A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A dispatch unit within the processor core receives a vector memory operation. The dispatch unit sends the vector memory operation to a first vector input queue of multiple vector input queues. The sending is based on the memory addressing mode. A micro-operation sequencer splits the vector memory operation into one or more memory micro-operations, which includes forwarding each micro-operation within the one or more micro-operations to a first memory queue within multiple memory queues. A memory operation is then issued to a load-store unit within the processor core. The issuing includes selecting, from the multiple memory queues, the memory operation. The vector memory operation comprises either a vector load operation or a vector store operation.

Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication and augment existing memory systems to allow them to be both high capacity and high bandwidth simultaneously. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and / or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.

The invention discloses a memory controller, a memory address processing method thereof and a computing system.The method comprises the steps that a reverse mapping table between a system physical address area and an available DRAM physical address area is obtained through bad area data based on a DRAM, and during running, the memory controller sends a system physical address sent by a processor to the DRAM physical address area according to the reverse mapping table; the method comprises the following steps: dynamically remapping to a DRAM physical address of a non-failure unit, and generating a corresponding control signal for accessing the DRAM, thereby shielding a DRAM physical region containing a failure storage unit, providing a continuous and complete system physical address space for an upper layer, improving the effective utilization rate of the DRAM and the operation stability of a computing system, and improving the reliability of the computing system on the premise of not changing the memory access mode of a processor. And the risk that the whole memory is unavailable due to local storage failure is reduced.

A computer express link fabric having: a plurality of computer express link switches; a plurality of computer express link connections among the computer express link switches; and a controller. The controller is configured to: map memory addresses in a mapped memory space to physical addresses of random access memory cells of memory devices connected to the computer express link fabric; and implement, in a storage space of a memory sub-system connected to the computer express link fabric and having non-volatile memory cells, a persistent copy of data stored by memory access requests received in the computer express link fabric and having memory addresses in the mapped memory space.

The invention discloses a cross-chip access method and device, a medium, a program product and a multi-chip system. The method is applied to a first chip, the first chip is any one of cascaded multi-stage chips, and the method comprises the following steps: receiving a first access instruction of a previous-stage chip, the first access instruction comprising a first address; querying a first mapping table, and converting the first address into a second address in a second address interval of the first chip in response to the fact that the first address is located in a first address interval of the upper-level chip; the first mapping table comprises a mapping relation between the first address interval and the second address interval; based on a second mapping table, converting the second address into a third address in a memory address interval of a next-level chip; the second mapping table comprises a mapping relation between the second address interval and the memory address interval; and sending a second access instruction to the next-level chip, wherein the second access instruction comprises the third address.

The invention provides a data transmission verification method and device, electronic equipment and a storage medium, and relates to the technical field of network communication, a unique connection identifier is allocated in a connection establishment stage of two communication parties, and a serial number field is designed as a combination of message length information and a random number; a connection identifier and a serial number field are packaged at the head and the tail of the data message respectively, a type-length-value structure message is carried in the middle of the data message, and the consistency of the connection identifier and the serial number field at the head and the tail of the data message is verified after the received message is de-packaged; and when verification fails, the current connection is terminated, and the connection is triggered to be reestablished to retransmit data, so that the problems that packet loss, data tampering or errors are easy to occur during RoCE data transmission in the prior art, and a traditional verification mode is high in calculation complexity, large in occupied bandwidth and high in reliability can be solved. And a traditional retransmission mode is easy to cause system performance reduction or system abnormity caused by access of a wrong memory address.

The invention relates to a physical unclonable function modeling attack resisting method based on a neural network. The method comprises the following steps: generating a multi-bit random bit stream by using a random seed generated by an LFSR module, and simultaneously acting PUF excitation on a plurality of physical unclonable functions to generate a multi-bit physical unclonable function response; the method comprises the following steps: constructing an initial feature matrix by utilizing a Decoder module, and equally dividing position decoding excitation into a plurality of binary position decoding sub-excitation with a certain length; sequentially guiding multi-bit physical unclonable function responses to storage units of corresponding addresses to form a physical unclonable function response feature matrix, and inputting the physical unclonable function response feature matrix into the neural network model to obtain one-bit confusion response; and the other bit of confusion response of the random seed is reutilized until a final confusion response sequence with a preset bit is generated, and the server compares the final confusion response sequence with an expected confusion response to complete identity authentication. By adopting the method, the hardware security can be improved.

The invention relates to the technical field of real-time data statistics, and discloses a real-time data statistics method and system.The method comprises the steps that the total memory space size is calculated based on the number of ports of a switch, a shared memory area is applied through a unique key value of the system, and the shared memory area is mapped to a process address space; creating a timer object, and when the period of the timer object expires, triggering a callback function and writing the read statistical data into the shared memory area; and when the front-end application module receives a statistical data acquisition request, calling an access interface function to directly read the port statistical data from a memory address corresponding to the shared memory region. Decoupling of collection and access of port statistical data is achieved, the method is suitable for a network monitoring scene needing high-frequency refreshing of statistical information, and user experience is effectively improved.

A processing device writes file system data to a first area of a memory zone of a zoned block memory device based on a current position of a write pointer within the memory zone. The file system data comprises data files contained within a file system and file structure metadata describing a file structure of the file system. The processing device detects a write event based on the write pointer advancing past a predetermined memory address within the memory zone that corresponds to a checkpoint. The checkpoint is a second area within the memory zone that is designated for storing write event data. Based on detecting the write event, the processing device writes write event data to the checkpoint, the first write event data indicating a most recent memory address of a root node of the file structure within the memory zone.

Systems and techniques for providing mixed-precision matrix multiplication in multi-chiplet processors recognize different precision formats of matrices to be multiplied based on, e.g., parameters provided with instructions or start and end memory locations of the matrices. A plurality of different multiplication chains are provided for different formats such that mixed-precision matrix multiplication can be performed using multiplication chains configured to handle multiplication of different precision formats. The multiplication chains are automatically selected based on the precision formats of the matrices to be multiplied, enabling programmers to utilize the chains without having to directly access the individual multiplication chains.

An on-die computer apparatus (100) comprises a plurality of cores (106) and a plurality of RAM modules (100). Sets of physical memory addresses in the RAM modules are allocated for use by virtual machines executing on the cores. A plurality of data transfer channels (112) are associated the RAM modules. The apparatus further comprises a channel controller (120) for controlling data transfer over the data transfer channels. The channel controller stores security information indicating which of the VMs is designated as secure, and channel information indicating which of the data transfer channels is assigned for use by each of the VMs for accessing its allocated physical memory addresses. The channel controller directs read / write requests from a VM over the data transfer channel assigned to the VM based on the security information and the channel information.

The embodiment of the application discloses a kind of collaborative evaluation method for exploring the upper limit of processor micro-architecture performance and related device, the method includes that various idealized micro-architecture components are constructed according to the collaborative process of ideal model by real processor model, processor micro-architecture performance is collaboratively evaluated, and collaborative process includes: real processor model sends instruction query and information request to ideal model, and the request carries the memory address of dynamic instruction;Ideal model executes dynamic instruction according to memory address and obtains target value in normal working state, and target value is returned as the response of the request to real processor model;Real processor model executes dynamic instruction and obtains actual value in execution phase;Target value and actual value are verified in submission phase, and verification result is obtained.Using the embodiment of the application, the theoretical performance upper limit of value prediction and other speculative execution techniques can be accurately quantified, and the real performance bottleneck of the entire processor system integrated with the technique can be identified.

The invention relates to a memory management method, electronic equipment and a vehicle. The method comprises the steps of receiving a memory allocation request; wherein the memory allocation request indicates the size of the memory requested to be allocated; determining the size of a to-be-allocated memory and a memory address linked list corresponding to the to-be-allocated memory according to the size of the memory requested to be allocated and indicated by the memory allocation request and the size of a preset memory unit; wherein the size of the preset memory unit indicates the size of the pre-divided memory unit; the memory address linked list is used for storing memory addresses; according to the determined size of the to-be-allocated memory, acquiring a memory address of the to-be-allocated memory from a memory address linked list corresponding to the determined to-be-allocated memory; and allocating the to-be-allocated memory based on the determined memory address of the to-be-allocated memory. On the basis of improving the reasonability of confirming the address of the memory to be allocated, the reasonability and user experience of memory management based on the determined address of the memory to be allocated are further improved.

A method of operating a memory circuit is disclosed. A memory circuit includes a memory array having a memory portion and a spare portion. The method includes receiving a first write command to a first memory address, where the first memory address has a state mapped to a first backup memory address, and where the first memory address corresponds to a first memory location in the memory portion, and the first spare memory address corresponds to a first spare memory location in the spare portion. The method further includes, in response to the first write command, performing a first write operation by attempting to write the first data to the first memory location; determining whether the first write operation is successful; and in response to success of the first write operation, de-mapping the first memory address from the first standby memory address.

This application provides a verification system, verification method, apparatus, and related devices. The verification system includes two cache consistency slave device verification units, each configured with a main address region and a mirror address region. The mirror data in the mirror address region of one cache consistency slave device verification unit is the data in the main address region of the other cache consistency slave device verification unit. When a mirroring operation is triggered between the two cache consistency slave device verification units, the correctness of the mirror data in the mirror address region is verified. The verification is determined by comparing the data in the main address region of one cache consistency slave device verification unit with the mirror data in the mirror address region of the other cache consistency slave device verification unit. This application avoids the complex processes of traditional verification, comprehensively reduces verification overhead, and thus improves the verification efficiency of memory address mirroring functionality.

A processing system including processing cores, a shared memory, a shift table that stores a maximum number of reservations to locations in the memory, and an exclusive monitor that uses the shift table and an eviction policy to enforce core synchronization. The eviction policy is based on priority, age of valid reservations, shift table fullness state, and reservation memory conflict. The shift table may include a memory address and a size value indicative of a flexible amount of reserved memory at the memory address. The exclusive monitor evicts an oldest reservation in the shift table having a same or lower priority level as the new reservation. The exclusive monitor rejects the new reservation when the shift table is full of higher priority reservations. Reservations are shifted to maintain age status. Stale reservations may be invalidated or have their priority lowered. Conflicting reservations may be made with the same priority level.

The invention relates to an application programming interface for indicating strided memory. Apparatuses, systems, and methods for performing thread memory addressing are disclosed. In at least one embodiment, a processor includes one or more circuitry to execute an application programming interface (API) to cause execution of one or more instructions based at least in part on one or more API parameters, the one or more API parameters indicate a size of one or more operands to be used by the one or more instructions.

A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.

An apparatus is described having processing circuitry for performing operations during which access requests to memory are generated. The processing circuitry generates memory addresses for the access requests using capabilities, where each capability indicates a pointer value and constraining information used to constrain access to memory using memory addresses derived from the pointer value. A marker indication field is stored in association with each capability to provide a marker value used to distinguish between static capabilities used to access statically allocated memory and dynamic capabilities used to access dynamically allocated memory. Capability tracking circuitry maintains a tracking structure providing a tracking field for each of a plurality of memory regions, and the capability tracking circuitry sets the tracking field for a given memory region amongst the plurality of memory regions when at least one capability whose associated marker indication field has a specified marker value is written to the given memory region. The specified marker value indicates that writing of the associated capability to memory is to be tracked by the capability tracking circuitry to facilitate subsequent revocation of that associated capability.

The application provides a method for protecting all memory space addresses based on a limited number of MPU configuration areas, which comprises the following steps: setting a configuration area (X-1) and 0 as inaccessible, and dynamically accessing the configuration area (X-1) by an exception processing function, so as to realize the method for configuring different access permissions of all memory addresses, effectively solve the problem that many scattered memory address spaces cannot be protected due to the limited number of hardware MPU configuration areas in the traditional scheme, and simplify the steps of configuring memory attributes and permissions, and improve the efficiency of embedded software development.

Provided in the embodiments of the present disclosure are a data processing method, apparatus and system. The method is applied to a data transmission device, and comprises: in response to a data sending notification of a data processing device, acquiring a target data descriptor of target message data; when it is determined, on the basis of the target data descriptor, that the target message data requires order preservation, placing the target data descriptor in a target buffer area for ordering, so as to obtain an ordering result; and on the basis of the ordering result, acquiring the target message data from a target memory address corresponding to the target data descriptor. A message order-preserving mode is changed to reordering based on a target data descriptor, and the size of the target data descriptor is much smaller than the size of target message data, so that the usage requirements of hardware resources are effectively reduced while an order-preserving capability that accommodates a higher CPU processing latency is achieved, thereby ensuring message order-preserving and performance requirements under high-latency CPU processing.

Methods and apparatus for mapping memory allocation to DRAM dies of a stacked memory modules are described herein. Memory address ranges in a module employing 3DS (three dimensional stacked) DRAMs (Dynamic Random Access Memories) comprising stacked DRAM dies are mapped to DRAM dies in the module based on a layer of the DRAM dies, where dies in different layers have different thermal dissipation characteristic. Chunks of the memory address range are allocated to software entities such as virtual machines (VMs) and / or applications based on a memory access rate of the VMs / applications and the thermal dissipation characteristics of the DRAM die layers, wherein VMs / applications with higher memory access rate are allocated memory on DRAM dies with higher thermal dissipation. In one aspect, memory ranks are associated with respective die layers. In response to detection of change in access rates, memory may be migrated between ranks. Interleaving at multiple levels is also supported.

The present disclosure provides a cache architecture comprising a cache memory having a tag storage and a data storage, a miss status holding register (MSHR) configured to track memory requests where each memory request includes a NoFill field, a safe history buffer (SHB) configured to store safe memory addresses and generate cache line fetch requests based on the stored safe memory addresses, and a cache controller configured to prevent cache fills for memory requests having the NoFill field set, send data to a processor without filling the cache memory when the NoFill field is set, and fill the cache memory with cache lines retrieved by the cache line fetch requests generated by the SHB. The cache architecture provides security against cache timing attacks by decorrelating cache fills from actual memory requests while maintaining performance through the safe history buffer mechanism.

Techniques for shared data prefetch are described. An exemplary instruction for shared data prefetch includes at least one field for an opcode, at least one field for a source operand to provide a memory address at least a byte of data, wherein the opcode is to indicate that circuitry is to fetch of a line of data from memory at the provided address that contains the byte specified with the source operand and store that byte in at least a cache local to a requester, wherein the byte of data is to be stored in a shared state.

The invention provides a data cache fault diagnosis method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring initial first data; writing the first data into the to-be-diagnosed set by utilizing a memory address matched with the to-be-diagnosed set in the data cache in the memory data area; reading second data from the set to be diagnosed; if the second data is consistent with the first data, updating the first data and returning to execute the step of writing the first data into the to-be-diagnosed set until the updating frequency of the first data is greater than the frequency threshold value so as to complete fault diagnosis of the to-be-diagnosed set; switching a next set in the data cache to serve as a to-be-diagnosed set, and returning to execute the step of obtaining the initial first data until fault diagnosis of all the sets in the data cache is completed; and if the second data is not consistent with the first data, determining that the to-be-diagnosed set has a fault, thereby completing fault diagnosis of the data cache.

This application discloses an instruction processing method, an information processing unit, a chip, and a chip system. The instruction processing method introduces instruction-based encapsulation, mapping, and parsing operations. This allows the first chip to access the memory cells of the second chip without directly overwriting the second chip's large memory address space during the mapping stage. Instead, it encapsulates a data packet based on the target instruction, writes this data packet to the second information processing unit of the second chip through mapping by the switching unit, and then parses it to trigger the actual access to the memory cell. This method occupies only a small mapping address space to complete cross-chip interaction. Compared to existing direct mapping access methods, it effectively reduces mapping space usage, avoids reliance on large BAR spaces or frequent sliding window mechanisms, and improves the applicability, scalability, and processing efficiency of the instruction processing method.

The invention relates to a processor and a memory access method. The processor comprises a UAV instruction sending unit, a UAV register management unit, a general register unit, a UAV data caching unit and a loading storage unit; the loading storage unit is configured to receive an SIMD instruction; reading resource information of the target UAV register from the UAV register management unit according to the address information of the target UAV register; under the condition that the SIMD instruction is determined to be a loading instruction according to the operation code, reading channel logic address information of each channel from the general register unit; under the condition that the memory addresses to be accessed by the multiple channels of the SIMD instruction are judged to be continuous, calculating the memory access address of the first channel, and calculating the memory access addresses of the other channels based on the memory access address of the first channel; and generating a memory access request based on the memory access address of each channel. According to the method, the throughput rate of the loading storage instruction of the continuous address is improved, the number of ALUs calculated by the memory address is reduced, and meanwhile, the power consumption is reduced.