55 results about "Lockstep" patented technology

The invention provides a heterogeneous flight control computer and a redundancy flight control computer system, the flight control computer comprises a normal mode lockstep calculation unit used for receiving external data and calculating to generate output data, and the output data is a control instruction used for controlling an aviation aircraft. The normal mode lockstep calculation unit selectively adopts one of the following two structures: the first structure comprises two heterogeneous control processors, the two heterogeneous control processors simultaneously calculate the external data to generate two groups of output data, and the two groups of output data are compared to realize lockstep; the second structure comprises a dual-core lockstep processor, two cores are used for calculating the external data at the same time to generate two sets of output data, and lockstep is achieved after the two sets of output data are compared. The invention provides the flight control computer with higher safety.

A method is provided for improving multiplayer user experience in an online video game utilizing a lockstep engine. The method includes receiving user input information from at least one of a plurality of users of a match of the video game that utilizes the lockstep engine. Each of the user input information from the at least one of the plurality of users being associated with a current frame of a plurality of frames of the lockstep engine based on the respective user input information being received within a current time interval of the current frame. The method also includes sending the current frame of the user input information irrespective of whether the user input information is received from each of the plurality of users within the current time interval. Clients no longer need to be in the game at the same time for the game to proceed.

The invention provides a dual-core lock step processor instruction fetching control system supporting an extension instruction. The dual-core lock step processor instruction fetching control system comprises an instruction fetching module, an instruction cache, a branch prediction module, a lock step comparison module and a dual-core lock step processor. According to the method, fine-grained control is carried out on lock step protection modes of different user codes through a lock step extension instruction; the lock step extension instruction adopts a decoding path different from that of a conventional instruction, and directly enters lock step extension instruction decoding logic after the instruction is fetched, so that the lock step extension instruction does not depend on post-stage resource scheduling of a lock step processor and does not depend on a specific instruction set; branch prediction faults are regarded as branch prediction failure conditions and are processed in an instruction fetching module, and it is ensured that the branch prediction faults cannot pollute the rear stage of the dual-core lockstep processor; for a post-stage fault of the dual-core lockstep processor, the instruction fetching module can widen the pulse width of a post-stage fault signal to a difference value of a dual-core instruction period, and aligns instruction streams in the verification core and the execution core by inserting a null operation into an assembly line.

Embodiments of the present disclosure relate to hardware accelerator devices, corresponding systems, and operating methods. A device includes a set of processing circuits arranged in a subset, a set of data memory banks coupled to a memory controller, a control unit, and an interconnection network. The processing circuits are configurable to read first input data from the data memory bank via the interconnection network and the memory controller, process the first input data to generate output data, and write the output data to the data memory bank via the interconnection network and the memory controller. The hardware accelerator device includes a set of configurable lockstep control units that connect the processing circuit interface to the interconnection network. Each configurable lockstep control unit is coupled to a subset of the processing circuits and is selectively activated to operate in a first operating mode or in a second operating mode.

Apparatuses, systems, and methods for implementing temporal lockstep for error detection utilizing a single processor core are provided. For example, a processor core includes a pipeline with an instruction fetch circuit and an instruction decode and execute circuit. The instruction decode and execute circuit comprises a controller including a finite state machine with a plurality of states to control the processor core. A voting circuit is provided to vote on a control signal to control the finite state machine for transitioning from a current state to a next state. The processor core, based at least on the plurality of states of the finite state machine, is configured to: execute the first dummy instruction to generate a first dummy result; store the first dummy result in a first dummy buffer; execute the first real instruction to generate a first real result; compare the results to identify an error.

The present invention provides an instruction fetch control system for a dual-core lockstep processor supporting extended instructions, comprising an instruction fetch module, an instruction cache, a branch prediction module, a lockstep comparison module, and a dual-core lockstep processor. The present invention implements fine-grained control of the lockstep protection mode of different user codes through lockstep extended instructions. Lockstep extended instructions use a decoding path different from conventional instructions, directly entering the lockstep extended instruction decoding logic after instruction fetching, without relying on resource scheduling of the lockstep processor's subsequent stages or a specific instruction set. Branch prediction faults are treated as a type of branch prediction failure and processed in the instruction fetch module to ensure that branch prediction faults do not contaminate the dual-core lockstep processor's subsequent stages. For subsequent stage faults in the dual-core lockstep processor, the instruction fetch module can widen the pulse width of the subsequent stage fault signal to the difference value of the dual-core instruction cycles, and align the instruction streams in the check core and the execution core by inserting no-operations into the pipeline.

The invention provides a satellite-borne control computer and a safety control method thereof, and relates to the technical field of satellite-borne equipment. The dual-redundancy FPGA security gateway comprises a dual-CPU hot backup master control module, a dual-redundancy FPGA security gateway module and a peripheral module group, wherein the main control module integrates a dual-core lockstep kernel and an application processor kernel, and constructs a CPU redundant architecture combining a static lockstep pool and a dynamic lockstep pool; the state of the system is judged in real time by polling a PMU register and utilizing a health degree fusion algorithm, and then the ranges of the lock step part and the non-lock step part in the dynamic lock step pool are dynamically regulated and controlled. Meanwhile, a traditional full-static redundancy mode is broken through, task allocation is carried out according to work importance classification of instructions, and it is ensured that high-critical tasks preferentially obtain lock step redundancy protection; in addition, according to the invention, different satellite-borne control algorithms are subjected to local analogue simulation by using an idle kernel, and seamless switching of the satellite-borne control algorithms is realized by using switching between the master CPU and the slave CPU.

This invention proposes a microprocessor architecture, including: a master core, a slave core, a bus, and a comparator. The master core and the comparator are communicatively connected to the bus, and the slave core is communicatively connected to the comparator. When the microprocessor is in lockstep mode, the comparator blocks the slave core's access requests to the bus. Both the master core and the slave core execute the master core's tasks. The comparator compares the master core's execution data with the slave core's execution data to detect faults in the execution status of the master core's tasks. The invention also provides a microprocessor fault detection method, including: setting the microprocessor's operating mode according to task requirements, including lockstep mode and non-lockstep mode; if the microprocessor is in lockstep mode, both the master core and the slave core execute the master core's tasks, and faults in the execution status of the master core's tasks are detected by comparing the master core's execution data with the slave core's execution data.

A lockstep testing system includes a lockstep controller that generates various control signals. The lockstep testing system further includes various lockstep circuitries, with each lockstep circuitry including primary and redundant functional circuits that are operable in a lockstep mode, and a fault injection circuit that receives a control signal from the lockstep controller and injects a transient fault in the corresponding lockstep circuitry. The transient fault can be injected at one of input and output stages of the primary and redundant functional circuits. Each lockstep circuitry further includes a checker circuit that tests whether the corresponding lockstep circuitry is faulty (i.e., whether the injected fault is accurately detected), and generates and provides, to the lockstep controller, a fault indication signal indicating whether the corresponding lockstep circuitry is faulty.

The present invention provides a multi-threaded software and hardware fault analysis method and device applied to a lockstep core, relating to the technical field of software and hardware fault monitoring of an ECU, comprising: detecting the internal hardware of a multi-core processor and the software process of each thread in a current cycle respectively; if the internal hardware has a fault in the current cycle, storing and backing up first software and hardware information at a first current moment according to a preset fault type, and resetting the internal hardware; if the software process has a fault in the current cycle, storing and backing up second software and hardware information at a second current moment according to a preset fault type, and resetting the software process; analyzing the software and hardware faults of the lockstep core based on the first software and hardware information and the second software and hardware information; and alleviating the technical problem of data interference and data pollution caused by subsequent fault analysis using such backup data by unifying hardware fault detection and software fault detection under the same timing.

This invention discloses a fault handling method based on a dual-core lockstep processor. The dual-core lockstep processor includes a master processor and a slave processor. The dual-core lockstep processor receives data from the last four stages of the processor's pipeline via a fault detection module, outputting a fault flag signal and a fault program pointer. A front-end fault handling module receives the fault flag signal and the fault program pointer, performing a pipeline-level rollback. A back-end fault handling module controls the handshake and selection signals of the last four stages of the pipeline and executes a virtual write-back fault-tolerance mechanism, managing the operating status of the last four stages of the pipeline and the instruction fetch stage pipeline. This prevents data conflicts during superscalar processor fault handling, thereby achieving full coverage of fault handling while maintaining low time and area overhead, and simultaneously achieving high performance and high reliability. This invention can be widely applied in the field of dual-core lockstep processors.

The invention relates to a validity verification method and device based on a dual-core lockstep mechanism, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring fault injection configuration parameters for performing electromagnetic fault injection; the fault injection configuration parameters comprise fault generation parameters, and the fault injection configuration parameters indicate to-be-verified functions; a verification instruction corresponding to the to-be-verified function is sent to a chip with a dual-core lockstep processor, so that the chip is switched to a test program corresponding to the to-be-verified function; electromagnetic interference is injected into the chip based on the fault generation parameters so as to trigger a dual-core lockstep processor of the chip to break down; and when the to-be-verified function is a fault detection function, obtaining a fault detection state and a fault output signal output by the chip, and verifying the validity of the fault detection function according to the fault detection state and the fault output signal. By adopting the method, the reliability of a verification result of validity verification based on dual-core overlock can be improved.

The invention is suitable for the technical field of chip fault recovery, and provides a dual-core lockstep processor fault recovery device and method. According to the method, before the fault of the processor is recovered, self-inspection is carried out on related system components required by running of the processor, the specific self-inspection content can be configured and comprises chip component self-inspection, processor self-inspection, software self-inspection and the like, selective recovery is carried out on abnormal parameters or states according to the self-inspection states, and the self-inspection efficiency is improved. It is ensured that the current software and hardware state allows the system rollback operation, recovery is ensured without adopting a multi-recovery-point or overall reset mode, and the reliability of fault recovery is ensured.

A completely de-energizable defibrillator is provided, allowing the electrical components of the defibrillator to be electrically unbiased while the defibrillator is not in use. The energizing of the defibrillator can be controlled through a power switch interfaced to a relay, with the microcontroller of the AED being able to de-energize the circuitry in case of unintended activation. Additionally, the microcontroller unit of the AED includes features to prevent computational errors due to external influences, electromagnetic interference, radio frequency interference, ionizing radiation, high energy particles, cosmic radiation, and / or solar radiation, or a combination thereof, including one or more pairs of lockstep processors, error detection code, and features that prevent tampering with the microcontroller.

The present disclosure relates to a semiconductor device. The semiconductor device performs software lockstep. The semiconductor device includes a first circuit group including a first intellectual property (IP) to be operated in a first address space, a first bus, and a first memory; a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory; a third bus connectable to a third memory; and a transfer control circuit coupled with the first bus to the third bus. When software lockstep is performed, the second circuit group converts an access address from the second IP to the second memory so that an address allocated to the second memory in the second address space is the same as an address allocated to the first memory in the first address space.

The present invention is applicable to the field of chip fault recovery technology and provides a dual-core lockstep processor fault recovery device and method. Before recovering from a processor fault, the present invention performs a self-test on the relevant system components required for processor operation. The specific self-test content is configurable and includes chip component self-test, processor self-test, software self-test, etc. Based on the self-test status, abnormal parameters or states are selectively restored to ensure that the current software and hardware states allow system rollback operations. This eliminates the need for multiple recovery points or a full reset to ensure recovery, thereby ensuring the reliability of fault recovery.

The invention discloses a multi-service demand adaptation method and device based on a single chip, equipment and a medium. The method comprises the following steps: dividing a plurality of processing cores in the system-on-chip into at least one processing domain based on service requirements; configuring a memory access permission for each processing domain so as to realize memory access isolation among different processing domains; configuring a hardware resource access permission for each processing domain so as to realize hardware resource access isolation between different processing domains; if a plurality of processing domains are obtained through division, an inter-domain cache consistency maintenance mechanism is configured; if a processing domain is obtained through division, an intra-domain cache consistency maintenance mechanism is configured; wherein the plurality of processing cores are connected through a consistent interconnection network; and configuring the processing core in the target processing domain into a lock step operation mode according to the function security level requirement corresponding to the service requirement. According to the method and the device, the cost and the time for developing special chips for different scenes are reduced, and multiplexing of hardware resources and improvement of research and development efficiency are realized.

A method for fault detection in a dual core lockstep microcontroller is provided. The method may include executing a set of instructions by a first central processing circuitry, executing the set of instructions by one or more second central processing circuitries operating in parallel with the first central processing circuitry, comparing an output from the first central processing circuitry with an output from one or more second central processing circuitries using a first comparator, comparing the output from the first central processing circuitry with the output from the one or more second central processing circuitries using one or more second comparators, and triggering, by at least one logic gate, a fault signal in response to output signals received from the first comparator and the one or more second comparators.

A method of explicit lockstep for functional safety includes spawning, by a main thread, a first safe thread core and a second safe thread core. The method also includes initializing and mapping a first data register associated with the first safe thread core to each safe variable of a set of predetermined safe variables. The method further includes initializing and mapping a second data register associated with the second safe thread core to each safe variable of the set of predetermined safe variables. The method also includes comparing, by a hardware comparator, a first safe variable value in the first data register to a second safe variable value in the second register. The method further includes issuing an error completion to the first safe thread core and the second safe thread core when the hardware comparator detects a mismatch between the first data register and the second data register.

A single-chip-based multi-service requirement adaptation method, device, equipment and medium. The method comprises: dividing a plurality of processing cores in a system-level chip into at least one processing domain based on service requirements; configuring memory access permissions for each processing domain to realize memory access isolation between different processing domains; configuring hardware resource access permissions for each processing domain to realize hardware resource access isolation between different processing domains; if a plurality of processing domains are obtained by division, a domain-to-domain cache consistency maintenance mechanism is configured; if one processing domain is obtained by division, an intra-domain cache consistency maintenance mechanism is configured; wherein the plurality of processing cores are connected through a consistent interconnection network; and the processing cores in the target processing domain are configured to a lockstep running mode according to the functional safety level requirement corresponding to the service requirement. Through the present application, the cost and time for developing special-purpose chips for different scenarios are reduced, and the reuse of hardware resources and the improvement of research and development efficiency are realized.

The invention relates to the technical field of chip architectures, and provides a lockstep core processor, a lockstep core reset circuit and electronic equipment, a clock reset control circuit in a verification core delays a system reset signal and inputs the delayed system reset signal to a system reset logic circuit, so that the system reset logic circuit can reset the system reset signal when performing reset processing; the reset delay time is the same as the input signal delay time, and the verification core can be reset only after completing the same operation as the main core, so that the problem of lock losing alarm caused by inconsistent reset time points of the verification core and the main core and inconsistent storage contents of a non-reset register during local reset is avoided, and the safety is improved.

The application provides a neural network-oriented accelerator, which comprises a main processing core, an input buffer, a controller, a main systolic array and an output buffer, the input buffer is used for storing feature maps and weight parameters of a neural network, the controller is used for generating operation signals to read the feature maps and the weight parameters from the input buffer, the main systolic array is used for receiving the feature maps and the weight parameters and performing calculation to obtain an output sequence; a sorter is used for reordering each element in the output sequence to select a to-be-detected sequence, a lockstep processing core is used for recalculating the value of each element in the to-be-detected sequence through a lockstep systolic array to obtain a check sequence; a check logic module is used for comparing whether the values of the same elements in the to-be-detected sequence and the check sequence are the same; and an error recovery module is used for recalculating the values of all elements in the to-be-detected sequence that do not pass the check according to a preset recalculation mechanism.

An exemplary fault-tolerant computing system includes a secondary processor configured to execute with a primary processor from a common program store in a delay lock-step manner, a comparator in a stored data and write-back path to detect a fault based on comparing a primary processor state and a secondary processor state, and allowing a write-back path delay that aborts execution when a fault is detected prior to write-back of invalid data. Auxiliary processor execution and main processor storage data and write back may be delayed by a predetermined number of cycles, allowing fault detection prior to writing invalid data. The storage data and write-back path may include a triple module redundancy configured to delay a level of most data only through the storage data and write-back path. Some embodiments may forward data from the storage data path delay stage to a write-back stage or memory if the load data address matches the address of data in the storage data path delay stage.

The invention relates to a novel lockstep safety system capable of covering a latent fault, and the system comprises a first time sequence module which is configured to receive external input data and send the data to a function core and a shadow core; a functional core; a shadow core; the second time sequence module comprises a first self-detection beating module and a second self-detection beating module, the first self-detection beating module sends an execution result of the functional core to the comparator, or the first self-detection beating module generates first data and sends the first data to the comparator; the second self-detection beating module sends the execution result of the shadow core to the comparator, or the second self-detection beating module generates second data and sends the second data to the comparator; and the comparator is configured to receive the execution results sent by the first self-detection beating module and the second self-detection beating module and compare the execution results to diagnose whether the functional core and the shadow core have faults or to receive and compare the first data and the second data to diagnose whether the comparator itself has faults.

The application discloses a processor lockstep device and related components, and relates to the field of processors, comprising a lockstep module and an abstract generation module corresponding to each processor. Each abstract generation module generates abstract data according to the running data of each processor. The lockstep module compares whether the abstract data is consistent to determine whether each processor is working normally. The abstract generation module extracts abstract data from the running data of each processor, and the lockstep is completed based on the abstract data. On the basis of realizing the judgment of whether each processor is working normally, the amount of data to be compared in the lockstep process is reduced, and the integrity of the running data of each processor to be transmitted is ensured.

Apparatuses, systems, and methods for implementing temporal lockstep for error detection utilizing a single processor are provided. For example, a processor includes a controller, wherein the controller includes a finite state machine comprising a plurality of states. The processor, based at least on the plurality of states of the finite state machine, is configured to fetch a first instruction, generate a first dummy instruction based on the first instruction and a first real instruction based on the first instruction, execute the first dummy instruction to generate a first dummy result; store the first dummy result in a first dummy buffer, execute the first real instruction to generate a first real result, and compare the first dummy result stored in the first dummy buffer with the first real result to identify an error.

A method of explicit lockstep for functional security includes deriving, by a main thread, a first security thread core and a second security thread core. The method also includes initializing a first data register associated with the first security thread core and mapping it to each security variable in a set of predetermined security variables. The method also includes initializing a second data register associated with a second security thread core and mapping it to each security variable in a set of predetermined security variables. The method further includes comparing, by a hardware comparator, a first security variable value in the first data register to a second security variable value in the second register. The method further includes issuing an erroneous completion to the first secure thread core and the second secure thread core when the hardware comparator detects a mismatch between the first data register and the second data register.

A method is provided for replaying a match in a video game. The method includes receiving player input information of the match in the video game that utilizes a lockstep game engine. The player input information includes player input data for each of a plurality of frames of the lockstep game engine. The method also includes generating a plurality of game states of the match in the video game based on the player input data for each of the plurality of frames. The method further includes storing the plurality of game states of the match in at least one memory. The method also includes receiving a selection of a playback point of the match. The method further includes generating the plurality of video frames of the match using the stored plurality of game states based on the selected playback point.

The application discloses a kind of coaxial shafting engine intelligent layered distributed control method and system, to solve the problem of slow control response, poor fuel adaptability and safety linkage lag caused by high-speed shafting strong coupling.The method comprises: performing system self-checking calibration, driving shafting to establish self-sustaining operation, loading to steady state and performing speed fuel double closed loop, double flow path thermal management, multi-fuel self-adaptation and efficiency optimization, and triggering hardware level protection when abnormal.The system comprises: multi-core lockstep MCU decision layer, FPGA fast execution layer and sensor executor network;MCU is responsible for logical decision and optimization, FPGA is responsible for hard real-time control and physical level emergency stop.The application separates decision and execution logic through layered architecture, can realize hard real-time stable control under high-speed working condition and multi-fuel variable working condition disturbance-free switching, while ensuring material safety, significantly improves system cycle efficiency and operation and maintenance intelligent level.

Systems and methods related to area-efficient functional safety are disclosed. A main core may have a first physical design and register transfer level (RTL) description. A secondary core may have a second physical design. The secondary core may have the same RTL description, but the first physical design may focus on performance and speed while the second physical design focuses on area-efficiency or low power. The secondary core may have a portion of the same RTL, but a different RTL description overall. The portion that is described by the same RTL may be an error prone portion of the main core. In either case, the secondary core may be physically smaller than the main core. The secondary core may be used to monitor for errors of the main core during operation. The main core may slow down when the main core and secondary core are operated in lockstep.