5 results about "Lockstep" patented technology

A single-chip-based multi-service requirement adaptation method, device, equipment and medium. The method comprises: dividing a plurality of processing cores in a system-level chip into at least one processing domain based on service requirements; configuring memory access permissions for each processing domain to realize memory access isolation between different processing domains; configuring hardware resource access permissions for each processing domain to realize hardware resource access isolation between different processing domains; if a plurality of processing domains are obtained by division, a domain-to-domain cache consistency maintenance mechanism is configured; if one processing domain is obtained by division, an intra-domain cache consistency maintenance mechanism is configured; wherein the plurality of processing cores are connected through a consistent interconnection network; and the processing cores in the target processing domain are configured to a lockstep running mode according to the functional safety level requirement corresponding to the service requirement. Through the present application, the cost and time for developing special-purpose chips for different scenarios are reduced, and the reuse of hardware resources and the improvement of research and development efficiency are realized.

The application provides a neural network-oriented accelerator, which comprises a main processing core, an input buffer, a controller, a main systolic array and an output buffer, the input buffer is used for storing feature maps and weight parameters of a neural network, the controller is used for generating operation signals to read the feature maps and the weight parameters from the input buffer, the main systolic array is used for receiving the feature maps and the weight parameters and performing calculation to obtain an output sequence; a sorter is used for reordering each element in the output sequence to select a to-be-detected sequence, a lockstep processing core is used for recalculating the value of each element in the to-be-detected sequence through a lockstep systolic array to obtain a check sequence; a check logic module is used for comparing whether the values of the same elements in the to-be-detected sequence and the check sequence are the same; and an error recovery module is used for recalculating the values of all elements in the to-be-detected sequence that do not pass the check according to a preset recalculation mechanism.

A system (300) includes a memory (206) configured to store test patterns. A first lockstep core (102) and a second lockstep core (104) are configured to receive a same set of test patterns. During a reset of the first lockstep core and the second lockstep core, a first scan output is generated from the first lockstep core (102) and a second scan output is generated from the second lockstep core (104). A comparator (306) can be coupled to the first lockstep core and the second lockstep core and configured to compare the first scan output and the second scan output. If the first and second scan outputs are the same, the first and second lockstep cores (102, 104) can be initialized to a similar state. The first and second lockstep cores can comprise non-resettable flip-flops.

This application discloses a dual-core lockstep circuit, a controller, and a vehicle. The dual-core lockstep circuit includes: a first processor configured to be coupled to a first signal terminal; a second processor configured to be coupled to the first signal terminal via a first register circuit; a control circuit configured to be coupled to the first register circuit and a clock signal line, providing a clock signal to the first register circuit based on the signal states of its input and output terminals; wherein, the control circuit provides a clock signal when the signal states are different, and does not provide a clock signal when the signal states are the same. A comparator circuit configured to be coupled to the output terminal of the second processor determines the validity of the first processor's function based on first data and second data. This application can reduce the power consumption of the dual-core lockstep circuit and the applied vehicle, achieving power savings with finer granularity, improving the overall circuit reliability, and enhancing the stability of the applied system.

This invention discloses a fine-grained, lock-step-tolerant, superscalar out-of-order processor design method and system. The method includes: reading the current instruction address and performing branch prediction to obtain the fetch address of the next instruction; decoding the instruction fetch to extract the opcode, source operand register number, and destination operand register number; renaming the instruction decoding result; processing the renamed instruction decoding result through a reservation station module; performing arithmetic and logical operations on the arbitrated instruction decoding result; comparing and checking the results of executed instructions and writing them into the system; reordering and buffering the written results of executed instructions before committing them to construct the superscalar out-of-order processor. This invention improves the fault detection and recovery capabilities of superscalar out-of-order processors. As a fine-grained, lock-step-tolerant, superscalar out-of-order processor design method and system, this invention can be applied to the field of fault-tolerant processor design technology.