14 results about "Lockstep" patented technology

This invention discloses a fault handling method based on a dual-core lockstep processor. The dual-core lockstep processor includes a master processor and a slave processor. The dual-core lockstep processor receives data from the last four stages of the processor's pipeline via a fault detection module, outputting a fault flag signal and a fault program pointer. A front-end fault handling module receives the fault flag signal and the fault program pointer, performing a pipeline-level rollback. A back-end fault handling module controls the handshake and selection signals of the last four stages of the pipeline and executes a virtual write-back fault-tolerance mechanism, managing the operating status of the last four stages of the pipeline and the instruction fetch stage pipeline. This prevents data conflicts during superscalar processor fault handling, thereby achieving full coverage of fault handling while maintaining low time and area overhead, and simultaneously achieving high performance and high reliability. This invention can be widely applied in the field of dual-core lockstep processors.

The present disclosure relates to a semiconductor device. The semiconductor device performs software lockstep. The semiconductor device includes a first circuit group including a first intellectual property (IP) to be operated in a first address space, a first bus, and a first memory; a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory; a third bus connectable to a third memory; and a transfer control circuit coupled with the first bus to the third bus. When software lockstep is performed, the second circuit group converts an access address from the second IP to the second memory so that an address allocated to the second memory in the second address space is the same as an address allocated to the first memory in the first address space.

The invention discloses a multi-service demand adaptation method and device based on a single chip, equipment and a medium. The method comprises the following steps: dividing a plurality of processing cores in the system-on-chip into at least one processing domain based on service requirements; configuring a memory access permission for each processing domain so as to realize memory access isolation among different processing domains; configuring a hardware resource access permission for each processing domain so as to realize hardware resource access isolation between different processing domains; if a plurality of processing domains are obtained through division, an inter-domain cache consistency maintenance mechanism is configured; if a processing domain is obtained through division, an intra-domain cache consistency maintenance mechanism is configured; wherein the plurality of processing cores are connected through a consistent interconnection network; and configuring the processing core in the target processing domain into a lock step operation mode according to the function security level requirement corresponding to the service requirement. According to the method and the device, the cost and the time for developing special chips for different scenes are reduced, and multiplexing of hardware resources and improvement of research and development efficiency are realized.

A single-chip-based multi-service requirement adaptation method, device, equipment and medium. The method comprises: dividing a plurality of processing cores in a system-level chip into at least one processing domain based on service requirements; configuring memory access permissions for each processing domain to realize memory access isolation between different processing domains; configuring hardware resource access permissions for each processing domain to realize hardware resource access isolation between different processing domains; if a plurality of processing domains are obtained by division, a domain-to-domain cache consistency maintenance mechanism is configured; if one processing domain is obtained by division, an intra-domain cache consistency maintenance mechanism is configured; wherein the plurality of processing cores are connected through a consistent interconnection network; and the processing cores in the target processing domain are configured to a lockstep running mode according to the functional safety level requirement corresponding to the service requirement. Through the present application, the cost and time for developing special-purpose chips for different scenarios are reduced, and the reuse of hardware resources and the improvement of research and development efficiency are realized.

The application provides a neural network-oriented accelerator, which comprises a main processing core, an input buffer, a controller, a main systolic array and an output buffer, the input buffer is used for storing feature maps and weight parameters of a neural network, the controller is used for generating operation signals to read the feature maps and the weight parameters from the input buffer, the main systolic array is used for receiving the feature maps and the weight parameters and performing calculation to obtain an output sequence; a sorter is used for reordering each element in the output sequence to select a to-be-detected sequence, a lockstep processing core is used for recalculating the value of each element in the to-be-detected sequence through a lockstep systolic array to obtain a check sequence; a check logic module is used for comparing whether the values of the same elements in the to-be-detected sequence and the check sequence are the same; and an error recovery module is used for recalculating the values of all elements in the to-be-detected sequence that do not pass the check according to a preset recalculation mechanism.

The application discloses a processor lockstep device and related components, and relates to the field of processors, comprising a lockstep module and an abstract generation module corresponding to each processor. Each abstract generation module generates abstract data according to the running data of each processor. The lockstep module compares whether the abstract data is consistent to determine whether each processor is working normally. The abstract generation module extracts abstract data from the running data of each processor, and the lockstep is completed based on the abstract data. On the basis of realizing the judgment of whether each processor is working normally, the amount of data to be compared in the lockstep process is reduced, and the integrity of the running data of each processor to be transmitted is ensured.

A method and system are disclosed for adaptive lossless data compression using a predictive model that is updated deterministically in lockstep at both encoder and decoder. An encoder generates symbol probability distributions from a frozen base model with a small set of updatable parameters, encodes input blocks via entropy coding, and applies deterministic parameter updates using the observed data. A decoder entropy-decodes the compressed bitstream, reconstructs the same blocks, and applies identical updates, thereby maintaining synchronization without transmission of model parameters. Optional features include periodic beacons for state verification and resynchronization, error-control metadata, and modality-specific tokenization. In preferred embodiments, parameter adaptation is confined to adapter modules within a largely fixed neural network, ensuring computational efficiency and reproducibility across platforms. Over time, the model specializes to the stream, reducing average coding rate while guaranteeing exact reconstruction of the original data.

The application provides a satellite-borne control computer and a safety control method thereof, and relates to the technical field of satellite-borne equipment; the application comprises a main control module of double-CPU hot backup, a double-redundancy FPGA safety gateway module and a peripheral module group; wherein the main control module adopts a CPU redundancy architecture combining a static lockstep pool and a dynamic lockstep pool by integrating a dual-core lockstep kernel and an application processor kernel; the system state is judged in real time by polling a PMU register and using a health degree fusion algorithm, and then the range of the lockstep and non-lockstep parts in the dynamic lockstep pool is dynamically regulated. Meanwhile, the application breaks through the traditional full-static redundancy mode, and task allocation is performed according to the importance classification of instructions, so that high-key tasks can be ensured to obtain lockstep redundancy protection in priority; in addition, the application also uses the idle kernel to perform local simulation of different satellite-borne control algorithms, and uses the switching between the master CPU and the slave CPU to realize seamless switching of the satellite-borne control algorithm.

A system (300) includes a memory (206) configured to store test patterns. A first lockstep core (102) and a second lockstep core (104) are configured to receive a same set of test patterns. During a reset of the first lockstep core and the second lockstep core, a first scan output is generated from the first lockstep core (102) and a second scan output is generated from the second lockstep core (104). A comparator (306) can be coupled to the first lockstep core and the second lockstep core and configured to compare the first scan output and the second scan output. If the first and second scan outputs are the same, the first and second lockstep cores (102, 104) can be initialized to a similar state. The first and second lockstep cores can comprise non-resettable flip-flops.

This application discloses a dual-core lockstep circuit, a controller, and a vehicle. The dual-core lockstep circuit includes: a first processor configured to be coupled to a first signal terminal; a second processor configured to be coupled to the first signal terminal via a first register circuit; a control circuit configured to be coupled to the first register circuit and a clock signal line, providing a clock signal to the first register circuit based on the signal states of its input and output terminals; wherein, the control circuit provides a clock signal when the signal states are different, and does not provide a clock signal when the signal states are the same. A comparator circuit configured to be coupled to the output terminal of the second processor determines the validity of the first processor's function based on first data and second data. This application can reduce the power consumption of the dual-core lockstep circuit and the applied vehicle, achieving power savings with finer granularity, improving the overall circuit reliability, and enhancing the stability of the applied system.

Systems and methods that provide for executing a machine learning model in lockstep with a real-time transaction processing system are described. An example system includes a feature store in a memory, processes storing real-time data, including a clock signal, in designated memory regions in the feature store, and processes controlling the execution of the machine learning model in accordance with the clock signal.

The utility model discloses a dual-core lockstep processor hardware error detection and correction system, which relates to the technical field of processors and comprises a master processor, a slave processor, an error monitoring module, a backtracking address generation module and an instruction flushing backtracking control module. The error monitoring module is used for comparing and monitoring the main processor and the slave processor, and when the output data of the main processor and the slave processor are different, a dual-core lock step error signal is triggered; the instruction flushing backtracking control module is used for sending an assembly line emptying signal and an instruction backtracking signal when receiving the error signal; the backtracking address generation module is used for generating a backtracking instruction address when receiving the error signal; and when receiving the assembly line emptying signal and the instruction backtracking signal, the main processor and the slave processor are used for emptying the instruction operated by the current assembly line and then obtaining the instruction again according to the address of the backtracking instruction to realize error correction. The scheme does not depend on software, hardware self-inspection and self-correction can be completed, and the recovery time required for detecting and recovering the transient fault is greatly shortened.

This invention discloses a fine-grained, lock-step-tolerant, superscalar out-of-order processor design method and system. The method includes: reading the current instruction address and performing branch prediction to obtain the fetch address of the next instruction; decoding the instruction fetch to extract the opcode, source operand register number, and destination operand register number; renaming the instruction decoding result; processing the renamed instruction decoding result through a reservation station module; performing arithmetic and logical operations on the arbitrated instruction decoding result; comparing and checking the results of executed instructions and writing them into the system; reordering and buffering the written results of executed instructions before committing them to construct the superscalar out-of-order processor. This invention improves the fault detection and recovery capabilities of superscalar out-of-order processors. As a fine-grained, lock-step-tolerant, superscalar out-of-order processor design method and system, this invention can be applied to the field of fault-tolerant processor design technology.

Techniques herein involve operations for reducing divergence for ray tracing. In ray tracing on parallel hardware, rays are processed in “wavefronts” which include multiple threads that execute in lockstep. High divergence can occur in ray tracing as ray processing can have very outcomes. Techniques presented herein reduce divergence by swapping rays between wavefronts at intermediate processing points. The swapping groups more coherent rays together, thereby reducing divergence and increasing efficiency.