Method, device and circuit for synchronizing signals between nodes under Lockstep architecture

Abstract

The invention provides a method, device and circuit for synchronizing signals between nodes under a Lockstep architecture. The method comprises the following steps of: receiving a first ready signal for representing whether a first node is ready or not; carrying out delay of n clock periods on the first ready signal to obtain a local synchronization signal; wherein n is an integer greater than 1;delay of m clock periods is carried out on the first ready signal to obtain a delay ready signal of the first node, and m is a positive integer smaller than n; sending a delay ready signal of the first node to a second node; the structure of the second node is completely the same as that of the first node; receiving a delay ready signal of a second node sent by the second node; performing n-m clock period delay on the delay ready signal of the second node to obtain a far-end synchronization signal; and when the local synchronization signal and the remote synchronization signal are valid at thesame time, setting the target key signal of the first node to be valid.

Description

technical field [0001] The invention relates to the field of high-safety embedded computing, in particular to an inter-node signal synchronization method, device and circuit under the Lockstep architecture. Background technique [0002] Lockstep (Lockstep) technology is an advanced technology used to improve computing integrity, and is mainly used in embedded computing fields with high safety requirements, such as avionics systems of civil aircraft. Lockstep technology uses multiple sets of redundant hardware components (processor, FPGA / ASIC, memory, etc.) to allow multiple processing nodes to execute the same instruction accurately and synchronously at the same time through synchronous comparison during operation. [0003] figure 1 It is a typical Lockstep technical architecture. Two groups of hardware components run in lockstep, each group of hardware includes processor, FPGA / ASIC, memory, equipment, etc., and the two groups of hardware use a unified reference clock. Us...

AI Technical Summary

Problems solved by technology

If the internal key signals of the FPGA / ASIC of different nodes are not synchronized with each other, it may cause the lock-step comparison to fail, and then trigger a system failure

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