Method, device and circuit for synchronizing signals between nodes under Lockstep architecture

A signal synchronization, inter-node technology, applied in response error generation, electrical digital data processing, hardware redundancy in data error detection, etc., can solve key signal asynchrony, lockstep comparison failure, system failure and other problems to achieve the effect of improving operation stability and avoiding lockstep comparison errors.

Active Publication Date: 2019-08-27
XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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  • Application Information

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Problems solved by technology

If the internal key signals of the FPGA/ASIC of different nodes are not synchronized with e

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  • Method, device and circuit for synchronizing signals between nodes under Lockstep architecture
  • Method, device and circuit for synchronizing signals between nodes under Lockstep architecture
  • Method, device and circuit for synchronizing signals between nodes under Lockstep architecture

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Embodiment Construction

[0048]The internal signals of the FPGA / ASIC of different nodes in the Lockstep architecture will be asynchronous between nodes due to some unavoidable objective reasons. This asynchrony may cause lockstep comparison errors and affect the stable operation of the Lockstep system. The present invention proposes a signal synchronization method between nodes under the Lockstep framework, which effectively solves this problem.

[0049] The design method of the present invention can realize the complete synchronization of key signals inside the FPGA / ASIC of different nodes in the Lockstep architecture, so that on the one hand, it can avoid the lockstep comparison error caused by the out-of-sync key signals between nodes, and on the other hand, it can also ensure that different The FPGA / ASIC of the node can give a fully synchronous output signal to the processor chip, thus improving the operational stability of the Lockstep system. In addition, the design method of the present inventi...

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Abstract

The invention provides a method, device and circuit for synchronizing signals between nodes under a Lockstep architecture. The method comprises the following steps of: receiving a first ready signal for representing whether a first node is ready or not; carrying out delay of n clock periods on the first ready signal to obtain a local synchronization signal; wherein n is an integer greater than 1;delay of m clock periods is carried out on the first ready signal to obtain a delay ready signal of the first node, and m is a positive integer smaller than n; sending a delay ready signal of the first node to a second node; the structure of the second node is completely the same as that of the first node; receiving a delay ready signal of a second node sent by the second node; performing n-m clock period delay on the delay ready signal of the second node to obtain a far-end synchronization signal; and when the local synchronization signal and the remote synchronization signal are valid at thesame time, setting the target key signal of the first node to be valid.

Description

technical field [0001] The invention relates to the field of high-safety embedded computing, in particular to an inter-node signal synchronization method, device and circuit under the Lockstep architecture. Background technique [0002] Lockstep (Lockstep) technology is an advanced technology used to improve computing integrity, and is mainly used in embedded computing fields with high safety requirements, such as avionics systems of civil aircraft. Lockstep technology uses multiple sets of redundant hardware components (processor, FPGA / ASIC, memory, etc.) to allow multiple processing nodes to execute the same instruction accurately and synchronously at the same time through synchronous comparison during operation. [0003] figure 1 It is a typical Lockstep technical architecture. Two groups of hardware components run in lockstep, each group of hardware includes processor, FPGA / ASIC, memory, equipment, etc., and the two groups of hardware use a unified reference clock. Us...

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Application Information

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IPC IPC(8): G06F11/16
CPCG06F11/1604
Inventor 段小虎马小博周啸吴琳刘铎索晓杰
Owner XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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