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Main processor error detection using checker processors

A main processor, error detection technology, applied in the field of data processing, can solve problems such as increasing transient faults

Pending Publication Date: 2019-06-14
ARM LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the number of transistors in a system increases and the feature size decreases, the likelihood of failure increases because smaller transistors are more susceptible to transient errors caused by cosmic ray or other particle strikes, and the potential for smaller feature sizes increases. Increased denaturation will significantly increase the occurrence of transient failures

Method used

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  • Main processor error detection using checker processors
  • Main processor error detection using checker processors
  • Main processor error detection using checker processors

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Embodiment Construction

[0017] Implementing error detection can be challenging, especially with larger and more complex processors. One approach may use a dual-core lockstep technique, where two versions of the same processor are provided and the same instruction is executed in parallel on the same input, so that there can be a gap between the results of the two processors. An error was detected while diffing. However, this approach requires the second core to keep pace with the first core, so a full second core identical to the first core must be provided, doubling the area and power consumption of the processing system. This can be a significant cost, especially when the host processor is a relatively complex high-performance processor (eg, one that supports out-of-order execution). Furthermore, since many interfaces of the corresponding cores are compared to detect errors, a lot of extra wiring will be required. For more complex processors, due to the physical size of these processors and the re...

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Abstract

An apparatus (2) comprises a main processor (4) to execute a main stream (30) of program instructions, two or more checker processors (20) to execute respective checker streams (34) of program instructions in parallel with each other, the checker streams corresponding to different portions (32) of the main stream executed by the main processor, and error detection circuitry (28) to detect an errorwhen a mismatch is detected between an outcome of a given portion (32) of the main stream executed on the main processor (4) and an outcome of the corresponding checker stream (34) executed on one ofthe plurality of checker processors (20). This approach enables high performance main processors (4) to be checked for errors with lower circuit area and power consumption overhead than a dual-core lockstep technique.

Description

technical field [0001] This technique relates to the field of data processing, and more specifically, to error detection. Background technique [0002] Hardware faults, including soft (transient) faults and hard (permanent) faults, are increasingly common in data processing systems. As the number of transistors in a system increases and the feature size decreases, the likelihood of failure increases because smaller transistors are more susceptible to transient errors caused by cosmic ray or other particle strikes, and the potential for smaller feature sizes increases. Increased denaturation will significantly increase the occurrence of transient failures. At the same time, workloads executed on data processing systems are increasingly error-tolerant, especially for applications such as the automotive industry, which require stringent safety standards. Therefore, techniques for detecting errors in data processing systems are becoming increasingly important. Contents of th...

Claims

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Application Information

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IPC IPC(8): G06F11/16
CPCG06F11/1629G06F11/1641G06F11/1407
Inventor 萨姆·安斯沃思托马斯·克里斯多夫·格鲁卡特蒂莫西·马丁·琼斯
Owner ARM LTD
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