7831 results about "MicroBlaze" patented technology

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for multi-agent AI collaboration. The system provides a universal multi-modal key-value subsystem for sharing partial computations, implements hybrid placement strategies for dynamic memory management, and incorporates quantum-resistant secure enclaves. The architecture integrates hardware acceleration through GPU-FPGA hybrid caching and neuromorphic processors, applies adaptive energy and thermal management across hardware generations, and implements autonomous flash resource orchestration with multi-dimensional wear management. The system orchestrates tensor workflows using hierarchical scheduling, enables cross-agent collaboration with privacy preservation, and supports continuous learning without catastrophic forgetting. This integration delivers unprecedented computational efficiency and security in high-dimensional decision-making environments while supporting incremental adoption through modular interfaces.

A new transaction barrier synchronization primitive enables executing threads and asynchronous transactions to synchronize across parallel processors. The asynchronous transactions may include transactions resulting from, for example, hardware data movement units such as direct memory units, etc. A hardware synchronization circuit may provide for the synchronization primitive to be stored in a cache memory so that barrier operations may be accelerated by the circuit. A new wait mechanism reduces software overhead associated with waiting on a barrier.

One aspect of the instant disclosure may provide a system and method for processing scatter-gather direct memory access (S-G DMA) instructions. During operation, the system may receive an S-G DMA instruction associated with a message and gather instruction context for the S-G DMA instruction. An S-G DMA processor may process the S-G DMA instruction based on the gathered instruction context and determine whether there exists a pending S-G DMA instruction associated with the message. In response to the presence of the pending S-G DMA instruction, the system stores the instruction context in a hot context cache at an address corresponding to the pending S-G DMA instruction. In response to the absence of the pending S-G DMA instruction, the system stores the instruction context in a cold context cache.

The invention relates to the technical field of computer architecture and parallel computing, and discloses a parallel task scheduling algorithm for a heterogeneous multi-core processor, which comprises the steps of task modeling, resource mapping, dynamic load balancing, communication optimization, task scheduling decision and execution monitoring. Task allocation is adjusted in real time through dynamic load balancing, cross-core communication delay is reduced in combination with communication optimization, and an efficient task allocation sequence is generated by using an improved genetic algorithm. According to the method, the resource utilization rate and the task execution efficiency of the heterogeneous multi-core processor in a high-performance computing scene can be improved, meanwhile, the robustness and adaptability of an algorithm are enhanced, and the task allocation problem in a complex computing scene is effectively solved.

The invention discloses a network card data local preprocessing system fused with edge computing, and relates to the technical field of edge computing and artificial intelligence collaborative optimization. Comprising an edge computing unit, a hierarchical collaborative architecture, a model hot switching and generative fragmentation module, an intention recognition and adaptive scheduling module, a delay energy consumption optimization scheduling module, a CXL zero-copy sharing module, an edge computing unit integrated processor, an FPGA or ASIC and a neuromorphic computing unit. According to the method, an FPGA, an ASIC and a neuromorphic computing unit are integrated in an intelligent network card, microsecond-level dynamic connection reconfiguration and adaptive generative model fragmentation execution are realized through a reconfigurable Mesh interconnection matrix, an attention layer and a feed-forward layer of a Transform class model are fragmented and allocated to different computing units for parallel execution, and cross-card streamlined processing is realized in cooperation with a zero-copy shared memory. And the intention recognition module is deeply coupled with the model hot switching module, so that dynamic model switching and fragmentation strategy optimization based on service priorities and system loads are realized.

A system for real-time detection and mitigation of morphing malware in high-density edge networks, consisting of: a data acquisition unit configured to receive, normalize, and encode multimodal telemetry data streams originating from at least one of the following domains: network traffic, process behavior, system call sequences, binary instruction traces, and control flow graphs; the data acquisition unit is further configured to compute feature embeddings over sliding time windows and apply privacy-preserving redactions prior to storage; a generative neural processor that is operationally coupled to the data acquisition unit and configured to generate synthetic morphing malware variants by learning probabilistic transformations of previously observed malicious data representations, maintaining semantic functionality while varying structural and behavioral features; a discriminative neural processor trained adversarially with the generative neural processor, wherein the discriminative neural processor is configured to detect morphing malware by evaluating a probability distribution over multimodal telemetry embeddings and classifying anomalous process and flow behaviors in real time; a coordination processor that is communicatively connected to both the generative neural processor and the discriminative neural processor and is configured to orchestrate adversarial co-training, regulate detection thresholds, calculate reinforcement-based penalties for false negative results, and trigger countermeasures as soon as a detection confidence level exceeds a predefined adaptive threshold; a secure, system-integrated inference and enforcement unit configured to perform low-latency countermeasures at the network edge, including selective packet filtering, flow isolation, process interruption, or system microsegmentation, based on instructions from the coordinating processor; and a hardware-embedded security enclave that is embedded in the system and configured to store cryptographic keys, neural model parameters, and integrity affirmation data to ensure the confidentiality, authenticity, and immutability of model artifacts and policy configurations.

A system and method for executing computer readable code instructions for an on-the-box (OTB) artificial intelligence (AI) productivity tool comprising a hardware processor accessing capabilities associated with each of a plurality of AI productivity tool-enablable software applications, a natural language capabilities database memory to store natural language descriptions of the capabilities and capability intent values generated from the natural language descriptions in a capabilities decision tree with each capability node grouped under a branch of the capabilities decision tree according to logical topics in hierarchical parent-child relationships, the hardware processor generating a query input intent value from a user query input and performing a cosine semantic similarity search comparing the capability intent values of the capability nodes along the branch of the capabilities decision tree for identifying a best match capability node having a highest cosine semantic similarity search score, and the hardware processor executing the best match capability.

The invention relates to the technical field of intelligent monitoring, in particular to a multi-thread low-power-consumption intelligent monitoring system based on an AI processor. The method has the advantages that aiming at the problems of unbalanced computing power and power consumption, high multi-task processing delay and strong hardware dependence in the prior art, the NPU module of the RK3588 processor is combined with the INT8 quantitative model, so that the power consumption is lower than 10W under the 6TOPS computing power; a dynamic multi-thread scheduling mechanism is designed, parallel processing of more than eight paths of video streams is supported through binding of a priority queue and an NPU core, and end-to-end delay is compressed to be within 200 ms; a zero-copy video stream architecture is constructed, data transfer is eliminated through memory mapping, and preprocessing time consumption is reduced by 90%; an energy efficiency control module is integrated, the NPU voltage frequency is dynamically adjusted according to the load, and the energy efficiency ratio reaches 0.83 TOPS / W; space-time alignment of multi-model reasoning results is realized by adopting a frame ID synchronization technology, and the mismatching rate is lower than 0.1%.

The invention relates to the technical field of computer system structures and storage, in particular to a non-volatile memory quick recovery method based on metadata priority and on-demand loading. The method comprises the following steps: in response to a system fault signal detected by a voltage monitoring unit, freezing a processor context and traversing a page table structure to extract system configuration information; writing the system configuration information and business data codes in the volatile memory into a nonvolatile medium to generate a persistent state mirror image; analyzing the persistent state mirror image, extracting address conversion metadata, and reconstructing a mapping relation from a virtual address to a physical page frame in a volatile memory; and generating an address mapping table, wherein the physical page frame pointed by the address mapping table is set to be in an existing state but is not associated with the effective service data. According to the method, decoupling of the control flow and the data flow is realized by constructing a virtual ready state, and quick starting of the system and immediate response of key services are realized on the premise of not depending on the total capacity of a memory.

The invention discloses a power consumption and performance balanced scheduling method and system for a heterogeneous multi-core processor, and belongs to the technical field of computers, and the method comprises the steps: obtaining historical load data and current system state parameters, generating a load sequence and carrying out load prediction analysis, generating a predicted load value for feature fusion and quantification, and generating a task feature vector; constructing a core capability portrait, calculating a matching degree between the task characteristic vector and the core capability portrait, and generating a scheduling strategy; and dynamically combining the physical cores into a logic calculation unit according to a scheduling strategy, configuring a power consumption state, and executing task allocation and migration. According to the method, the technical means of load prediction analysis, quantitative matching of tasks and cores and dynamic combination and configuration of physical cores are adopted, and pre-judgment and prospective distribution of system resources can be achieved, so that performance requirements are met, meanwhile, the system energy efficiency is effectively optimized, and deep balance of power consumption and performance of a processor is achieved.

An apparatus and method generating an optimal output. The apparatus includes at least a processor and a memory communicatively connected to the at least a processor. The memory instructs the processor to receive a plurality of reference data from an entity input, receive at least an inquiry datum associated with the plurality of reference data from the entity input, train, using entity training data, a first optimizer, generate, using the first optimizer, an optimal output as a function of the at least an inquiry and the plurality of reference data, receive, using the at least a processor, entity feedback comprising at least a correction datum, retrain, using the entity feedback, the first optimizer, display, using a downstream device, the optimal output through a graphical user interface of the downstream device.

The invention relates to the technical field of electric digital data processing, and discloses a multi-dimensional data logic processing method based on an artificial intelligence algorithm, which comprises the following steps: receiving a target discrete data packet, extracting metadata, and calculating to generate a dimension entropy feature vector representing data logic complexity; inputting the vector into a preset topological mapping model, and outputting an initial adjacent matrix; calling a feedback suppression mask matrix generated based on a historical operator utility state, and executing bitwise logic AND operation with the initial adjacent matrix to generate a corrected effective topological matrix; the matrix is analyzed, a logic operator function pointer is dynamically indexed in an instruction cache, and a directed acyclic execution linked list is constructed; according to the method, redundant logic nodes in AI prediction are definitely eliminated through a bit operation mask mechanism based on historical feedback, and deterministic convergence of processing delay and optimal matching of computing power resources are achieved.

The invention discloses a chip surface defect detection method based on a boundary guide hierarchical feature fusion network, and mainly solves the problem that the existing traditional chip surface defect detection technology is low in detection accuracy of chips with tiny defects, fuzzy edges and large scale changes. The implementation scheme is as follows: 1) acquiring a data set and a detection label; 2) constructing a chip surface defect detection model; 3) constructing a loss function; 4) training a chip surface defect detection model; and 5) obtaining a chip surface defect detection result. According to the chip surface defect detection model constructed by the invention, the small target defect detection capability is improved through the dynamic multi-receptive-field attention module; the multi-scale defect detection capability is enhanced through a hierarchical scale attention module; the learning and extraction capabilities are improved through the fusion feature processor module; the weak boundary defect detection capability is improved through an edge guiding attention mechanism module; the method shows excellent precision and efficiency in practical application, and is superior to an existing defect detection algorithm.

The invention discloses an RISC-V vector register pressure-oriented dynamic management method and system, and relates to the technical field of computer processor architecture and compiler optimizing.The method comprises the steps that in the program compiling or executing process, the use state of an RISC-V vector register is monitored in real time, and when it is monitored that the vector register pressure exceeds the limit, the RISC-V vector register pressure is monitored; if yes, selecting a target register and triggering a management strategy; identifying a source instruction of a vector value in the target register, executing heavy materialization validity verification, and dividing the vector value into a heavy materialization type and a non-heavy materialization type according to a verification result; according to a division result, dynamically estimating the heavy materialization cost and the register overflow cost; comparing the two types of costs, and if the heavy material cost is higher, deciding to adopt a register overflow strategy and executing the strategy; and if the overflow cost of the register is higher, a decision is made to adopt a heavy matter strategy and is executed. The computing performance of the processor can be improved, and the problem of performance loss caused by high register pressure is solved.

One or more systems, devices, computer program products and / or computer-implemented methods of use provided herein relate to predicting an optimized result for a graph neural network (GNN). A system can comprise a memory configured to store computer executable components; and a processor configured to execute the computer executable components stored in the memory, wherein the computer executable components comprise: a fusion component that that models non-linear modality correlations within and across entities through Hirschfeld-Gebelein-Re'nyi maximal correlation (MaxCorr) embeddings that generates a multi-graph that preserves identities of modalities and entities; and a multi-graph neural network (MGNN) component for task-informed reasoning in multi-graphs, that learns parameters defining entity-modality graph connectivity and message passing in an end-to-end fashion.

The invention discloses a multi-precision matrix calculation unit and a use method thereof, and relates to the technical field of integrated circuits, the multi-precision matrix calculation unit comprises a control logic unit, a cache module and a calculation array; wherein the control logic unit is used for configuring a computing array and controlling the cache module to read in and read out data; the cache module comprises three first cache sub-modules and one second cache sub-module; wherein the three first cache sub-modules are respectively used for caching a first to-be-processed matrix, a second to-be-processed matrix and a third to-be-processed matrix, and the second cache sub-module is used for caching a result matrix; and the calculation array is used for carrying out multiplication and addition operation on different types of to-be-processed matrixes to obtain a result matrix and writing the result matrix back to the cache module. The method can serve as a basic operation core for integrated processing of large-scale matrix multiplication and can also be integrated in processors such as RISC-V for matrix operation, universality is higher, and the method can adapt to fast and efficient calculation scenes.

In various examples, systems and methods are disclosed relating to coordinating and synchronizing the actions of different types of processors with low latency. Different types of processors may perform better at different types of tasks. By coordinating the processing of a one-dimensional processor such as a vector processing unit (VPU) and the processing of a two-dimensional processor such as a pixel processing engine (PPE), an overall speed of task completion can be improved.

The embodiments of the present application relate to the technical field of terminals. Provided are a rendering processing method and an electronic device. The method comprises: determining a plurality of rendering instructions corresponding to first graphic data to be rendered of a first application program, wherein the plurality of rendering instructions include a first rendering instruction; and then reading, from a graphics processing unit (GPU) memory, a first rendering resource corresponding to the first rendering instruction, and executing the plurality of rendering instructions on the basis of rendering resources respectively corresponding to the plurality of rendering instructions, so as to render the first graphic data. In this way, a rendering resource is read from a GPU memory, so as to reduce data interaction between a GPU and a main memory, thereby reducing the bandwidth consumption of a terminal device.

Embodiments of the subject application relate to methods and apparatuses for a buffer status report (BSR). According to an embodiment of the subject application, a user equipment (UE) includes a processor and a transceiver coupled to the processor; and the processor is configured to: receive, via the transceiver from a network, a configuration for enabling a function of an enhanced buffer status report (EBSR); and transmit the EBSR via the transceiver to the network.

According to the heterogeneous multi-core chip power consumption state control system and the heterogeneous multi-core chip provided by the invention, the power consumption state request of each sub power supply domain is received through the set system hardware power consumption management module, and the driving signal is sent to the corresponding sub power supply domain according to the preset hardware time sequence, so that the corresponding sub power supply domain enters the target state; generating a PMU control signal; and the power management module drives an internal voltage regulator to execute corresponding regulation operation according to the PMU control signal. A special control processor (SCP) is not needed, the system hardware power consumption management module realized by pure hardware is adopted to directly control the power consumption state of each sub power supply domain in the heterogeneous multi-core SoC, the software processing delay is eliminated, the response speed is high, the static power consumption of the power consumption management module is remarkably reduced, and the system is particularly suitable for an ultra-low power consumption scene and has a wide application prospect. And hardware-level surge current protection is realized in a multi-core power-on process.

The invention discloses a matrix multiplication task execution method and device, equipment, a medium and a program product, the method is applied to a processor unit in a graphics processor, and the method comprises the steps that in the process that the processor unit executes a matrix multiplication task, the processor unit executes the matrix multiplication task; distributing a target register for the matrix multiplication task in the processor unit, wherein the target register comprises a shared register; generating at least two types of second thread bundles for executing the matrix multiplication task; the at least two types of second thread bundles asynchronously execute the matrix multiplication task based on the common register; and the common register is used for storing an intermediate result of the matrix multiplication task.

The invention discloses a debugging system and a debugging method of an RISC-V architecture, and relates to the field of processor debugging, the debugging system comprises a debugging host, a transport layer interface, a debugging module, a debugging logic module in a processor core and a monitoring module, and all the components are in communication connection in sequence. According to the invention, by supporting an RV32 / RV64 double-word-length processor, being compatible with a U / S / M full privilege level operation mode and adapting to various mainstream open-source RISC-V cores and self-defined cores, compared with the existing scheme only supporting a single architecture variant, the method does not need to reconstruct debugging logic for different core types, reduces the core adaptation cost, does not need to customize a debugging instruction or a tool chain process, and has the advantages that the debugging efficiency is improved, and the debugging cost is reduced. Through the register and protocol standardization, the method has high compatibility, and the cross-platform debugging cost is reduced.

The invention discloses a quantum bit mapping optimization method for hardware guidance and fidelity perception and a related device, and belongs to the field of quantum computing, and the method comprises the steps: defining each node in a hardware coupling graph of a target quantum processor as an initial community; evaluating all adjacent community pairs according to a reward function defined based on modularity and fidelity of candidate communities, selecting an optimal community pair for fusion, and taking the community with the largest current scale as an optimal candidate area; iteratively executing a community fusion step until a converged single community is obtained; and selecting an optimal candidate region with the physical quantum bit number greater than or equal to the logic quantum bit number of the quantum circuit to be mapped and the minimum scale, and outputting a mapping sub-graph. According to the method, through a recursive community fusion strategy, the operation range of the solver is restrained in a subspace with the scale greatly reduced and the quality better, the problem of combinatorial explosion caused by global search is fundamentally avoided, and the calculation overhead is greatly reduced.

The invention relates to a memory shader. The programmable atomic memory shader execution circuitry is a seamless component of the hierarchical memory system, and can receive and execute programmable atomic operation calls from any number of processors. Programmable atomic memory shader execution circuitry close to memory allows execution circuitry to access shader programs stored in memory, thereby eliminating latency that may occur when an upstream processor exchanges shader instructions, data, and memory lock / unlock commands with the execution circuitry. The locked / unlocked state of the programmable atomic memory shader execution circuitry (e.g., in the L2 or L3 cache memory) allows the system to quickly lock the memory resources, perform one or more operations in an atomic manner over one or more cycles, and then quickly unlock the memory resources.

The invention discloses a memory management method and related equipment, and relates to the technical field of data storage, the method comprises the following steps: based on access information of memory pages of a target operating system, determining a dynamic popularity score of each memory page; on the basis of the current memory pressure level and the dynamic popularity score of the target operating system, executing a corresponding hierarchical data migration strategy so as to migrate different memory pages to the corresponding main Swap storage space or auxiliary Swap storage space; adjusting a compression algorithm applied to the auxiliary Swap storage space based on the current central processing unit utilization rate of the target operating system; and detecting real-time states of the main Swap storage space, the auxiliary Swap storage space and the physical memory, and adjusting a hierarchical data migration strategy and a compression algorithm based on a detection result. Through dynamic popularity perception, hierarchical data migration, adaptive compression regulation and cross-layer collaborative optimization, the memory utilization rate, the exchange efficiency and the overall system stability can be improved under different system loads.

The embodiment of the invention discloses an interrupt processing method, a processor, a chip, a storage medium and a program product, and the method comprises the steps: determining the remaining processing time of an assembly line of a target task based on the state of the assembly line of the target task being processed in response to a to-be-processed interrupt signal; determining the real-time weight of the interrupt signal to be processed based on the interrupt type of the interrupt signal to be processed and the current working mode of a processor; the real-time weight is used for representing the urgency of the interrupt signal to be processed; determining a response score of the interrupt signal to be processed based on the remaining processing time of the pipeline and the real-time weight; the response score represents the response priority of the interrupt signal to be processed; and in response to the response score reaching a first threshold value, triggering interrupt preemption, and processing the interrupt signal to be processed.

A gaming system including a processor and a memory storing instructions thereon which, when executed by the processor, cause the processor to: select symbols from reel strips stored in the memory for display in corresponding columns by determining stopping positions for the reel strips; cause display of the selected symbols in the columns on a display of a gaming device; determine that a trigger condition stored in the memory is satisfied based on the selected symbols; and in response to determining that the trigger condition is satisfied: replace one or more of the selected symbols in a group of symbol positions with an animation effect, the animation effect including display of a spin and stop sequence of credit values in the group of symbol positions; select a subset of the credit values; and cause display of the subset of credit values in the group of symbol positions.

The invention discloses a data transmission optimization method and system in hybrid deployment of a real-time system and a non-real-time system based on Jailhouse, belongs to the technical field of data transmission, and solves the problems of low data transmission efficiency, high copy overhead, lack of universality of interfaces and the like in an existing system. Comprising the steps that a hybrid deployment platform including a real-time system and a non-real-time system is built on a multi-core processor platform, and the hybrid deployment platform runs in an isolation environment of a Jailhouse partition manager; building an abstract transmission interface layer as a unified channel for accessing a shared memory by a real-time system and a non-real-time system; establishing a plurality of shared memory channels in the abstract transmission interface layer and scheduling according to the priority of tasks; establishing a data transmission path, and compressing a memory copy operation into one time by adopting a memory mapping multiplexing technology and a DMA (Direct Memory Access) collaboration mechanism; and a cache consistency maintenance technology is adopted, so that the data consistency is ensured, and the optimization of data transmission is completed. The method is suitable for application scenes such as industrial automation, intelligent connected automobiles and edge calculation.

The invention discloses an underwater acoustic processing CPU-GPU dynamic load balancing method based on a task flow model, and belongs to the technical field of underwater acoustic processing. The method comprises the following steps: deconstructing an underwater acoustic processing application into a task flow model represented by a directed acyclic graph; establishing a feature portrait including calculation complexity, parallelism and data throughput for each task node, and constructing a cost prediction model; the CPU / GPU utilization rate and the data transmission performance are monitored in real time; a processor is distributed to each task node by using a dynamic programming algorithm in combination with a cost prediction model and a real-time system state with the goal of minimizing the total task flow completion time; and dynamically scheduling tasks through a central scheduler according to a decision result, and periodically updating a strategy. According to the method, the defects that static task division lacks adaptability and neglects task dependence and communication overhead are overcome, dynamic and efficient utilization of CPU and GPU resources is achieved, and the efficiency and real-time performance of underwater sound processing are remarkably improved.

Techniques are described for onboarding a plurality of devices using a network management system (NMS). The NMS has memory and one or more processors coupled to the memory, the one or more processors configured to obtain onboarding information of a first device of a plurality of devices; assign, based on obtaining onboarding information of the first device, the first device to a group of devices to be managed by the network management system; and based on assigning the first device to the group of devices to be managed by the NMS, automatically assign a second device of the plurality of devices to the group of devices to be managed by the network management system.