19975 results about "MicroBlaze" patented technology

A computing system may include non-transitory computer-readable media storing instructions that when executed by the one or more computer processors, causes the computing system to perform operations comprising: causing presentation of a graphical user interface, the graphical user interface being associated with patient health data, wherein the graphical user interface is configured to: display one or more user interface elements, receive information identifying a logging action and at least one classification associated with the logging action, generate, by the processor, one or more models based on the received information, based on the generated one or more models, automatically associate the one or more user interface elements with one or more logging actions and update the graphical user interface with at least a portion of the one or more user interface elements.

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for multi-agent AI collaboration. The system provides a universal multi-modal key-value subsystem for sharing partial computations, implements hybrid placement strategies for dynamic memory management, and incorporates quantum-resistant secure enclaves. The architecture integrates hardware acceleration through GPU-FPGA hybrid caching and neuromorphic processors, applies adaptive energy and thermal management across hardware generations, and implements autonomous flash resource orchestration with multi-dimensional wear management. The system orchestrates tensor workflows using hierarchical scheduling, enables cross-agent collaboration with privacy preservation, and supports continuous learning without catastrophic forgetting. This integration delivers unprecedented computational efficiency and security in high-dimensional decision-making environments while supporting incremental adoption through modular interfaces.

A server computer system includes a communications module; at least one processor coupled to the communications module; and a memory coupled to the at least one processor, the memory storing processor-executable instructions which, when executed by the at least one processor, configure the at least one processor to receive, via the communications module, an indication that a cheque clearing process has been initiated for a cheque; obtain an account number and a routing number for the cheque; perform a lookup to identify a payor of the cheque; and send, via the communications module and to a client device associated with the payor of the cheque, a real-time update indicating that the cheque has been submitted for collection.

The invention relates to the technical field of firmware protection, in particular to a firmware protection method and system based on a security coprocessor. The method comprises the following steps: acquiring characteristic data of the coprocessor; extracting hardware entropy source data according to the coprocessor feature data; generating a hardware trust root key based on the hardware entropy source data; performing partition processing on the firmware based on the hardware trust root key to obtain firmware partition data; constructing hierarchical verification structure data according to the firmware partition data; implementing firmware starting security verification based on the hierarchical verification structure data to obtain integrity verification data; establishing a secure communication channel between the processors according to the integrity verification data; executing a bidirectional authentication process based on the secure communication channel, and generating session key data; a firmware runtime environment is monitored based on the session key data. According to the method, the hardware entropy source is extracted by measuring the physical characteristics of the coprocessor, and an unforgeable hardware trust root is established, so that the security is improved fundamentally.

The invention relates to the technical field of low-power-consumption AI processors, and discloses a load balancing method of a low-power-consumption AI processor, a chip and a storage medium, the method comprises the following steps: performing cache resource division on a plurality of neural mimicry cores in the low-power-consumption AI processor to obtain a double-layer cache structure; performing characteristic analysis on the target calculation task, and constructing a calculation task directed acyclic graph and a dependency intensity matrix; performing task segmentation to obtain a subtask division scheme; creating a task-core mapping table; organizing the neural mimicry core into a plurality of concentric ring layers based on the task-core mapping table to obtain a multi-layer ring cooperative computing network; and calculating a plurality of performance indexes of each neural mimicry core based on the multilayer annular cooperative computing network, and performing dynamic load optimization to obtain a dynamic load optimization strategy. According to the invention, the load balancing of the low-power AI processor is realized, and the calculation efficiency and the energy utilization rate are improved.

The invention discloses a low-power-consumption single-emission out-of-order execution RISC-V processor, which comprises seven stages of pipeline architecture, namely an instruction fetch unit, an instruction buffer unit, a decoding unit, an emission unit for single instruction emission, a physical register file, an execution unit for parallel out-of-order calculation and a retirement unit in sequence, and the instruction fetch unit is used as the front end of the RISC-V processor; a five-level pipeline architecture formed by the decoding unit, the transmitting unit, the physical register file, the execution unit and the retirement unit is used as the rear end of the RISC-V processor; through the technical scheme, the invention provides a micro-architecture which is more balanced in performance and power consumption, so that the applicability of a processor core in a scene with high computing requirements and sensitive power consumption is improved.

The invention discloses a matrix calculation adaptive optimization method and system based on an ARM architecture. The method comprises the following steps: preprocessing to-be-processed matrix data; performing local activeness calculation and hot spot region identification on the preprocessed matrix data, and determining long-tail distribution characteristics of the matrix; calculating the optimal block size range of the matrix based on the long tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the processor information, and generating an asymmetric block scheme; based on an asymmetric partitioning scheme, establishing a mapping relation between matrix features and optimal partitioning parameters; calculating the calculation density and the memory access mode of each block based on the asymmetric block scheme and the mapping relation, and generating a task scheduling scheme; based on the task scheduling scheme, matrix calculation is executed on the processor, and a final calculation result is output. According to the method, self-adaptive blocking and heterogeneous core scheduling are realized by identifying the long tail distribution characteristics of the matrix, and the performance and energy efficiency of matrix calculation on ARM are improved.

The embodiment of the invention provides an instruction processing method and a processor, and the method comprises the steps: obtaining a to-be-executed instruction, and determining a conflict type of the to-be-executed instruction; distributing a physical register for the to-be-executed instruction based on the conflict type; determining a dependency conflict condition and a resource conflict condition of the to-be-executed instruction, and determining an execution sequence of the to-be-executed instruction based on the dependency conflict condition and the resource conflict condition; determining a target execution unit based on the execution sequence, and sending the instruction to be executed to the target execution unit; and controlling the target execution unit to execute the to-be-executed instruction, and writing the to-be-executed instruction into the physical register when the to-be-executed instruction is executed, so that efficient out-of-order execution is realized through refined conflict detection, resource allocation and instruction scheduling, and the performance of the RISC-V processor can be remarkably improved. And the adaptability to complex applications is enhanced.

The invention discloses a power supply real-time compensation technology and application based on digital signal processing, and relates to the technical field of power electronics, and the power supply real-time compensation technology comprises a split-phase parallel processing architecture: a three-phase independently configured DSP core, each core integration comprises a real-time harmonic detection module, a dynamic sliding window FFT-RT algorithm is adopted, and the window length is adjustable in a set range; the bandwidth of the self-adaptive variable parameter filter can be dynamically adjusted in a set range; the FPGA coprocessor is specially used for PWM generation; an input stage of the harmonic prediction and decomposition module is synchronously acquired by a multi-source sensor; the processing layer comprises an improved VMD decomposition unit and a variational mode decomposition order; the edge prediction network is used for deploying a lightweight LSTM model, embedding a DSP core and predicting a harmonic spectrum in a future short period; and the multi-target dynamic optimization layer is used for setting a dynamic weight distributor and performing real-time adjustment according to the load sudden change rate. According to the invention, through split-phase parallel architecture, harmonic prediction and dynamic optimization, the response speed, multi-target cooperation and reliability improvement in the field of power supply real-time compensation are realized.

The invention relates to a dynamic adjustable multi-core cooperation mechanism and power consumption optimization method and system based on an RISC-V architecture. The method comprises the following steps: 1) initializing a dynamic adjustable multi-core cooperation system; comprising the steps that a hardware module is initialized, and the hardware module comprises a high-performance core P-core, a low-power-consumption core E-core, a hardware scheduling unit HSU and a power management unit PMU; loading a task queue, and marking task characteristics; 2) core state monitoring; comprising the following steps: an HSU monitors a core state; the power management unit PMU monitors voltage and frequency; 3) dynamic task scheduling; comprising the steps that task characteristics are allocated to a high-performance core P-core or a low-power-consumption core E-core; the idle core enters a low-power-consumption mode; and 4) self-adaptive energy saving is realized, and task migration is carried out. And through a dynamic task scheduling and energy-saving optimization algorithm, the flexibility and efficiency of the RISC-V multi-core processor are remarkably improved.

The invention relates to the technical field of process management, and discloses a lightweight process management method, which comprises the following steps of: defining a business process and analyzing the business process through a process engine; a graphical process design interface is provided, and a user can dynamically configure business process nodes through dragging and clicking operations; the business process is disassembled into a plurality of task nodes, and each task node is packaged into an independent function module through modularization design; the task nodes are combined according to needs and executed in parallel on different processors, and efficient execution of the task nodes is ensured; the execution state of the business process is monitored in real time, and potential problems are found and processed in time through log recording and an exception processing mechanism. According to the technical scheme of supporting dynamic adjustment of the task nodes and optimizing parameters based on the historical abnormal mode, execution parameters of the task nodes are dynamically corrected, association logic between the nodes is adjusted in real time, and the effects that process management is flexible and adapts to complex service scenes, and operation stability is improved are achieved.

A system is provided which includes a plurality of users, each having a mobile Web3 node associated therewith, wherein each mobile Web3 node is equipped with a tangible, non-transient memory device having a set of software instructions recorded. The software instructions, when executed by at least one compute processor, perform the steps of establishing a hardware root of trust, establishing a biometric binding which is unique among the mobile Web3 nodes, and creating an AI with a user interface. The user interface receives input from a user and uses the input to generate privacy preserved zero-ID transactions, and to create a private chain network on the mobile Web3 node to establish and secure a P2P control channel for all communication with at least some of the plurality of users.

In one embodiment, a computer-implemented method executed using one or more processors of an incident management system comprises receiving a notification of an incident associated with a computer system, and in response to receiving the notification: extracting an error message from the notification; reading a set of computer program code changes that have been implemented in the computer system; matching the error message to the set of computer program code changes and outputting a set of one or more candidate code changes that may correspond to the error message; based on the set of candidate code changes, generating an automatic remediation for the incident; and using the one or more processors of the incident management system, executing the automatic remediation on the computer system.

According to the instruction processing system, method and device provided by the invention, the instructions can be efficiently and smoothly distributed and run through the at least one processing module of the processor, and different instruction distribution logics are adopted based on different types of business processing instructions through two-stage instruction distribution, so that the service processing efficiency is improved. The business processing instructions are stored in the target storage area and then scheduled to the instruction execution module, so that quick distribution and hardware support of different types of business processing instructions are realized, the instruction distribution efficiency is greatly improved, complex calculation tasks can be flexibly and efficiently processed, instruction scheduling can be performed according to the priorities of the business processing instructions, and the service processing efficiency is improved. The key business operation is ensured to be responded and processed in time, and the overall performance and the operation efficiency of the database processor are effectively improved. The technical effect of flexibly and efficiently processing the database acceleration task is achieved.

A gaming machine, system, method, and program product for controlling such are provided. A group of gaming machines in a system is operated under control of at least one electronic processor to perform a method. The method includes receiving a player game activation input at a selected gaming machine and obtaining a game result in response. The method determines if the game result is to be awarded a designated jackpot prize, and if not, presents the game result on a display system of the selected gaming machine, and if so, sends a message to a group controller for the group of gaming machines. Under control of the group controller, a set of eligible gaming machines in the group of gaming machines presents an initial display sequence of a jackpot game presentation in unison. Then, the selected machine is identified and displays a final sequence of the jackpot game presentation.

The invention discloses a test case determination method and device, a computer readable storage medium and a processor. The method comprises the following steps: identifying a source code of software by utilizing a pre-trained large model to obtain a plurality of functional modules in the software and a dependency relationship among the plurality of functional modules; in response to updating of the source code of the software, determining a code updating part in the source code; determining a test case matched with the code updating part from a test case library of the software based on the code updating part and a dependency relationship among the plurality of functional modules, the test case being used for testing the code updating part; based on a test result of the test case, adjusting a selection strategy of the test case; and re-determining the test case for testing the code updating part based on the adjusted selection strategy of the test case. The technical problem that a traditional regression test strategy is low in test efficiency is solved.

Provided is a process, including: accessing, with a processor of an embedded computing device, immutable executable code stored in read-only memory of the embedded computing device; executing, with the processor of the embedded computing device, instructions of the immutable executable code that retrieve, from the read-only memory, a network-layer address of a tamper-evident, immutable data repository and an application-layer address of firmware of the embedded computing device stored in the tamper-evident, immutable data repository; executing, with the processor of the embedded computing device, instructions of the immutable executable code that, using the network-layer address and the application-layer address, download the firmware of the embedded computing device from the tamper-evident, immutable data repository; and executing, with the processor of the embedded computing device, instructions of the immutable executable code that store the downloaded firmware in re-writeable memory of the embedded computing device.

The invention discloses a method and a device for realizing task splitting based on a multi-core processor and a related product. A device may be included as a processing device in a combined processing device, which may further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete computing operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is connected with the computing device and the processing device and used for storing data of the computing device and the processing device. The scheme disclosed by the invention provides a method for scheduling group matrix multiplication class operation task splitting on the multi-core processor, which can effectively reduce data memory access and improve processing efficiency.

The invention relates to the technical field of data processing, in particular to an industrial environment data acquisition device and method, and the device comprises a sensing layer, an edge calculation layer, a cloud platform layer, and an application layer. Compared with a traditional scheme in which a single sensor is adopted to work independently, software synchronization is relied on, and signal conditioning parameters are fixed, the technical scheme of the invention realizes significant breakthrough through collaborative design of a multi-mode sensor array and an intelligent signal conditioning system, microsecond-level clock synchronization is realized by adopting a hardware-level PTP protocol, and the signal conditioning precision is improved. The program control amplifier is combined with the self-adaptive anti-aliasing filter, so that the conditioning circuit can be self-adaptive to the working condition change of equipment; meanwhile, nanosecond-level real-time processing of signals is achieved through an FPGA + ARM heterogeneous processor architecture, abnormal high-speed sampling is dynamically triggered in cooperation with an ARM, compared with a traditional scheme, the real-time performance is improved by three orders of magnitude, meanwhile, invalid data transmission is reduced by 80%, and a high-timeliness and low-redundancy intelligent monitoring solution is provided for early failure early warning of industrial equipment.

The invention relates to the technical field of path planning scheme design based on deep reinforcement learning, in particular to a path planning method and system based on deep reinforcement learning and electronic equipment. According to the method, a reward function is designed by comprehensively considering path length, smoothness, feasibility and multi-objective optimization weight through a deep reinforcement learning model, the model is trained by using experience playback and exploring and utilizing a balance strategy, and the generated path is used for real-time planning after being subjected to smoothness and feasibility correction. The system comprises an environment perception module, an action definition module, a reward function design module, a model construction and training module, a path optimization module, a plan updating module and the like. The electronic device covers a processor, a memory, and input and output modules to implement real-time path planning. According to the method, the quality and efficiency of path planning can be improved, the method adapts to a complex dynamic environment, potential risks caused by frequent turning or sudden change are effectively avoided, the practicability and safety of the path are improved, and the method has a wide application prospect.

Method and apparatus for 5GS assisted adaptive AI or ML operation are disclosed. In one embodiment, an SMF comprises a processor; and a transceiver coupled to the processor, wherein the processor is configured to: receive, via the transceiver, app assistant information from a NG-RAN node, wherein the app assistant information includes at least one of predicted UL data rate of UE and predicted DL data rate of UE; and transmit, via the transceiver, the app assistant information to an AF.

The invention provides an optimization method for improving parallelism and performance of hardware executing RISC-V vector instructions, which comprises the following steps: S1, an instruction fetching and decoding stage step: the step comprises an instruction fetching link and a decoding link, and the instruction fetching link reads instructions from a memory according to a program sequence and stores the instructions into an instruction queue; the decoding link comprises the steps of analyzing an instruction, identifying whether the instruction is a vector mask instruction or a vector length control instruction, and if the instruction needs an old value of a destination register, marking that the instruction needs to carry an old value dependency identifier, belonging to the technical field of optimization methods. According to the method, the instruction is transmitted without waiting for the old value of the target vector register to be ready, the instruction can be transmitted in advance after a certain condition is met, and the correct old value is obtained, so that the aim of improving the parallelism and the performance of hardware for executing the RISC-V vector instruction is fulfilled.

Disclosed in the present invention are a GPU feature mining and analysis method and system based on computer microarchitecture independence. The method comprises: building a target instrumentation library, analyzing a calling sequence of a target application program, and extracting a plurality of levels of performance features, wherein the performance features are high-level features of a program and are independent of a microarchitecture of a processor; analyzing a correlation between the performance features and execution performance of the target application program; and outputting an analysis result according to the obtained correlation, wherein the analysis result reflects a performance bottleneck of the target application program and a corresponding optimization suggestion. The present invention can help developers to adjust and optimize application programs, so as to fully use computing capabilities of GPUs.

An electronic gaming system including a memory and a processor is described. The processor is configured to receive a first input from a first electronic gaming device associated with initiation of a first play and receive a second input from a second electronic gaming device associated with initiation of a second play. The processor is also configured to cause a first game outcome for the first play to be determined and cause a second game outcome for the second play to be determined. The processor is also configured to cause the first output amount to be provided to the first player account and, based upon the first output amount associated with a first output amount ID being provided to the first player account, cause a replacement game outcome to be determined as a replacement for the second game outcome.

Implementations relate to a method implemented by one or more processors, the method including: receiving an input prompt for a large language model (LLM); generating first LLM output that is usable to generate a set of user interface (UI) each associated with a corresponding sub-prompt of the input prompt; causing, based on the first LLM output, the set of UI elements to be rendered at a user device; receiving further user input based on user interactions with one or more of the UI elements of the set of UI elements; and in response to determining that one or more termination conditions are satisfied: generating a final response to the input prompt based on generating second LLM output that is usable to generate the final response; and causing the final response to be rendered at the user device.

The invention discloses a hardware fault real-time detection method and system based on cooperation of a CPU (Central Processing Unit) and a BMC (Baseboard Management Controller), and the method comprises the following steps: respectively collecting high-frequency state data and tendency indexes by establishing a communication mechanism between the CPU and the BMC; the processor uses a CUSUM algorithm to carry out abrupt change analysis on the periodically collected operation state to generate an abrupt change event; and the management controller uses an EWMA algorithm to model the trend data, and extracts abnormal changes. And the system performs fusion analysis on the mutation event and the trend anomaly to form a fusion anomaly vector. The risk assessment module calculates a risk score based on a preset rule, determines a fault level, positions a target component, and outputs a processing strategy. And triggering a response action according to the strategy and recording an execution state. And the fusion data and the response record are input into the adaptive module together for dynamically adjusting CUSUM and EWMA parameters, so that adaptive updating of the algorithm is realized, and finally a fault detection signal is generated.

The invention provides a server voltage monitoring system and method, electronic equipment and a storage medium, and relates to the technical field of computers, the system comprises a complex programmable logic device CPLD, and an initial timing module, a voltage acquisition module, an abnormal data storage module, a CPU processor and a baseboard management controller BMC module which are respectively in communication connection with the CPLD. The initial timing module activates the monitoring function of the CPLD through a startup signal; the voltage acquisition module acquires voltage data under the control of the CPLD so as to read the voltage data of the server mainboard; the CPLD obtains voltage data, compares the voltage data with a reference voltage range of the abnormal data storage module, triggers an interrupt signal after identifying abnormal fluctuation voltage, and feeds back the interrupt signal to the CPU and the BMC, so that the CPU and the BMC quickly output an alarm. The system covers full-cycle monitoring from startup to BMC startup, supports efficient acquisition, dynamic detection and low-delay response of multi-path voltage, relieves the voltage pressure of a BMC monitoring mainboard, and provides reliable guarantee for power supply safety of a server.

Systems, apparatus, articles of manufacture, and methods are disclosed to utilize large language artificial intelligence models to convert computer code. An example apparatus includes instructions and processor circuitry to execute the instructions to at least: train a large language model based on a computer instructions repository that includes code of a first type; utilize the large language model to convert an input set of instructions of the first type into output code of a second type; cause execution of the output code; determine if the execution is successful; and when the execution is not successful, utilize the output code for fine-tuning training of the large language model with incorrect data.

The invention discloses a processor, a chip product, computer equipment and a tensor processing method, and relates to the technical field of processors. A first tensor having a plurality of elements arranged according to a first arrangement order is stored in the first storage unit; the tensor storage engine is used for reading the plurality of elements from the first storage unit to the second storage unit according to a second arrangement sequence to obtain a rearranged tensor; the tensor calculation engine is used for executing logical operation on the rearranged tensor to obtain an operation result; the format conversion unit is used for converting the data format of each element in the operation result into a target data format to obtain an operation result after format conversion, and storing the operation result after format conversion into a third storage unit, the operation result after format conversion comprises the operation results of the multiple elements, and the third storage unit is used for storing the operation results after format conversion. A third arrangement sequence of the operation results of the plurality of elements in the third storage unit is the same as the first arrangement sequence. The development cost of the processor can be reduced.