16189 results about "MicroBlaze" patented technology

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for multi-agent AI collaboration. The system provides a universal multi-modal key-value subsystem for sharing partial computations, implements hybrid placement strategies for dynamic memory management, and incorporates quantum-resistant secure enclaves. The architecture integrates hardware acceleration through GPU-FPGA hybrid caching and neuromorphic processors, applies adaptive energy and thermal management across hardware generations, and implements autonomous flash resource orchestration with multi-dimensional wear management. The system orchestrates tensor workflows using hierarchical scheduling, enables cross-agent collaboration with privacy preservation, and supports continuous learning without catastrophic forgetting. This integration delivers unprecedented computational efficiency and security in high-dimensional decision-making environments while supporting incremental adoption through modular interfaces.

The invention relates to the technical field of firmware protection, in particular to a firmware protection method and system based on a security coprocessor. The method comprises the following steps: acquiring characteristic data of the coprocessor; extracting hardware entropy source data according to the coprocessor feature data; generating a hardware trust root key based on the hardware entropy source data; performing partition processing on the firmware based on the hardware trust root key to obtain firmware partition data; constructing hierarchical verification structure data according to the firmware partition data; implementing firmware starting security verification based on the hierarchical verification structure data to obtain integrity verification data; establishing a secure communication channel between the processors according to the integrity verification data; executing a bidirectional authentication process based on the secure communication channel, and generating session key data; a firmware runtime environment is monitored based on the session key data. According to the method, the hardware entropy source is extracted by measuring the physical characteristics of the coprocessor, and an unforgeable hardware trust root is established, so that the security is improved fundamentally.

The invention discloses a matrix calculation adaptive optimization method and system based on an ARM architecture. The method comprises the following steps: preprocessing to-be-processed matrix data; performing local activeness calculation and hot spot region identification on the preprocessed matrix data, and determining long-tail distribution characteristics of the matrix; calculating the optimal block size range of the matrix based on the long tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the processor information, and generating an asymmetric block scheme; based on an asymmetric partitioning scheme, establishing a mapping relation between matrix features and optimal partitioning parameters; calculating the calculation density and the memory access mode of each block based on the asymmetric block scheme and the mapping relation, and generating a task scheduling scheme; based on the task scheduling scheme, matrix calculation is executed on the processor, and a final calculation result is output. According to the method, self-adaptive blocking and heterogeneous core scheduling are realized by identifying the long tail distribution characteristics of the matrix, and the performance and energy efficiency of matrix calculation on ARM are improved.

The invention discloses a power supply real-time compensation technology and application based on digital signal processing, and relates to the technical field of power electronics, and the power supply real-time compensation technology comprises a split-phase parallel processing architecture: a three-phase independently configured DSP core, each core integration comprises a real-time harmonic detection module, a dynamic sliding window FFT-RT algorithm is adopted, and the window length is adjustable in a set range; the bandwidth of the self-adaptive variable parameter filter can be dynamically adjusted in a set range; the FPGA coprocessor is specially used for PWM generation; an input stage of the harmonic prediction and decomposition module is synchronously acquired by a multi-source sensor; the processing layer comprises an improved VMD decomposition unit and a variational mode decomposition order; the edge prediction network is used for deploying a lightweight LSTM model, embedding a DSP core and predicting a harmonic spectrum in a future short period; and the multi-target dynamic optimization layer is used for setting a dynamic weight distributor and performing real-time adjustment according to the load sudden change rate. According to the invention, through split-phase parallel architecture, harmonic prediction and dynamic optimization, the response speed, multi-target cooperation and reliability improvement in the field of power supply real-time compensation are realized.

The invention relates to a dynamic adjustable multi-core cooperation mechanism and power consumption optimization method and system based on an RISC-V architecture. The method comprises the following steps: 1) initializing a dynamic adjustable multi-core cooperation system; comprising the steps that a hardware module is initialized, and the hardware module comprises a high-performance core P-core, a low-power-consumption core E-core, a hardware scheduling unit HSU and a power management unit PMU; loading a task queue, and marking task characteristics; 2) core state monitoring; comprising the following steps: an HSU monitors a core state; the power management unit PMU monitors voltage and frequency; 3) dynamic task scheduling; comprising the steps that task characteristics are allocated to a high-performance core P-core or a low-power-consumption core E-core; the idle core enters a low-power-consumption mode; and 4) self-adaptive energy saving is realized, and task migration is carried out. And through a dynamic task scheduling and energy-saving optimization algorithm, the flexibility and efficiency of the RISC-V multi-core processor are remarkably improved.

In one embodiment, a computer-implemented method executed using one or more processors of an incident management system comprises receiving a notification of an incident associated with a computer system, and in response to receiving the notification: extracting an error message from the notification; reading a set of computer program code changes that have been implemented in the computer system; matching the error message to the set of computer program code changes and outputting a set of one or more candidate code changes that may correspond to the error message; based on the set of candidate code changes, generating an automatic remediation for the incident; and using the one or more processors of the incident management system, executing the automatic remediation on the computer system.

According to the instruction processing system, method and device provided by the invention, the instructions can be efficiently and smoothly distributed and run through the at least one processing module of the processor, and different instruction distribution logics are adopted based on different types of business processing instructions through two-stage instruction distribution, so that the service processing efficiency is improved. The business processing instructions are stored in the target storage area and then scheduled to the instruction execution module, so that quick distribution and hardware support of different types of business processing instructions are realized, the instruction distribution efficiency is greatly improved, complex calculation tasks can be flexibly and efficiently processed, instruction scheduling can be performed according to the priorities of the business processing instructions, and the service processing efficiency is improved. The key business operation is ensured to be responded and processed in time, and the overall performance and the operation efficiency of the database processor are effectively improved. The technical effect of flexibly and efficiently processing the database acceleration task is achieved.

The invention discloses a test case determination method and device, a computer readable storage medium and a processor. The method comprises the following steps: identifying a source code of software by utilizing a pre-trained large model to obtain a plurality of functional modules in the software and a dependency relationship among the plurality of functional modules; in response to updating of the source code of the software, determining a code updating part in the source code; determining a test case matched with the code updating part from a test case library of the software based on the code updating part and a dependency relationship among the plurality of functional modules, the test case being used for testing the code updating part; based on a test result of the test case, adjusting a selection strategy of the test case; and re-determining the test case for testing the code updating part based on the adjusted selection strategy of the test case. The technical problem that a traditional regression test strategy is low in test efficiency is solved.

The invention relates to the technical field of data processing, in particular to an industrial environment data acquisition device and method, and the device comprises a sensing layer, an edge calculation layer, a cloud platform layer, and an application layer. Compared with a traditional scheme in which a single sensor is adopted to work independently, software synchronization is relied on, and signal conditioning parameters are fixed, the technical scheme of the invention realizes significant breakthrough through collaborative design of a multi-mode sensor array and an intelligent signal conditioning system, microsecond-level clock synchronization is realized by adopting a hardware-level PTP protocol, and the signal conditioning precision is improved. The program control amplifier is combined with the self-adaptive anti-aliasing filter, so that the conditioning circuit can be self-adaptive to the working condition change of equipment; meanwhile, nanosecond-level real-time processing of signals is achieved through an FPGA + ARM heterogeneous processor architecture, abnormal high-speed sampling is dynamically triggered in cooperation with an ARM, compared with a traditional scheme, the real-time performance is improved by three orders of magnitude, meanwhile, invalid data transmission is reduced by 80%, and a high-timeliness and low-redundancy intelligent monitoring solution is provided for early failure early warning of industrial equipment.

The invention relates to the technical field of path planning scheme design based on deep reinforcement learning, in particular to a path planning method and system based on deep reinforcement learning and electronic equipment. According to the method, a reward function is designed by comprehensively considering path length, smoothness, feasibility and multi-objective optimization weight through a deep reinforcement learning model, the model is trained by using experience playback and exploring and utilizing a balance strategy, and the generated path is used for real-time planning after being subjected to smoothness and feasibility correction. The system comprises an environment perception module, an action definition module, a reward function design module, a model construction and training module, a path optimization module, a plan updating module and the like. The electronic device covers a processor, a memory, and input and output modules to implement real-time path planning. According to the method, the quality and efficiency of path planning can be improved, the method adapts to a complex dynamic environment, potential risks caused by frequent turning or sudden change are effectively avoided, the practicability and safety of the path are improved, and the method has a wide application prospect.

Method and apparatus for 5GS assisted adaptive AI or ML operation are disclosed. In one embodiment, an SMF comprises a processor; and a transceiver coupled to the processor, wherein the processor is configured to: receive, via the transceiver, app assistant information from a NG-RAN node, wherein the app assistant information includes at least one of predicted UL data rate of UE and predicted DL data rate of UE; and transmit, via the transceiver, the app assistant information to an AF.

The invention provides an optimization method for improving parallelism and performance of hardware executing RISC-V vector instructions, which comprises the following steps: S1, an instruction fetching and decoding stage step: the step comprises an instruction fetching link and a decoding link, and the instruction fetching link reads instructions from a memory according to a program sequence and stores the instructions into an instruction queue; the decoding link comprises the steps of analyzing an instruction, identifying whether the instruction is a vector mask instruction or a vector length control instruction, and if the instruction needs an old value of a destination register, marking that the instruction needs to carry an old value dependency identifier, belonging to the technical field of optimization methods. According to the method, the instruction is transmitted without waiting for the old value of the target vector register to be ready, the instruction can be transmitted in advance after a certain condition is met, and the correct old value is obtained, so that the aim of improving the parallelism and the performance of hardware for executing the RISC-V vector instruction is fulfilled.

An electronic gaming system including a memory and a processor is described. The processor is configured to receive a first input from a first electronic gaming device associated with initiation of a first play and receive a second input from a second electronic gaming device associated with initiation of a second play. The processor is also configured to cause a first game outcome for the first play to be determined and cause a second game outcome for the second play to be determined. The processor is also configured to cause the first output amount to be provided to the first player account and, based upon the first output amount associated with a first output amount ID being provided to the first player account, cause a replacement game outcome to be determined as a replacement for the second game outcome.

Implementations relate to a method implemented by one or more processors, the method including: receiving an input prompt for a large language model (LLM); generating first LLM output that is usable to generate a set of user interface (UI) each associated with a corresponding sub-prompt of the input prompt; causing, based on the first LLM output, the set of UI elements to be rendered at a user device; receiving further user input based on user interactions with one or more of the UI elements of the set of UI elements; and in response to determining that one or more termination conditions are satisfied: generating a final response to the input prompt based on generating second LLM output that is usable to generate the final response; and causing the final response to be rendered at the user device.

The invention discloses a hardware fault real-time detection method and system based on cooperation of a CPU (Central Processing Unit) and a BMC (Baseboard Management Controller), and the method comprises the following steps: respectively collecting high-frequency state data and tendency indexes by establishing a communication mechanism between the CPU and the BMC; the processor uses a CUSUM algorithm to carry out abrupt change analysis on the periodically collected operation state to generate an abrupt change event; and the management controller uses an EWMA algorithm to model the trend data, and extracts abnormal changes. And the system performs fusion analysis on the mutation event and the trend anomaly to form a fusion anomaly vector. The risk assessment module calculates a risk score based on a preset rule, determines a fault level, positions a target component, and outputs a processing strategy. And triggering a response action according to the strategy and recording an execution state. And the fusion data and the response record are input into the adaptive module together for dynamically adjusting CUSUM and EWMA parameters, so that adaptive updating of the algorithm is realized, and finally a fault detection signal is generated.

The invention provides a server voltage monitoring system and method, electronic equipment and a storage medium, and relates to the technical field of computers, the system comprises a complex programmable logic device CPLD, and an initial timing module, a voltage acquisition module, an abnormal data storage module, a CPU processor and a baseboard management controller BMC module which are respectively in communication connection with the CPLD. The initial timing module activates the monitoring function of the CPLD through a startup signal; the voltage acquisition module acquires voltage data under the control of the CPLD so as to read the voltage data of the server mainboard; the CPLD obtains voltage data, compares the voltage data with a reference voltage range of the abnormal data storage module, triggers an interrupt signal after identifying abnormal fluctuation voltage, and feeds back the interrupt signal to the CPU and the BMC, so that the CPU and the BMC quickly output an alarm. The system covers full-cycle monitoring from startup to BMC startup, supports efficient acquisition, dynamic detection and low-delay response of multi-path voltage, relieves the voltage pressure of a BMC monitoring mainboard, and provides reliable guarantee for power supply safety of a server.

The invention discloses a processor, a chip product, computer equipment and a tensor processing method, and relates to the technical field of processors. A first tensor having a plurality of elements arranged according to a first arrangement order is stored in the first storage unit; the tensor storage engine is used for reading the plurality of elements from the first storage unit to the second storage unit according to a second arrangement sequence to obtain a rearranged tensor; the tensor calculation engine is used for executing logical operation on the rearranged tensor to obtain an operation result; the format conversion unit is used for converting the data format of each element in the operation result into a target data format to obtain an operation result after format conversion, and storing the operation result after format conversion into a third storage unit, the operation result after format conversion comprises the operation results of the multiple elements, and the third storage unit is used for storing the operation results after format conversion. A third arrangement sequence of the operation results of the plurality of elements in the third storage unit is the same as the first arrangement sequence. The development cost of the processor can be reduced.

The invention provides a multi-task dynamic resource sharing method and system for a universal graphics processor, and belongs to the technical field of computing graphics process.The method comprises the steps that a plurality of computing tasks are distributed to processing subunits in a cooperative processing unit respectively; obtaining the load state of the computing resource in each processing subunit, and determining the available computing resource capacity of each processing subunit according to the load state; according to the available computing resource capacity, marking the processing subunit of which the current execution thread beam instruction queue length exceeds the own available computing resource capacity as a source processing subunit, and marking the processing subunit with idle computing resources as a target processing subunit; and migrating part or all of the to-be-executed thread beam instructions in the to-be-executed thread beam instruction queue of the source processing subunit to the idle computing resources of the target processing subunit for execution. According to the method and the device, the cross-processing subunit dynamic migration is carried out on the thread beam instruction based on real-time load monitoring, so that the throughput rate and the computing resource utilization rate are improved.

A computer implemented system is described in various embodiments herein, the system includes a processor, a memory coupled to the processor and storing processor-executable instructions that, when executed, configure the processor to: receive an initial video data object V comprising a plurality of image frame data objects I; receive a set of time-synchronized viseme parameters corresponding to target audio data object A′; and process the initial video data object V and the set of time-synchronized viseme parameters using a machine learning network to generate an output video data object V′, wherein initial mouth regions in the initial video data object V have been replaced with replacement mouth regions generated based on the set of time-synchronized viseme parameters.

An apparatus to facilitate lossless and lossy automatic hardware compression in graphics-to-graphics network links is disclosed. The apparatus includes compressor / decompressor circuitry (CDC) integrated with physical layer (PHY) intellectual property (IP) hardware circuitry for a graphics processor unit (GPU)-to-GPU communication link communicably coupling a first GPU to one or more other GPUs, the CDC to: receive a data message from the first GPU, wherein the data message is in an uncompressed format; determine that a compression process is to be applied to the data message; apply the compression process to the data message to generate a compressed data message; and cause a GPU link IP hardware circuitry that comprises the PHY IP hardware circuitry to transmit the compressed data message over the GPU-to-GPU communication link.

The invention discloses a control method for a cooling circulation system of a multi-core processor, and relates to the technical field of computer hardware heat dissipation, and the control method comprises the following steps: the multi-core processor is responsible for executing a calculation task; the sensor module monitors the temperature of each core; the cooling system control module is used for receiving data from the temperature sensor and the load monitoring module, calculating the cooling requirement of each core according to the data and commanding a cooling unit to adjust; the cooling unit is used for adjusting cooling equipment to reduce the temperature of the processor according to an instruction of the control unit; and the debugging interface is used for monitoring the state of the system and displaying the temperature, the load and the cooling resource distribution condition of each core. The method has the beneficial effects that the rotating speed of the fan, the liquid cooling flow and the working state of the heat pipe system can be accurately controlled by combining the accurate analysis of the load change and the temperature data, the heat dissipation efficiency of the processor is improved, and the energy waste is reduced.

In an approach to coordinating a conversational agent with a large language model for conversation repair, one or more computer processors receive a failure indicator from a first conversational agent. One or more computer processors retrieve a descriptive prompt associated with the first conversational agent. One or more computer processors transmit the descriptive prompt to a large language model. One or more computer processors transfer control of the failed conversation from the first conversational agent to the large language model. One or more computer processors determine the intent of the user associated with the failed conversation using the large language model. One or more computer processors determine whether the intent of the user associated with the failed conversation matches a capability of the first conversational agent. One or more computer processors transfer by one or more computer processors, the user back to the first conversational agent.

The invention relates to the technical field of microprocessors, and discloses a safety debugging method of an embedded microprocessor and the embedded microprocessor, the method comprises the following steps: implanting a random module in the microprocessor, constructing a resistance network array through random distribution of silicon substrate lattice defects to generate a disordered sequence, and if microprocessor data access is carried out, starting the random module; if physical intrusion is detected, a debugging session is established, three types of physical characteristics are synchronously generated to construct a composite key, a triple dynamic confusion layer is constructed in the microprocessor, the dynamic confusion layer and the composite key construct physical logic linkage protection, a probe access instruction logic address is called, if physical intrusion is detected, a probe triggers an invisible check point, and the probe accesses the invisible check point. The integrity of an execution environment is verified, if abnormal debugging is detected, a hardware defense mechanism is triggered, an access attack model is established, confusion parameters are trained and optimized, and a module interconnection mode is changed, so that the learning cycle of an attacker is broken, and the risk of attacking a processor in a machine learning mode is reduced.

A new transaction barrier synchronization primitive enables executing threads and asynchronous transactions to synchronize across parallel processors. The asynchronous transactions may include transactions resulting from, for example, hardware data movement units such as direct memory units, etc. A hardware synchronization circuit may provide for the synchronization primitive to be stored in a cache memory so that barrier operations may be accelerated by the circuit. A new wait mechanism reduces software overhead associated with waiting on a barrier.

The invention discloses a cache consistency system, method and device, an electronic device and a storage medium, and relates to the technical field of computers.A request buffer area is arranged between a master node and a slave node, the slave node can monitor the blocking condition of each memory access request in the request buffer area, and the cache consistency is improved. When the request blocking degree of any processor core reaches the preset blocking threshold value, the priority of the memory access request of the processor core is improved in the request buffer area, so that the situation that the slave node does not respond to the memory access request of a certain processor core in time is avoided, and the overall performance of a system is improved.

A computer platform for generating a video includes one or more memories to store instructions and one or more processors to execute the instructions to perform operations, the operations including: receiving a query from a user relating to a location; in response to receiving the query, generating conditioning parameters based at least in part on the query, wherein the conditioning parameters provide values for one or more conditions associated with a scene to be rendered at the location; generating, using a generative machine-learned model, the video, wherein the video depicts the scene at the location and with the values for the one or more conditions; and providing the video for presentation to the user.

A robotic emulation device includes a processor, memory and multimedia interfaces to capture a video signal from a target device, analyze it, and transmit manipulation control signals to the target device input by emulating a peripheral input device, wherein the manipulation control signals determine manipulation or selection of a target interface control associated with a first user interface encoded and transmitted in the video signal. Furthermore, the robotic emulation device may be connected via an embedded transceiver to at least one computer or computer tenant for relaying the captured video data for analysis, and based on the analysis, applying inferred manipulation semantics.

Embodiments of the present invention provide computer-implemented methods, computer program product, and computer systems. One or more processors analyze user prompts using one or more natural language understanding techniques. One or more processors then enrich the user prompts by integrating contextual data from user interaction history and adapt the enriched user prompts to align with characteristics of Large Language Models (LLMs) and Application Programming Interfaces (API) requirements of the LLMs.

Techniques are described herein for system for preserving memories and experiences through a Non-Fungible Token (NFT) engine. An example system includes one or more memories storing a set of computer-readable instructions including the NFT engine and one or more processors interfacing with the one or more memories. The one or more processors are configured to execute the set of computer-readable instructions to cause the system to: receive data of a user from a time period, and execute the NFT engine to: analyze the data to classify a memory experienced by the user during the time period based on a memory threshold, generate, for display to the user, an NFT based on the memory, and mint the NFT corresponding to the memory to a blockchain, wherein a portion of the data associated with the memory is linked to the NFT.

One aspect of the instant disclosure may provide a system and method for processing scatter-gather direct memory access (S-G DMA) instructions. During operation, the system may receive an S-G DMA instruction associated with a message and gather instruction context for the S-G DMA instruction. An S-G DMA processor may process the S-G DMA instruction based on the gathered instruction context and determine whether there exists a pending S-G DMA instruction associated with the message. In response to the presence of the pending S-G DMA instruction, the system stores the instruction context in a hot context cache at an address corresponding to the pending S-G DMA instruction. In response to the absence of the pending S-G DMA instruction, the system stores the instruction context in a cold context cache.