12744 results about "MicroBlaze" patented technology

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for multi-agent AI collaboration. The system provides a universal multi-modal key-value subsystem for sharing partial computations, implements hybrid placement strategies for dynamic memory management, and incorporates quantum-resistant secure enclaves. The architecture integrates hardware acceleration through GPU-FPGA hybrid caching and neuromorphic processors, applies adaptive energy and thermal management across hardware generations, and implements autonomous flash resource orchestration with multi-dimensional wear management. The system orchestrates tensor workflows using hierarchical scheduling, enables cross-agent collaboration with privacy preservation, and supports continuous learning without catastrophic forgetting. This integration delivers unprecedented computational efficiency and security in high-dimensional decision-making environments while supporting incremental adoption through modular interfaces.

The invention discloses a matrix calculation adaptive optimization method and system based on an ARM architecture. The method comprises the following steps: preprocessing to-be-processed matrix data; performing local activeness calculation and hot spot region identification on the preprocessed matrix data, and determining long-tail distribution characteristics of the matrix; calculating the optimal block size range of the matrix based on the long tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the processor information, and generating an asymmetric block scheme; based on an asymmetric partitioning scheme, establishing a mapping relation between matrix features and optimal partitioning parameters; calculating the calculation density and the memory access mode of each block based on the asymmetric block scheme and the mapping relation, and generating a task scheduling scheme; based on the task scheduling scheme, matrix calculation is executed on the processor, and a final calculation result is output. According to the method, self-adaptive blocking and heterogeneous core scheduling are realized by identifying the long tail distribution characteristics of the matrix, and the performance and energy efficiency of matrix calculation on ARM are improved.

The invention discloses a power supply real-time compensation technology and application based on digital signal processing, and relates to the technical field of power electronics, and the power supply real-time compensation technology comprises a split-phase parallel processing architecture: a three-phase independently configured DSP core, each core integration comprises a real-time harmonic detection module, a dynamic sliding window FFT-RT algorithm is adopted, and the window length is adjustable in a set range; the bandwidth of the self-adaptive variable parameter filter can be dynamically adjusted in a set range; the FPGA coprocessor is specially used for PWM generation; an input stage of the harmonic prediction and decomposition module is synchronously acquired by a multi-source sensor; the processing layer comprises an improved VMD decomposition unit and a variational mode decomposition order; the edge prediction network is used for deploying a lightweight LSTM model, embedding a DSP core and predicting a harmonic spectrum in a future short period; and the multi-target dynamic optimization layer is used for setting a dynamic weight distributor and performing real-time adjustment according to the load sudden change rate. According to the invention, through split-phase parallel architecture, harmonic prediction and dynamic optimization, the response speed, multi-target cooperation and reliability improvement in the field of power supply real-time compensation are realized.

In one embodiment, a computer-implemented method executed using one or more processors of an incident management system comprises receiving a notification of an incident associated with a computer system, and in response to receiving the notification: extracting an error message from the notification; reading a set of computer program code changes that have been implemented in the computer system; matching the error message to the set of computer program code changes and outputting a set of one or more candidate code changes that may correspond to the error message; based on the set of candidate code changes, generating an automatic remediation for the incident; and using the one or more processors of the incident management system, executing the automatic remediation on the computer system.

An electronic gaming system including a memory and a processor is described. The processor is configured to receive a first input from a first electronic gaming device associated with initiation of a first play and receive a second input from a second electronic gaming device associated with initiation of a second play. The processor is also configured to cause a first game outcome for the first play to be determined and cause a second game outcome for the second play to be determined. The processor is also configured to cause the first output amount to be provided to the first player account and, based upon the first output amount associated with a first output amount ID being provided to the first player account, cause a replacement game outcome to be determined as a replacement for the second game outcome.

The invention discloses a hardware fault real-time detection method and system based on cooperation of a CPU (Central Processing Unit) and a BMC (Baseboard Management Controller), and the method comprises the following steps: respectively collecting high-frequency state data and tendency indexes by establishing a communication mechanism between the CPU and the BMC; the processor uses a CUSUM algorithm to carry out abrupt change analysis on the periodically collected operation state to generate an abrupt change event; and the management controller uses an EWMA algorithm to model the trend data, and extracts abnormal changes. And the system performs fusion analysis on the mutation event and the trend anomaly to form a fusion anomaly vector. The risk assessment module calculates a risk score based on a preset rule, determines a fault level, positions a target component, and outputs a processing strategy. And triggering a response action according to the strategy and recording an execution state. And the fusion data and the response record are input into the adaptive module together for dynamically adjusting CUSUM and EWMA parameters, so that adaptive updating of the algorithm is realized, and finally a fault detection signal is generated.

The invention provides a multi-task dynamic resource sharing method and system for a universal graphics processor, and belongs to the technical field of computing graphics process.The method comprises the steps that a plurality of computing tasks are distributed to processing subunits in a cooperative processing unit respectively; obtaining the load state of the computing resource in each processing subunit, and determining the available computing resource capacity of each processing subunit according to the load state; according to the available computing resource capacity, marking the processing subunit of which the current execution thread beam instruction queue length exceeds the own available computing resource capacity as a source processing subunit, and marking the processing subunit with idle computing resources as a target processing subunit; and migrating part or all of the to-be-executed thread beam instructions in the to-be-executed thread beam instruction queue of the source processing subunit to the idle computing resources of the target processing subunit for execution. According to the method and the device, the cross-processing subunit dynamic migration is carried out on the thread beam instruction based on real-time load monitoring, so that the throughput rate and the computing resource utilization rate are improved.

An apparatus to facilitate lossless and lossy automatic hardware compression in graphics-to-graphics network links is disclosed. The apparatus includes compressor / decompressor circuitry (CDC) integrated with physical layer (PHY) intellectual property (IP) hardware circuitry for a graphics processor unit (GPU)-to-GPU communication link communicably coupling a first GPU to one or more other GPUs, the CDC to: receive a data message from the first GPU, wherein the data message is in an uncompressed format; determine that a compression process is to be applied to the data message; apply the compression process to the data message to generate a compressed data message; and cause a GPU link IP hardware circuitry that comprises the PHY IP hardware circuitry to transmit the compressed data message over the GPU-to-GPU communication link.

A new transaction barrier synchronization primitive enables executing threads and asynchronous transactions to synchronize across parallel processors. The asynchronous transactions may include transactions resulting from, for example, hardware data movement units such as direct memory units, etc. A hardware synchronization circuit may provide for the synchronization primitive to be stored in a cache memory so that barrier operations may be accelerated by the circuit. A new wait mechanism reduces software overhead associated with waiting on a barrier.

Embodiments of the present invention provide computer-implemented methods, computer program product, and computer systems. One or more processors analyze user prompts using one or more natural language understanding techniques. One or more processors then enrich the user prompts by integrating contextual data from user interaction history and adapt the enriched user prompts to align with characteristics of Large Language Models (LLMs) and Application Programming Interfaces (API) requirements of the LLMs.

One aspect of the instant disclosure may provide a system and method for processing scatter-gather direct memory access (S-G DMA) instructions. During operation, the system may receive an S-G DMA instruction associated with a message and gather instruction context for the S-G DMA instruction. An S-G DMA processor may process the S-G DMA instruction based on the gathered instruction context and determine whether there exists a pending S-G DMA instruction associated with the message. In response to the presence of the pending S-G DMA instruction, the system stores the instruction context in a hot context cache at an address corresponding to the pending S-G DMA instruction. In response to the absence of the pending S-G DMA instruction, the system stores the instruction context in a cold context cache.

Apparatuses, systems, and techniques to select optimizations to be performed by compilers. In at least one embodiment, a processor includes one or more circuits to perform a compiler to select one or more optimizations to one or more first versions of a program based, at least in part, on a result of performing said one or more optimizations on one or more second versions of said program.

One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster including a plurality of graphics cores and tensor processing circuitry. The tensor processing circuitry includes a local memory, a tensor accelerator coupled with the local memory, the tensor accelerator configured to perform a matrix multiply and accumulate operation, and a tensor data movement accelerator configured to asynchronously transfer tensor data between a global memory coupled to the memory interface and the local memory. The tensor data movement accelerator includes circuitry configured to translate the tensor data from a first tensor format to a second tensor format.

The present disclosure relates to systems and methods remote memory access between systems. In particular, some implementations relate to remote memory access using data processing units that can reduce loads on central processing units or other system components. Some implementations utilize scheduling algorithms to optimize memory transfers. Some implementations relate to data processing unit hardware that includes programmable logic, which can be configured for scheduling, data processing, and the like.

A cloud deployment automation system consisting of: a deployment automation device housed in a rack-mountable enclosure, the device comprising: a multi-core orchestration processor configured to execute deployment logic as compiled execution graphs; a storage module operatively coupled to the orchestration processor, the storage storing a set of deployment templates, real-time execution states, telemetry logs, and policy configurations; a secure credential management processing unit embedded in the device, configured to generate, store, and rotate cloud access tokens, API keys, and user-specific credentials, and to provide encrypted access to those credentials during deployment execution; an in-memory workflow execution engine executed by the orchestration processor, configured to analyze a user-defined deployment configuration that includes a declarative specification of infrastructure resources and compile that configuration into a directed acyclic graph (DAG) that represents the resource deployment order, dependency mapping, and rollback relationships, a cloud provider interface subsystem communicatively connected to multiple heterogeneous cloud platforms via appropriate API adapters, the subsystem enabling the orchestration processor to send provisioning requests and receive status events from the platforms; a customizable workflow compiler unit configured to convert graphical workflow definitions or domain-specific language (DSL) scripts into execution sequences that can be used by the workflow execution engine, where the workflow compiler unit supports conditional branching, asynchronous operations, and runtime variable resolution; and A policy enforcement control unit integrated into the deployment automation device, with the policy engine configured to apply organization-specific compliance rules, tagging conventions, security group configurations, and runtime resource limits to all deployment actions in a context-aware manner prior to execution.

The invention relates to the technical field of computer architecture and parallel computing, and discloses a parallel task scheduling algorithm for a heterogeneous multi-core processor, which comprises the steps of task modeling, resource mapping, dynamic load balancing, communication optimization, task scheduling decision and execution monitoring. Task allocation is adjusted in real time through dynamic load balancing, cross-core communication delay is reduced in combination with communication optimization, and an efficient task allocation sequence is generated by using an improved genetic algorithm. According to the method, the resource utilization rate and the task execution efficiency of the heterogeneous multi-core processor in a high-performance computing scene can be improved, meanwhile, the robustness and adaptability of an algorithm are enhanced, and the task allocation problem in a complex computing scene is effectively solved.

An automation testing system includes a processor and a memory storing historical data which at least comprising past test results including input parameters and testing outcomes for each test case included in the past test results. The processor is configured to identify input parameters for a first iteration of a first software application having first functionalities; execute an initial test on the first iteration to generate initial results; based on the input parameters and the initial results, collecting first historical data at least comprising first past test results for at least one second software application having second functionalities corresponding to the first functionalities; training a model employing AI or ML based on the initial results and the first historical data to generate a trained model; executing the trained model with the input parameters as input to generate a set of test cases for testing the first functionalities.

An end-to-end rendering system enforces policy-constrained, symbolic presentation of artificial-intelligence (AI) outputs prior to any pixel emission. An AI accelerator emits inference tokens as (token identifier, confidence, domain tag) tuples into an output FIFO. A graphics processor with a command processor and SIMD co-processor executes a policy engine that runs a deterministic finite automaton (DFA) stored in non-transitory memory. The DFA consumes the tuples and produces, before any frame-buffer writes, a permit / deny decision and a visibility mask that constrain presentation attributes. A glyph selector maps permitted tuples to entries in a constrained glyph dictionary specifying a glyph identifier, semantic class, and allowed substitutions. A provenance tagger computes a cryptographic hash over at least the glyph identifier, a DFA-state policy identifier, a session nonce, and a checksum of the tuples to create an evidence capsule bound to the glyph. A device-aware renderer, consulting a device profile registry and a rendering grammar, emits a renderable asset for the glyph only when permitted by the visibility mask and grammar. A justification ledger records, for each displayed glyph, the evidence capsule and a monotonic timestamp. Executed entirely within the graphics processor, the pipeline prevents unauthorized tokens from entering the display path, enables cryptographically verifiable traceability of visible content, and reduces bandwidth by representing outputs as glyph identifiers rather than text or raster imagery, while allowing runtime policy updates without modifying the underlying inference model.

An apparatus and method for generating an automated output as a function of an attribute datum and key datums. The apparatus includes at least a processor and a memory communicatively connected to the at least a processor. The memory instructs the processor to receive a first datum comprising a plurality of unstructured data, classify, using a classifier, the first datum based on an attribute datum, identify, using a key datum extractor, key datums as a function of the attribute datum, generate, using a validation model, an output as a function of the attribute datum and the key datums, and transmit the output to a downstream system.

Provided are system, method, and device for automatically enhancing future prediction using a reservoir transformer in a machine learning model. According to example embodiments, the system may include: a memory storage storing computer-executable instructions; and at least one processor communicatively coupled to the memory storage, wherein the at least one processor may be configured to execute the instructions to: obtain current input data representing a current state of a complex system; determine a plurality of readout data based on previous input data representing a previous state of the complex system using a plurality of reservoirs; combine the plurality of readout data to form an ensemble reservoir data; and determine predicted output data representing a predicted state of the complex system based on the ensemble reservoir data and the current input data using a transformer.

The invention provides a write-after-read conflict prediction method, device and equipment, which are applied to the technical field of data processing, and the method comprises the following steps: reading a to-be-transmitted loading instruction; the loading instruction is located in a loading queue of the out-of-order execution processor. Determining an index value of the loading instruction; the index value is used for quickly positioning a conflict record matched with the loading instruction in a historical conflict table of the out-of-order execution processor. The conflict record comprises a first storage instruction corresponding to the loading instruction. And when it is determined that the conflict record corresponding to the index value exists in the historical conflict table, setting the loading instruction to be in a suspended state. And after the execution of the first storage instruction is finished, executing the loading instruction. The problem that the execution efficiency of a processor is affected due to pipeline emptying and pause caused by write conflicts after reading can be solved.

A system for prioritization of group computing tasks is described. The system includes at least a processor and a memory communicatively connected to the at least a processor. The memory contains instructions configuring the at least a processor to detect a plurality of active nodes communicatively connected in a group computing environment and receive a plurality of computing tasks associated with the plurality of active nodes for execution in the group computing environment. The at least a processor is also configured to determine a computing demand associated with each of the plurality of computing tasks on the group computing environment and establish a priority for the plurality of computing tasks as a function of the computing demand associated with each of the plurality of computing tasks.

The invention discloses a network card data local preprocessing system fused with edge computing, and relates to the technical field of edge computing and artificial intelligence collaborative optimization. Comprising an edge computing unit, a hierarchical collaborative architecture, a model hot switching and generative fragmentation module, an intention recognition and adaptive scheduling module, a delay energy consumption optimization scheduling module, a CXL zero-copy sharing module, an edge computing unit integrated processor, an FPGA or ASIC and a neuromorphic computing unit. According to the method, an FPGA, an ASIC and a neuromorphic computing unit are integrated in an intelligent network card, microsecond-level dynamic connection reconfiguration and adaptive generative model fragmentation execution are realized through a reconfigurable Mesh interconnection matrix, an attention layer and a feed-forward layer of a Transform class model are fragmented and allocated to different computing units for parallel execution, and cross-card streamlined processing is realized in cooperation with a zero-copy shared memory. And the intention recognition module is deeply coupled with the model hot switching module, so that dynamic model switching and fragmentation strategy optimization based on service priorities and system loads are realized.

A system for real-time detection and mitigation of morphing malware in high-density edge networks, consisting of: a data acquisition unit configured to receive, normalize, and encode multimodal telemetry data streams originating from at least one of the following domains: network traffic, process behavior, system call sequences, binary instruction traces, and control flow graphs; the data acquisition unit is further configured to compute feature embeddings over sliding time windows and apply privacy-preserving redactions prior to storage; a generative neural processor that is operationally coupled to the data acquisition unit and configured to generate synthetic morphing malware variants by learning probabilistic transformations of previously observed malicious data representations, maintaining semantic functionality while varying structural and behavioral features; a discriminative neural processor trained adversarially with the generative neural processor, wherein the discriminative neural processor is configured to detect morphing malware by evaluating a probability distribution over multimodal telemetry embeddings and classifying anomalous process and flow behaviors in real time; a coordination processor that is communicatively connected to both the generative neural processor and the discriminative neural processor and is configured to orchestrate adversarial co-training, regulate detection thresholds, calculate reinforcement-based penalties for false negative results, and trigger countermeasures as soon as a detection confidence level exceeds a predefined adaptive threshold; a secure, system-integrated inference and enforcement unit configured to perform low-latency countermeasures at the network edge, including selective packet filtering, flow isolation, process interruption, or system microsegmentation, based on instructions from the coordinating processor; and a hardware-embedded security enclave that is embedded in the system and configured to store cryptographic keys, neural model parameters, and integrity affirmation data to ensure the confidentiality, authenticity, and immutability of model artifacts and policy configurations.

The embodiment of the invention discloses a model reasoning calculation acceleration method and device, a medium and a program product, and the method comprises the steps: dividing the number of heads in multi-head attention processing into each processor core group according to the number of processor core groups in a processor in the multi-head attention processing of model reasoning; when the processor core group performs operation between a query vector and a key vector in multi-head attention processing, according to the total amount of the operation tasks and the number of the slave cores in the processor core group, the operation tasks are divided into the slave cores with uniform data volume; when an operation task is jointly processed by at least two slave cores, matrix segmentation is carried out on a query vector and a key vector in the operation task, and each slave core reads a corresponding vector according to a matrix segmentation result to carry out matrix multiplication operation; and caching the first matrix multiplication operation sub-result obtained by calculation of each slave core to a high-speed cache of a specified first target slave core to generate a first matrix multiplication operation result. The calculation efficiency can be improved by balancing the data volume of each slave core.

The present disclosure relates to a data processing method, a processor, a chip, and an electronic device. The method comprises: on the basis of an obtained control instruction, a control logic unit sequentially reads, from a memory to a dot product unit array, loop tiling data of data to be processed; the dot product unit array performs multiply-accumulate operation on the loop tiling data of the data to be processed that is received each time, and determines a loop tiling result of the data to be processed that is received each time; and on the basis of a plurality of loop tiling results obtained from the dot product unit array, the control logic unit determines a logic operation result of the data to be processed. The embodiments of the present disclosure can convert, into the reading and logic operation of multiple pieces of loop tiling data of the data to be processed, the reading and logic operation of the data to be processed, so that data with larger size can be processed under the condition that the hardware resources of the processor are not changed, and the pressure on the storage bandwidth is reduced.

Systems and methods for classifying encrypted data using an encrypted machine learning model are disclosed. An example method includes receiving, at one or more processors, encrypted data from a user that is encrypted in accordance with a first fully homomorphic encryption technique. The example method further includes analyzing, by the one or more processors executing an encrypted ML model that is encrypted in accordance with a second fully homomorphic encryption technique, the encrypted data to output an encrypted classification without decrypting the encrypted data. The example method further includes transmitting, by the one or more processors, the encrypted classification to a user computing device for decryption.

The invention discloses a parallel processor dynamic resource allocation system and method based on reconfigurable hardware, and relates to the technical field of computer chips, and the system comprises a workload monitoring module which is responsible for monitoring the workload type and the resource demand of a task processed by a parallel processor in real time, and determining the task type and the resource demand by identifying the task type and the resource demand; a monitoring result is fed back to the resource allocation control module; the resource allocation control module is responsible for generating a corresponding resource allocation control signal based on feedback information of the workload monitoring module and dynamically configuring the reconfigurable hardware module; the reconfigurable hardware module is responsible for realizing efficient adaptation to diversified tasks through a plurality of reconfigurable units formed by programmable logic devices according to different working load dynamic reconfiguration functions and connection modes; and the data caching and transmission module is responsible for cross-module data circulation and global data storage. Different task requirements can be accurately adapted, and the resource utilization rate is improved.

Disclosed in the present application are a data processing system and method, and a device, a medium and a computer program product in the technical field of computers. The data processing system comprises: at least one processor device and at least one target device connected to the at least one processor device, wherein the processor device and the target device each comprise a consistency function processing device and at least one consistency interface. In the same device, the consistency function processing device is in communication connection with the at least one consistency interface; and two consistency interfaces in different processor devices are in communication connection with each other, two consistency interfaces in different target devices are in communication connection with each other, or two consistency interfaces in any processor device and any target device are in communication connection with each other, such that the cache consistency between different processor devices, the cache consistency between different target devices, or the cache consistency between any processor device and any target device is realized.

A system and method for executing computer readable code instructions for an on-the-box (OTB) artificial intelligence (AI) productivity tool comprising a hardware processor accessing capabilities associated with each of a plurality of AI productivity tool-enablable software applications, a natural language capabilities database memory to store natural language descriptions of the capabilities and capability intent values generated from the natural language descriptions in a capabilities decision tree with each capability node grouped under a branch of the capabilities decision tree according to logical topics in hierarchical parent-child relationships, the hardware processor generating a query input intent value from a user query input and performing a cosine semantic similarity search comparing the capability intent values of the capability nodes along the branch of the capabilities decision tree for identifying a best match capability node having a highest cosine semantic similarity search score, and the hardware processor executing the best match capability.