128 results about "Memory processing" patented technology

The embodiment of the invention provides a memory processing method based on an intelligent agent, a storage medium and an electronic device, a memory architecture of the intelligent agent comprises a first memory layer, a second memory layer and a third memory layer, the first memory layer is used for storing historical dialogue information of interactive dialogue between at least one interactive object and the intelligent agent, and the second memory layer is used for storing historical dialogue information of interactive dialogue between at least one interactive object and the intelligent agent. The second memory layer is used for storing structured events extracted from historical dialogue information, and the third memory layer is used for storing pattern induction memory obtained by performing pattern induction on the structured dialogue events; the method comprises the steps that in response to current round dialogue input information of a target interaction object, target storage information associated with the current round dialogue input information is retrieved from at least one memory layer in a memory architecture, and the current round dialogue input information and the target storage information are assembled into a current cue word; and submitting the current prompt word to a specified interaction model through the intelligent agent, and outputting a response result of the specified interaction model to the interaction object.

The invention provides an agent memory management method and device based on asynchronous processing and a storage medium. The method comprises the following steps: after an interaction event is written into a first storage area, issuing a processing event associated with an event identifier to an event queue, and reading the corresponding interaction event from the first storage area according to the event identifier; when the interaction event passes the importance judgment, converting the interaction event into structured memory data; determining second storage areas based on the type identification field of the structured memory data, and respectively writing the structured memory data into at least one second storage area; and analyzing the query request to obtain a query condition, determining at least one target second storage area based on the query condition, reading structured memory data related to the query request from the target second storage area, performing aggregation processing, and outputting the aggregated memory data to the agent to generate a response result. According to the method, the interaction response delay can be reduced, the model calling cost is reduced, and the memory processing auditing performance is improved.

The invention discloses a large model memory processing method and device, equipment, a storage medium and a product, relates to the technical field of artificial intelligence, and discloses a method for extracting new memory data from a model memory updating instruction in response to the model memory updating instruction; querying target historical memory data associated with the new memory data from a data storage area; adjusting the target historical memory data based on the new memory data through a large language model to obtain adjusted target historical memory data; the new memory data is stored in a data storage area, original target historical memory data in the data storage area is updated to the adjusted target historical memory data, and the memory data in the data storage area is used for model questions and answers. According to the method, the quality of memory data of the large language model can be effectively improved, so that the answer performance of the large language model is guaranteed.

Embodiments of the present application provide a memory processing method based on an agent, a storage medium and an electronic device, wherein the memory architecture of the agent includes a first memory layer, a second memory layer and a third memory layer, the first memory layer is used to store historical dialogue information of an interactive dialogue between at least one interactive object and the agent, the second memory layer is used to store structured events extracted from the historical dialogue information, and the third memory layer is used to store pattern induction memories obtained by pattern induction on the structured events; the method includes: in response to current round dialogue input information of a target interactive object, retrieving target stored information associated with the current round dialogue input information from at least one memory layer in the memory architecture, and assembling the current round dialogue input information and the target stored information into a current prompt; submitting the current prompt to a specified interactive model through the agent, and outputting a response result of the specified interactive model to the interactive object.

The invention provides an agent memory processing method and device, electronic equipment and a readable storage medium, and belongs to the technical field of data processing.The agent memory processing method comprises the steps that in a semantic index layer, based on the semantic similarity between a query vector corresponding to a query request and a semantic feature vector in each semantic pointer, a semantic feature vector in each semantic pointer is obtained; determining a first candidate pointer set, wherein each semantic pointer comprises a semantic feature vector of which the dimension is lower than a dimension threshold value and a reference identifier pointing to the memory in the detail data layer; adding a second semantic pointer of which the correlation with each first semantic pointer in the first candidate pointer set is greater than a correlation threshold value into the first candidate pointer set to obtain a second candidate pointer set; and loading a memory corresponding to a semantic feature vector in a target semantic pointer from the detail data layer by using a target reference identifier in the target semantic pointer meeting a preset loading condition in the second candidate pointer set. Efficient data loading and recalling indirect associated memory can be realized.

Provided are systems, methods, and apparatuses for systems and methods of programming processes in processing in memory (PIM) systems. In one or more examples, the systems, devices, and methods include enabling, via a processor, a PIM manager for processing of PIM instructions, the PIM manager being located on a base die of a stacked memory module; enabling, via the PIM manager, a plurality of processing units of one or more memory dies of the stacked memory module for processing; compiling source code comprising the PIM instructions into machine code; loading, via PIM manager, the machine code into an allocation of memory of the stacked memory module; and executing, via the plurality of processing units, the PIM instructions based on loading the machine code into the memory of the stacked memory module.

The invention relates to an in-memory processing device and an in-memory processing package with asymmetric internal and external bandwidths. In one embodiment, an in-memory processing (PIM) device includes a processing unit die configured to communicate with an external device over an external bandwidth, and a storage die configured to communicate with the processing unit die over an internal bandwidth. The external bandwidth and the internal bandwidth are asymmetrically configured to operate at different data transfer rates.

A processing unit includes a redundant remainder generation circuit that converts first operand data and second operand data into a plurality of first operand redundant remainder sets and a plurality of second operand redundant remainder sets based on a redundant remainder system (RRNS) using first to Tth moduli. T is a natural number equal to or greater than 4. The processing unit includes a plurality of arithmetic circuits that perform operations using the plurality of first operand redundant remainder sets and the plurality of second operand redundant remainder sets, and a reconstruction circuit that restores the RRNS-based result data to the weighted coefficient-based result data. An in-memory processing (PIM) apparatus and an in-memory processing (PIM) system are also provided.

The embodiment of the invention provides a security defense method and device based on Hypervisor, and relates to the technical field of virtualization. The method comprises the steps of determining a memory processing type in response to a preset trigger operation; and calling an hvc command by calling a virtual machine monitor corresponding to the memory processing type so as to indicate a Hypervisor to execute a Hypervisor processing function corresponding to the hvc command. According to the embodiment of the invention, the distribution or release of the internal memory of the process is realized through the Hypervisor with higher authority, even if the kernel of the operating system is broken by a malicious application program, the integrity of a security mechanism of the operating system can still be ensured, and the effective defense of security threats of the operating system is realized.

The invention discloses a memory device, an operating method thereof, and an in-memory processing device. The memory device includes an in-memory processing (PIM) block configured to perform an operation between a weight value and an input value, the weight value being represented by a weight scaling factor and a weight element, the input value being represented by an input scaling factor and an input element, where the PIM block includes: a first scaling register file storing the input scaling factor; a second scaling register file storing a weight scaling factor; a scalar register file (SRF) storing input elements; a plurality of arithmetic logic units (ALU) configured to perform a first operation between the input scaling factor and the weight scaling factor and a second operation between the input element and the weight element in parallel in response to an operation command received from a host; and an accumulator configured to accumulate and store operation results of the first operation and the second operation.

A notification device includes an image acquisition unit that acquires images, a steady-state determination unit that determines whether a non-temporary malfunction state occurs in the camera system, a memory processing unit that stores malfunction information in a storage area, a start-up determination unit that determines whether the non-temporary malfunction state exists during the period until the steady-state determination unit is able to determine the occurrence of the non-temporary malfunction state, and an alarm output process processing unit that outputs an alarm when each determination unit determines that the non-temporary malfunction state exists. The start-up determination unit includes a previous information acquisition unit that acquires the malfunction information stored in the storage area when the control unit of the vehicle was turned off from a previous power-on state, and a provisional determination unit that determines that the non-temporary malfunction state exists if the previous information obtained by the previous information acquisition unit indicates that the non-temporary malfunction state exists, and determines that the non-temporary malfunction state does not exist if the previous information obtained by the previous information acquisition unit indicates that the non-temporary malfunction state does not exist.

The application provides a water turbine full-state intelligent early warning method and device and a server, relates to the technical field of intelligent operation and maintenance of hydroelectric generating equipment, and comprises the following steps: performing data cleaning processing and multi-scale time alignment processing on multi-modal data, performing feature fusion processing on target multi-modal data based on a cross-modal attention model to obtain target fusion features; adopting a multi-modal space-time memory network model, performing history state memory processing on the target fusion features through a four-branch parallel memory structure to obtain a memory state set, and performing cross-modal memory fusion processing on each memory state in the memory state set through a covariance adaptive fusion model to obtain a unified memory state; inputting the unified memory state into a full connection network model to perform mapping processing on a future state to obtain a prediction value and an uncertainty degree of the future state of the water turbine, and performing hierarchical early warning based on the prediction value and the uncertainty degree. The application can significantly improve the accuracy of intelligent early warning.

The application discloses a kind of multi-motor synchronous control methods based on neural network prediction compensation, comprising the following steps: collecting each motor speed, position, current and bus voltage signal, sampling time alignment is carried out to the collected signal, constructs motor state vector set and generates synchronous reference quantity;According to the synchronous reference quantity, the synchronization error of each motor is calculated, and the coupling error characteristics are established in combination with the topological connection relationship of multi-motor;The fractional order memory processing is carried out to the coupling error characteristics, and the working condition characteristics are fused to form a unified input vector;The radial basis function neural network outputs disturbance prediction result and prediction compensation result;Based on coupling error, memory error and prediction compensation result, generate synchronous control quantity, and map to each motor control increment;According to error state and control increment, update network weight and fractional order parameter, generate each motor drive control instruction and issue to corresponding driver.

The invention provides a computing accelerator card, a node state determination method and device and a medium, and relates to the field of data processing. The computing accelerator card includes an interface configured to receive respective initial states and initial weight sums of a plurality of nodes in an Isin model and edge weights among the plurality of nodes; an on-chip memory configured to store edge weights between the plurality of nodes; the near storage processing unit array comprises a plurality of processing units, each processing unit comprises an adder and a local storage unit, and the local storage unit is configured to store the state and the weight sum of at least one node in the plurality of nodes; and the state updating unit is configured to read the current state and the current weight sum of the target node from the processing unit corresponding to the target node, and determine whether to update the state of the target node. In response to determining that the state of the target node needs to be updated, the plurality of processing units corresponding to the plurality of adjacent nodes are configured to update the weight sum of the plurality of adjacent nodes in parallel.

A memory device includes: a memory storing instructions; and a processing unit including one or more processors, wherein the memory device is connected with a host processor through an interface, and wherein, the instructions, when executed by the processing unit, cause the memory device to: select, from among memory blocks stored in the memory, candidate hot memory blocks, the selecting based on access counts of the respective memory blocks stored in the memory; select a hot sub-block based on a number access counts of respective sub-blocks, including the hot sub-block, split from the selected candidate hot memory blocks; and transmit the selected hot sub-block to the host processor, based on a memory command regarding the hot sub-block, wherein the memory command is received from the host processor by the processing unit.

The application discloses an in-memory processing-based personalized recommendation system, and relates to the field of personalized recommendation.The system comprises a bottom full-connection engine, an embedding engine, a buffer, a top full-connection engine and a central processing unit.The embedding engine comprises an embedding module and a prediction module.The embedding module is composed of a ReRAM cross array, which is denoted as an embedding array, and each row of the embedding array stores a user interaction vector.The prediction module is composed of a group of vertically arranged ReRAM cross arrays, which is denoted as a prediction array, and each column of the prediction array is connected to the corresponding row in the embedding array.The embedding engine in the in-memory processing-based personalized recommendation system provided by the application sets the embedding module and the prediction module, utilizes the parallelism and high energy efficiency of ReRAM, reduces the bandwidth requirement, accelerates the embedding calculation of the embedding engine, and thus the computing speed of the personalized recommendation system is improved, and the efficiency and accuracy of the recommendation result are improved.

In some implementations, a programmable processor of a memory system may receive, from a host system, programming information, the programming information indicating one or more near memory processing (NMP) tasks that are to be performed by the programmable processor. The programmable processor may execute the one or more NMP tasks based on the programming information.

Embodiments of this application provide a memory processing method, an electronic device, and a readable storage medium. In the method, in a scenario in which an application program and a hardware device share a first physical memory, when the application program is switched to a background, the application program sends a first command to a memory processing apparatus, where the first command indicates to release the first physical memory of the application program; and the memory processing apparatus releases the first physical memory in response to the first command. In embodiments of this application, when the application program is switched to the background, and temporarily does not need to use the first physical memory, the application program may actively request to release the first physical memory, to increase an available memory of an electronic device.

Disclosed are a method and apparatus for in-memory processing (PIM) compute address generation, the method comprising: generating a memory request related to an in-memory processing (PIM) operation; obtaining a PIM compute address in response to the memory request; sending the memory request and the PIM compute address to a memory controller; and specifying, by the memory controller, a memory address through bank shuffling, the bank shuffling mapping the PIM compute address to a set of addresses shuffled to a preset target bank.

Systems, methods, and apparatus provide systems and methods for concurrent execution of in-memory processing (PIM) operations. In one or more examples, the systems, devices, and methods include receiving a memory request for processing on a memory die; modifying the memory request for processing on the memory die based on the memory request being configured; and sending the modified memory request to a processing unit on the memory die. In one or more examples, systems, devices, and methods include enabling a memory die for processing of PIM on-die processing, and disabling the memory die for off-die processing.

The invention relates to a memory processing method and device, a memory management system, electronic equipment and a chip, and belongs to the technical field of memory management. The method comprises the following steps: in response to a memory processing request, performing memory allocation and memory recovery processing corresponding to the memory processing request by adopting a target memory; wherein the target memory is a memory allocated to target hardware of the electronic equipment by a processor of the electronic equipment; in response to the fact that the first number of idle memories in the target memories is smaller than a first set threshold value, requesting the processor to distribute the idle memories to the target hardware to increase the first number; and in response to the first number being greater than a second set threshold, releasing the idle memory to the processor to reduce the first number. Therefore, the processor can distribute the target memory to the target hardware, the target hardware can respond to the memory processing request, the target memory is adopted for memory distribution and recovery processing, the load of the processor can be remarkably reduced, and the memory processing efficiency is remarkably improved.

A system for reducing memory processing resources comprises one or more processors configured to generate a plurality of principal components (PCs) corresponding to characteristic data for entities in a dataset to reduce a size of the dataset; generate a score for each entity in the dataset based at least on (i) the PCs, and (ii) weights for a condition of interest; determine a set of alternates that correspond to the condition of interest; determine, using a machine learning model, interactions between the set of alternates for one or more target components corresponding to the object and the scores, wherein the interactions are indicative of a response for the condition of interest; and perform one or more actions.

The invention discloses a memory processing method and device, equipment, a storage medium and a program product. The method comprises the following steps: receiving a query request of a user, and identifying a query intention type of the query request; determining target weight configuration of a plurality of memory types based on the query intention type, wherein the plurality of memory types comprise plot memory, semantic memory, programmed memory and emotion memory; determining a semantic similarity score of the candidate memory data according to the semantic similarity and the target weight configuration, and determining a comprehensive score of the candidate memory data according to the semantic similarity score and the semantic strength score; and determining initial target memory from the candidate memory data according to the comprehensive score, determining associated memory data of the initial target memory based on a co-activation association relationship among the memory data, and taking the initial target memory and the associated memory data as target memory data.

An apparatus includes a global memory and a systolic array. The global memory is configured to store and provide an input feature map (IFM) vector stream from an IFM tensor and a kernel vector stream from a kernel tensor. The systolic array is configured to receive the IFM vector stream and the kernel vector stream from the global memory. The systolic array is on-chip together with the global memory. The systolic array includes a plurality of processing elements (PEs) each having a plurality of vector units, each of the plurality of vector units being configured to perform a dot-product operation on at least one IFM vector of the IFM vector stream and at least one kernel vector of the kernel vector stream per unit clock cycle to generate a plurality of output feature maps (OFMs).

A memory processing system includes a processor, a main memory, and a MMU coupled to the processor and the main memory. The processor is used to generate a plurality of virtual addresses. The main memory includes a plurality of data corresponding to physical addresses in a main page table. The main page table is used to map the plurality of virtual addresses to the plurality of physical addresses. The memory management unit includes a TLB coupled to the processor and the main memory, a table walk unit coupled to the TLB and the main memory, and a merger coupled to the TLB and the processor. The TLB performs address translation by retrieving a physical address according to a virtual address from a first page table in the TLB or a second page table in the table walk unit or the main page table in the main memory.

The invention relates to address updates using spans for in-memory processing. The address can be updated to perform a convolution operation. Updating addresses can include determining, at a MAC engine coupled to an array of memory cells, a first address of first data and accessing the first data from the array using the first address. Updating the address can also include performing, at the MAC engine, a first convolution operation using the first data. Updating the address can further include determining, at the MAC engine, a second address for second data using a span corresponding to a second convolution operation and accessing the second data from the array using the second address. Updating the address can also include performing, at the MAC engine, a second convolution operation using the second data.

The invention relates to the technical field of artificial intelligence, and provides a data processing method and device based on an in-memory processing flow, and a medium. The method comprises the following steps: in a PIM mode of a first DRAM, calculating a first Q vector, a first K vector and a first V vector of a self-attention layer by using the first DRAM; in a non-PIM mode of the second DRAM, storing the first K vector, the first V vector and the first Q vector into the second DRAM; in a PIM mode of the first DRAM, performing self-attention calculation based on the first Q vector and a second K vector and a second V vector stored in the second DRAM to obtain second output information corresponding to a self-attention layer; and inputting the second output information to a subsequent network. According to the technical scheme, the problem that self-attention calculation in a neural network model is difficult to realize by an in-memory processing calculation process of an in-memory processing technology based on a dynamic random access memory at present can be solved.

The invention discloses a retrieval enhancement generation reasoning acceleration system and method based on in-memory calculation. According to the system, a decentralized document attention decomposition mechanism is adopted, attention calculation of document key value pairs is distributed to a plurality of in-memory processing devices to be independently executed, and the data transmission amount is reduced through local aggregation. The system architecture comprises a plurality of in-memory computing PIM devices, and each device integrates a PIM unit and a controller side unit to jointly complete a computing task. The scheduler adopts a hybrid scheduling strategy combining static mapping and dynamic triggering, supports multiple parallel modes, and improves the resource utilization rate through an interlaced execution mechanism. According to the method, data transmission overhead and calculation delay in RAG reasoning are remarkably reduced, and the method is suitable for a language model reasoning scene with large-scale knowledge enhancement.

Provided are a computer program product, system, and method for compiling an application having polynomial operations to produce directed acyclic graphs having commands to execute in a near memory processing device. An application is compiled including operations on a polynomial having coefficients, decomposed into a number of levels of coefficient elements, to generate hierarchical directed acyclic graphs (DAGs) having nodes indicating commands for execution by a hierarchy of hardware components in a near memory processing (NMP) device. The hierarchy of hardware components includes a plurality of enclaves of tiles. Each tile includes memory and a processing element to perform operations on the decomposed coefficients stored in the memory of the tile. Each of the hardware components includes a controller to process the commands in the DAG generated for the hardware components. The DAGs are provided to a hierarchical DAG tracker to generate commands for the NMP device.