192 results about "Memory processing" patented technology

The invention provides a hybrid parallel and dynamic scheduling method of a hybrid expert model based on 3D near-memory processing. The method comprises the following steps: establishing a joint performance analysis model; performing off-line linear programming optimization expert distribution; performing Bayesian optimization on physical node mapping; performing online reasoning; carrying out online dynamic priority detection; and an expert pre-broadcast and communication-friendly lexical element distribution strategy with optimal efficiency is provided. According to the method, node balancing optimization is realized through offline linear programming, and the problem of load imbalance of 3D NMP calculation is remarkably improved; in combination with a Bayesian optimization mapping strategy of link balance, the communication speed-up ratio is increased, and NoC link congestion is reduced; a dynamic scheduling strategy adapts to dynamic changes of expert activation in real-time reasoning through calculation load prediction and a pre-broadcast mechanism. Through cooperation of the offline automatic hybrid parallel mapping algorithm and the online dynamic scheduling strategy, the calculation load and the communication overhead are effectively balanced, and the reasoning efficiency of the hybrid expert model MoE on the 3D near-memory processing architecture is remarkably improved.

The embodiment of the invention provides a memory processing method based on an intelligent agent, a storage medium and an electronic device, a memory architecture of the intelligent agent comprises a first memory layer, a second memory layer and a third memory layer, the first memory layer is used for storing historical dialogue information of interactive dialogue between at least one interactive object and the intelligent agent, and the second memory layer is used for storing historical dialogue information of interactive dialogue between at least one interactive object and the intelligent agent. The second memory layer is used for storing structured events extracted from historical dialogue information, and the third memory layer is used for storing pattern induction memory obtained by performing pattern induction on the structured dialogue events; the method comprises the steps that in response to current round dialogue input information of a target interaction object, target storage information associated with the current round dialogue input information is retrieved from at least one memory layer in a memory architecture, and the current round dialogue input information and the target storage information are assembled into a current cue word; and submitting the current prompt word to a specified interaction model through the intelligent agent, and outputting a response result of the specified interaction model to the interaction object.

The invention provides an agent memory management method and device based on asynchronous processing and a storage medium. The method comprises the following steps: after an interaction event is written into a first storage area, issuing a processing event associated with an event identifier to an event queue, and reading the corresponding interaction event from the first storage area according to the event identifier; when the interaction event passes the importance judgment, converting the interaction event into structured memory data; determining second storage areas based on the type identification field of the structured memory data, and respectively writing the structured memory data into at least one second storage area; and analyzing the query request to obtain a query condition, determining at least one target second storage area based on the query condition, reading structured memory data related to the query request from the target second storage area, performing aggregation processing, and outputting the aggregated memory data to the agent to generate a response result. According to the method, the interaction response delay can be reduced, the model calling cost is reduced, and the memory processing auditing performance is improved.

The invention discloses a memory processing method and system for a generative model, an information interaction method and system, a medium and equipment. The method comprises the steps of obtaining interaction information between a user and a generative model, and storing the interaction information in a first database of a basic memory area; extracting and summarizing the interaction information in the first memory period to obtain memory fragment information, and storing the memory fragment information in a second database of a fragment memory area; summarizing the memory fragment information in the second memory period into topic information according to topic relevancy, and storing the topic information in a third database of a topic memory area; summarizing the topic information exceeding the second memory period as topic conclusion information, and storing the topic conclusion information in a vector retrieval engine of a historical memory area; and in response to received user query information, querying related information in the basic memory area, the fragment memory area, the topic memory area and the historical memory area, and generating reply information. According to the method, the information storage, processing and retrieval capabilities of the model can be improved.

Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors. The one or more processor subunits are configured to receive a sparse vector indicator from a host external to the at least one computational memory chip and, based on the received sparse vector indicator and the one or more portions of the embedding table, generate one or more vector sums.

The invention discloses a virtual machine memory processing method and device, a product, a virtualization server and a medium, and relates to the field of server virtualization. In the method, through a virtual input and output rear-end module arranged on a virtual machine monitor in a host and a virtual input and output front-end module on a virtual machine, it is ensured that the virtual input and output rear-end module can obtain information of a memory allocation event of direct memory access; secondly, after acquiring the information of the memory allocation event of the direct memory access, the virtual input / output rear-end module locks the address related to the memory allocation event, namely, the locked address meets the direct memory access requirement, and the memory of the virtual machine is dynamically locked, so that the memory utilization rate is improved, and the waste of resources is reduced; and only part of the memory of the virtual machine is locked, and only the locked memory part is migrated after the host is replaced, so that the amount of data to be migrated after the host is replaced is reduced.

The invention discloses a memory fault management system and method, a server and electronic equipment, and relates to the technical field of computers, the memory fault management system comprises a processing circuit of a hardware memory, a hardware layer and a processor are arranged on the processing circuit, and the processor is further divided into a kernel layer, a user layer and an input and output layer. Through cooperative work of the hardware layer and each software layer, hierarchical detection, classified processing and automatic isolation of memory error data are realized, and server downtime caused by memory fault error data is effectively prevented. And meanwhile, through a linkage mechanism of a kernel mode and a user mode and in combination with visual display, the monitorability and maintainability of memory errors are enhanced, operation and maintenance personnel can quickly position and repair problems conveniently, and the operation and maintenance cost of the system is reduced.

The invention discloses a memory processing system, method and device, a medium and a program product in the technical field of computers. In the application, the plurality of memory devices are used as extended memories of the plurality of computing devices in the host. The switching devices are connected between the computing devices and the memory devices and can determine the memory devices connected with downstream ports, record corresponding memory connection relations and send the memory connection relations to a main management controller in a host; when any computing device reads and writes the memory abnormally, the main management controller locates the abnormal memory device based on all the received memory connection relationships, and sends a hot removal command to the switching device connected with the abnormal memory device through the network device, so that the corresponding switching device responds to the hot removal command and performs hot removal on the abnormal memory device. Therefore, global memory connection topology identification, fault detection and hot removal are realized for the memory device, and normal operation of host services is not affected.

The invention provides a memory database starting method, system and device and a medium, and belongs to the technical field of computers. The method comprises the following steps: detecting a current project scale and a performance index of an original server, and determining whether to trigger a memory processing mechanism; if a memory processing mechanism is triggered, selecting a memory server according to high-performance computing and expansibility requirements, accessing an original server by utilizing a hot plug technology, configuring a memory database and initializing a memory computing cluster; configuring a to-be-synchronized database table by utilizing a metadata management function, loading original data to a memory database through a full-amount synchronization and incremental updating mechanism, and starting real-time data synchronization; starting a memory computing cluster, automatically detecting a memory processing state on an original server when a service task is triggered, and routing a large quantity of data tasks meeting conditions to a memory server to execute parallel computing. According to the method, the memory can be dynamically started for data processing, the operation efficiency is improved, and the user experience is improved.

The invention relates to the technical field of artificial intelligence, can be applied to business system platforms of financial science and technology, medical health and the like, and discloses a data processing method, device, equipment and medium based on man-machine interaction. Performing basic intention classification on the standardized data to obtain classified data; performing context memory processing on the classified data to obtain memory data; performing fine-grained analysis on the memory data to obtain analysis data; constructing a multi-dimensional query vector for the analysis data, and combining the multi-dimensional query vector with a preset external knowledge base to generate an intermediate reply; and performing optimization adjustment on the intermediate reply according to a pre-obtained feedback mechanism to obtain an optimization result. By deeply understanding the intention of the user and providing personalized services, the satisfaction and convenience of the user are remarkably improved, the user can obtain more accurate, more timely and more demand-meeting response in the use process, and the interaction experience is enhanced.

The invention discloses a large model memory processing method and device, equipment, a storage medium and a product, relates to the technical field of artificial intelligence, and discloses a method for extracting new memory data from a model memory updating instruction in response to the model memory updating instruction; querying target historical memory data associated with the new memory data from a data storage area; adjusting the target historical memory data based on the new memory data through a large language model to obtain adjusted target historical memory data; the new memory data is stored in a data storage area, original target historical memory data in the data storage area is updated to the adjusted target historical memory data, and the memory data in the data storage area is used for model questions and answers. According to the method, the quality of memory data of the large language model can be effectively improved, so that the answer performance of the large language model is guaranteed.

The concepts and technologies disclosed herein are directed to software runtime assisted co-processing acceleration with a memory hierarchy augmented with compute elements. An example system disclosed herein includes one or more switches and a plurality of hardware compute nodes connected via the one or more switches. Each hardware compute node of the plurality of hardware compute nodes includes an in-memory compute (IMC) element configured to perform in-memory processing operations on data, such as graph data. The system also includes a near-memory compute (NMC) element configured to perform near-memory processing operations on the data. The system also includes a far-memory compute (FMC) element configured to perform far-memory processing operations on the data.

Provided are a computer program product, system, and method for compiling an application having polynomial operations to produce directed acyclic graphs having commands to execute in a near memory processing device. An application is compiled including operations on a polynomial having coefficients, decomposed into a number of levels of coefficient elements, to generate hierarchical directed acyclic graphs (DAGs) having nodes indicating commands for execution by a hierarchy of hardware components in a near memory processing (NMP) device. The hierarchy of hardware components includes a plurality of enclaves of tiles. Each tile includes memory and a processing element to perform operations on the decomposed coefficients stored in the memory of the tile. Each of the hardware components includes a controller to process the commands in the DAG generated for the hardware components. The DAGs are provided to a hierarchical DAG tracker to generate commands for the NMP device.

Embodiments of the present application provide a memory processing method based on an agent, a storage medium and an electronic device, wherein the memory architecture of the agent includes a first memory layer, a second memory layer and a third memory layer, the first memory layer is used to store historical dialogue information of an interactive dialogue between at least one interactive object and the agent, the second memory layer is used to store structured events extracted from the historical dialogue information, and the third memory layer is used to store pattern induction memories obtained by pattern induction on the structured events; the method includes: in response to current round dialogue input information of a target interactive object, retrieving target stored information associated with the current round dialogue input information from at least one memory layer in the memory architecture, and assembling the current round dialogue input information and the target stored information into a current prompt; submitting the current prompt to a specified interactive model through the agent, and outputting a response result of the specified interactive model to the interactive object.

Provided are a device, system, and computer program product for a near memory processing device to process coefficient elements resulting from decomposition of polynomials. A near memory processing device includes a plurality of enclaves and a plurality of interconnected tiles on each enclave. Coefficients of a polynomial are decomposed into a number of levels of the coefficient elements. Each level of coefficient elements comprises a limb. A device control receives hierarchical commands, from an application, that map operations to perform on limbs of coefficient elements to the enclaves and that map operations for the enclaves to the tiles in the enclaves. The device controller distributes operations for the tiles in the hierarchical commands to perform on the coefficient elements to the enclaves to distribute operations to perform on the coefficient elements to the tiles.

The invention provides an agent memory processing method and device, electronic equipment and a readable storage medium, and belongs to the technical field of data processing.The agent memory processing method comprises the steps that in a semantic index layer, based on the semantic similarity between a query vector corresponding to a query request and a semantic feature vector in each semantic pointer, a semantic feature vector in each semantic pointer is obtained; determining a first candidate pointer set, wherein each semantic pointer comprises a semantic feature vector of which the dimension is lower than a dimension threshold value and a reference identifier pointing to the memory in the detail data layer; adding a second semantic pointer of which the correlation with each first semantic pointer in the first candidate pointer set is greater than a correlation threshold value into the first candidate pointer set to obtain a second candidate pointer set; and loading a memory corresponding to a semantic feature vector in a target semantic pointer from the detail data layer by using a target reference identifier in the target semantic pointer meeting a preset loading condition in the second candidate pointer set. Efficient data loading and recalling indirect associated memory can be realized.

The invention relates to a storage processing method and device based on a capacitance-free DRAM (Dynamic Random Access Memory), and the method comprises the steps: preparing a corresponding writing transistor and a corresponding reading transistor through a preset oxide semiconductor and a silicon transistor; based on a preset heterogeneous integration strategy, vertically stacking the write transistor on the read transistor to establish a capacitance-free DRAM memory unit; the method comprises the following steps: establishing a heterogeneous integrated capacitance-free DRAM memory macro based on a pre-established storage unit peripheral circuit and a capacitance-free DRAM memory unit, and establishing a corresponding in-memory processing architecture according to the heterogeneous integrated capacitance-free DRAM memory macro and a pre-established convolution kernel logic circuit, so as to execute corresponding storage operation through the in-memory processing architecture. Therefore, the technical problems that in the prior art, a DRAM memory processing framework is high in process cost, incompatible in preparation process, high in circuit complexity, poor in memory processing speed and the like are solved.

Provided are systems, methods, and apparatuses for systems and methods of programming processes in processing in memory (PIM) systems. In one or more examples, the systems, devices, and methods include enabling, via a processor, a PIM manager for processing of PIM instructions, the PIM manager being located on a base die of a stacked memory module; enabling, via the PIM manager, a plurality of processing units of one or more memory dies of the stacked memory module for processing; compiling source code comprising the PIM instructions into machine code; loading, via PIM manager, the machine code into an allocation of memory of the stacked memory module; and executing, via the plurality of processing units, the PIM instructions based on loading the machine code into the memory of the stacked memory module.

The invention discloses a data processing system, method and equipment, a medium and a program product in the technical field of computers. In the invention, a cache coherence root port of a computing device is connected with a cache coherence sub-port of a memory processing device through a cache coherence protocol, so that the computing device is used for synchronizing a query matrix of a model processing task and a first result output in a key value matrix calculation stage to the memory processing device through the cache coherence protocol; meanwhile, the memory processing device can synchronize the second result to the computing device through the cache coherence protocol, so that rapid data transmission between the computing device and the memory processing device is realized, the memory space of the computing device is saved, the overhead of a host processor in the execution process of the model processing task is reduced, and the performance of the model processing task is improved. And the task processing efficiency of the hardware computing equipment can be improved to a certain extent.

Provided are a near memory device, system, and method for processing coefficient elements resulting from decomposition of polynomials. The near memory device includes a plurality of enclaves and a plurality of interconnected tiles on each enclave. A tile includes a memory and a processing element to perform operations on decomposed coefficients stored in the memory of the tile. An enclave controller in an enclave of the enclaves receives an operation for coefficients of a polynomial. Each of the coefficients are decomposed into a number of levels of coefficient elements. The enclave controller distributes the coefficient elements to the tiles in the enclave to have processing elements of the tiles load and process the coefficient elements and store the processed results.

Provided are a device, system, and computer program product for a near memory processing device to process coefficient elements resulting from decomposition of polynomials. A near memory processing device includes a plurality of enclaves and a plurality of interconnected tiles on each enclave. Coefficients of a polynomial are decomposed into a number of levels of the coefficient elements. Each level of coefficient elements comprises a limb. A device control receives hierarchical commands, from an application, that map operations to perform on limbs of coefficient elements to the enclaves and that map operations for the enclaves to the tiles in the enclaves. The device controller distributes operations for the tiles in the hierarchical commands to perform on the coefficient elements to the enclaves to distribute operations to perform on the coefficient elements to the tiles.

The invention relates to an in-memory processing device and an in-memory processing package with asymmetric internal and external bandwidths. In one embodiment, an in-memory processing (PIM) device includes a processing unit die configured to communicate with an external device over an external bandwidth, and a storage die configured to communicate with the processing unit die over an internal bandwidth. The external bandwidth and the internal bandwidth are asymmetrically configured to operate at different data transfer rates.

The present application relates to a method, device, electronic device, and storage medium for processing a resistive random access memory (RRAM). The method includes: determining whether there is a need to process a RRAM; if there is a need to process a RRAM, performing a forward forming operation on the RRAM to be processed to obtain a RRAM after forward processing; if the conductance of the RRAM after forward processing is greater than or equal to a first preset conductance threshold, repeatedly applying a first RESET pulse to the RRAM after forward processing until the conductance of the RRAM after forward processing is less than the first preset conductance threshold, thereby obtaining a RRAM after reverse processing; and repeatedly applying a second RESET pulse to the RRAM after reverse processing until the conductance of the RRAM after reverse processing is greater than the second preset conductance threshold, thereby obtaining a target RRAM. This solves the problem of relaxation of the target memory after programming and enhances the stability of the conductance state of the RRAM after programming.

A processing unit includes a redundant remainder generation circuit that converts first operand data and second operand data into a plurality of first operand redundant remainder sets and a plurality of second operand redundant remainder sets based on a redundant remainder system (RRNS) using first to Tth moduli. T is a natural number equal to or greater than 4. The processing unit includes a plurality of arithmetic circuits that perform operations using the plurality of first operand redundant remainder sets and the plurality of second operand redundant remainder sets, and a reconstruction circuit that restores the RRNS-based result data to the weighted coefficient-based result data. An in-memory processing (PIM) apparatus and an in-memory processing (PIM) system are also provided.

A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of compute cores. The second memory can be coupled to the plurality of processing regions. The control logic can configure data flow between compute cores of one or more of the processing regions and corresponding adjacent regions of the first memory. The control logic can also configure data flow between the second memory and the compute cores of one or more of the processing regions. The control logic can also configure data flow between compute cores within one or more respective ones of the processing regions. The control logic can also configure array data for storage memory of the MPU.

The invention discloses a high-performance operation and maintenance monitoring method for energy storage equipment. The method comprises four steps of data acquisition, data processing, data analysis and data display. Through full-memory processing, multi-task queue and transaction batch updating mechanisms, the event processing efficiency is remarkably improved, and the database load is reduced. The data acquisition supports millisecond-level frequency and breakpoint resume; the data processing generates a structured event based on protocol analysis; data analysis dynamically marks event states and updates the event states in batches; and data display is realized through real-time visual alarm of a webpage end. The method is suitable for a large-scale energy storage system, and efficient and stable operation and maintenance monitoring is achieved.

Provided are a computer program product, system, and method for compiling an application having polynomial operations to produce directed acyclic graphs having commands to execute in a near memory processing device. An application is compiled including operations on a polynomial having coefficients, decomposed into a number of levels of coefficient elements, to generate hierarchical directed acyclic graphs (DAGs) having nodes indicating commands for execution by a hierarchy of hardware components in a near memory processing (NMP) device. The hierarchy of hardware components includes a plurality of enclaves of tiles. Each tile includes memory and a processing element to perform operations on the decomposed coefficients stored in the memory of the tile. Each of the hardware components includes a controller to process the commands in the DAG generated for the hardware components. The DAGs are provided to a hierarchical DAG tracker to generate commands for the NMP device.

The embodiment of the invention provides a security defense method and device based on Hypervisor, and relates to the technical field of virtualization. The method comprises the steps of determining a memory processing type in response to a preset trigger operation; and calling an hvc command by calling a virtual machine monitor corresponding to the memory processing type so as to indicate a Hypervisor to execute a Hypervisor processing function corresponding to the hvc command. According to the embodiment of the invention, the distribution or release of the internal memory of the process is realized through the Hypervisor with higher authority, even if the kernel of the operating system is broken by a malicious application program, the integrity of a security mechanism of the operating system can still be ensured, and the effective defense of security threats of the operating system is realized.

Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.

To provide a Karaoke device that enables at least a partial refund when coins are inserted into a coin counter after communication with the host computer is disconnected.SOLUTION: In a Karaoke device comprising a Karaoke main unit, speakers, a display device, a microphone, and a remote control device, the Karaoke main unit 20 includes: a memory processing unit that stores remaining balance, remaining number of plays, and play fee at a point when communication with a host computer is disconnected; a confirmation unit that calculates the number of plays from the remaining balance, the amount corresponding to a deposit signal, and the play fee, and confirms the difference obtained by subtracting the number of plays from the remaining number of plays, when receiving the deposit signal including the amount of coins inserted into the coin counter after the communication with the host computer is disconnected; and a deposit processing unit that transmits a refund signal to the coin counter if the remaining number of plays is less than the number of plays.SELECTED DRAWING: Figure 4