228 results about "In-Memory Processing" patented technology

The invention provides a hybrid parallel and dynamic scheduling method of a hybrid expert model based on 3D near-memory processing. The method comprises the following steps: establishing a joint performance analysis model; performing off-line linear programming optimization expert distribution; performing Bayesian optimization on physical node mapping; performing online reasoning; carrying out online dynamic priority detection; and an expert pre-broadcast and communication-friendly lexical element distribution strategy with optimal efficiency is provided. According to the method, node balancing optimization is realized through offline linear programming, and the problem of load imbalance of 3D NMP calculation is remarkably improved; in combination with a Bayesian optimization mapping strategy of link balance, the communication speed-up ratio is increased, and NoC link congestion is reduced; a dynamic scheduling strategy adapts to dynamic changes of expert activation in real-time reasoning through calculation load prediction and a pre-broadcast mechanism. Through cooperation of the offline automatic hybrid parallel mapping algorithm and the online dynamic scheduling strategy, the calculation load and the communication overhead are effectively balanced, and the reasoning efficiency of the hybrid expert model MoE on the 3D near-memory processing architecture is remarkably improved.

An apparatus comprises a processing device comprising a processor coupled to a memory. The processing device is configured to receive, over a first communication channel from an orchestrator entity, at least one command specifying one or more actions to take involving an endpoint device, the one or more actions comprising at least one of writing data to a tag of a tag bridge device and reading data from the tag of the tag bridge device. The processing device is further configured to relay the at least one command to the tag of the tag bridge device over a second communication channel, the second communication channel being established between a tag interface of the processing device and the tag bridge device, wherein the tag bridge device, 10 when plugged in to a port of the endpoint device, relays the at least one command from the tag to the endpoint device.

The invention provides a distributed recommendation method and system based on near data processing, the recommendation system proposes a near memory processing (NMP) architecture by utilizing a memory decoupling technology and a memory expansion capability of Compute Express Link (CXL) so as to realize extensible and efficient recommendation model training; the design of the ReCXL comprises a uniform and hardware-efficient NMP framework, the training of the whole embedded layer can be executed in a CXL memory, the forward propagation and reverse propagation processes are completed, the data volume transmitted through the bandwidth-limited CXL is minimized, and the utilization of the bandwidth of the internal memory is improved. In addition, the design of the ReCXL utilizes flexible management of memory resources and optimization of bandwidth bottleneck in the training process of a recommendation system (DLRM). By implementing near-memory processing in the CXL memory pool, the ReCXL improves the training efficiency. The ReCXL also integrates software and hardware co-optimization techniques, including independent prefetching and fine-grained update scheduling, to maximize the utilization rate of hardware and further improve performance.

The invention aims to provide an efficient memory allocation and recovery method for an Android device, and relates to the technical field of memory processing, the method comprises the following steps: step 1: obtaining running data of the Android device, and calculating a memory state entropy based on the running data; calculating a memory fragment risk degree in combination with the priority matrix and the operation data; 2, calculating a memory allocation dynamic threshold according to the memory fragmentation risk degree; calculating a self-adaptive memory compression rate; step 3, using a self-adaptive memory compression rate to compress memory data which is not used by the Android device at present; the page number of the activity process is lower than the set minimum page threshold value; 4, if the memory fragmentation risk degree exceeds a set fragmentation threshold value, the Android device executes memory fragmentation; and averagely distributing the residual memory capacity to all the active processes. According to the invention, accurate allocation and efficient recovery of memory resources are realized.

The embodiment of the invention provides a memory processing method, electronic equipment and a readable storage medium, in the method, in a scene in which an application program and hardware equipment share a first physical memory, when the application program is switched to a background, the application program sends a first command to a memory processing device, the first command is used for indicating to release a first physical memory of the application; in response to the first command, the memory processing device releases the first physical memory. In the embodiment of the invention, when the application program is switched to the background and the first physical memory cannot be used temporarily, the application program can actively request to release the first physical memory, so that the available memory of the electronic equipment is increased.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

According to some embodiments, systems and methods are provided including a memory, a processing unit and program code to: create an event, the event including an item value for a given quantity of an item provided by each of a plurality of entities; receive an event target; extract an entity identifier from the event target for each entity from the event; generate one or more simulations based on a plurality of characteristic parameter constraints and the event target; generate a characteristic parameter value for each of the plurality of characteristic parameters via execution of a machine learning model trained with prior values of characteristic parameters for the plurality of entities; scale the generated characteristic parameter values to a common unit of measure; generate an output, including a quantity distribution of the given quantity to at least one of the plurality of entities. Numerous other aspects are provided.

The invention discloses a virtual machine memory processing method and device, a product, a virtualization server and a medium, and relates to the field of server virtualization. In the method, through a virtual input and output rear-end module arranged on a virtual machine monitor in a host and a virtual input and output front-end module on a virtual machine, it is ensured that the virtual input and output rear-end module can obtain information of a memory allocation event of direct memory access; secondly, after acquiring the information of the memory allocation event of the direct memory access, the virtual input / output rear-end module locks the address related to the memory allocation event, namely, the locked address meets the direct memory access requirement, and the memory of the virtual machine is dynamically locked, so that the memory utilization rate is improved, and the waste of resources is reduced; and only part of the memory of the virtual machine is locked, and only the locked memory part is migrated after the host is replaced, so that the amount of data to be migrated after the host is replaced is reduced.

The embodiment of the invention discloses a data caching and memory processing method, system, device, equipment, medium and program, and the data caching method comprises the following steps: receiving a data caching request; the data caching request comprises the size of an application space of to-be-cached data; the application space represents the space occupied by the memory applied by the to-be-cached data; comparing the size of the application space with the size of a first fixing block; the first fixed block is the largest idle fixed block in the main memory blocks of the memory pool; the memory pool is used for realizing data caching, and the fixed block is a preset storage space in the main memory block; the main memory block comprises a plurality of fixed blocks with different sizes; and when the size of the application space is larger than that of the first fixed block, searching for an available memory from a standby memory block of the memory pool.

The invention provides a memory database starting method, system and device and a medium, and belongs to the technical field of computers. The method comprises the following steps: detecting a current project scale and a performance index of an original server, and determining whether to trigger a memory processing mechanism; if a memory processing mechanism is triggered, selecting a memory server according to high-performance computing and expansibility requirements, accessing an original server by utilizing a hot plug technology, configuring a memory database and initializing a memory computing cluster; configuring a to-be-synchronized database table by utilizing a metadata management function, loading original data to a memory database through a full-amount synchronization and incremental updating mechanism, and starting real-time data synchronization; starting a memory computing cluster, automatically detecting a memory processing state on an original server when a service task is triggered, and routing a large quantity of data tasks meeting conditions to a memory server to execute parallel computing. According to the method, the memory can be dynamically started for data processing, the operation efficiency is improved, and the user experience is improved.

A processing-in-memory (PIM) device may include a plurality of memory banks configured to provide plural groups of weight data, a global buffer configured to provide plural sets of vector data, and a plurality of multiplication / accumulation (MAC) operators configured to perform MAC operations of the plural groups of weigh data and the plural sets of vector data. Each of the plurality of MAC operators includes a plurality of multiple operation circuits. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

Apparatuses, methods, and systems are disclosed for inter-UE coordination (“IUC”) scheme restriction during congestion. An apparatus (700) includes a memory (710) and a processor (705) coupled to the memory (710). The processor (705) is configured to cause the apparatus (700) to identify a configuration comprising a lookup table defining a restriction of one or more inter-CE coordination schemes between the apparatus (700) and a second apparatus (700) and transmit an inter-UE coordination report to the second apparatus (700) according to the identified configuration and based at least in part on a request for the inter-UE coordination report from the second apparatus (700) or a condition.

A processing system includes a first memory. The processing system is configured to obtain first data, where the first data is data to be written into the first memory; determine, based on first error distribution area information of at least one memory space included in the first memory, a first arrangement manner of a memory space occupied by a data symbol; determine the first data as M data symbols based on the first arrangement manner of the memory space occupied by the data symbol, where each of the M data symbols includes a plurality of data bits; perform first error correction code encoding on the M data symbols to obtain N first redundant symbols; and write the M data symbols and the N first redundant symbols into the first memory.

A storage array for centralized logging is provided. The storage array for centralized logging includes one or more servers and a near memory processing NMP module. The one or more servers are configured to host one or more allocation units allocated to a logical volume. The NMP module is configured for one or more allocation units, and the NMP module is configured to record and update a state of a respective allocation unit in a reserved area of the respective allocation unit. The state includes a virtual offset of the respective allocation unit within a virtual log and a range of valid data in the respective allocation unit, and the NMP module is configured to return the allocation unit state in response to a command from one of one or more client devices.

The concepts and technologies disclosed herein are directed to software runtime assisted co-processing acceleration with a memory hierarchy augmented with compute elements. An example system disclosed herein includes one or more switches and a plurality of hardware compute nodes connected via the one or more switches. Each hardware compute node of the plurality of hardware compute nodes includes an in-memory compute (IMC) element configured to perform in-memory processing operations on data, such as graph data. The system also includes a near-memory compute (NMC) element configured to perform near-memory processing operations on the data. The system also includes a far-memory compute (FMC) element configured to perform far-memory processing operations on the data.

Provided are computer program product, system, and method for mapping data for nodes in a first transform network to input nodes of near-memory processing units implementing a smaller transform network. A plurality of processing units, which are interconnected, receive input data for n input nodes for a second transform network to process at interlinked stages of nodes in the processing units. A mapping maps N input nodes for the first transform network to the n input nodes of the second transform network. N is greater than n and a plurality of the N input nodes of the first transform network map to one of the n input nodes of the second transform network. A transform manager uses the mapping to map the N input nodes to n input nodes and loads received input data for the n input nodes into the processing units to perform computations in the processing units.

Apparatuses, methods, and systems are disclosed for LCP procedure considering IUC schemes. An apparatus (600) includes a memory (610) and a processor (605) coupled to the memory (610). The processor (605) is configured to cause the apparatus (600) to determine a latency bound for transmission of a SL inter-UE coordination report via a MAC CE, maintain a report timer for transmitting the inter-UE coordination report via the MAC CE according to the determined latency bound, and transmit the inter-UE coordination information via the MAC CE based on the report timer.

Provided in the present application is a method for handling a CE in a memory. In an embodiment, the method is applied to a computing device, and comprises: acquiring information of corrected errors (CEs) generated in a memory; on the basis of the information of the CEs, determining a first numerical value, wherein the first numerical value indicates the frequency at which the CEs occur in the memory during the process of a computing device refreshing the memory according to a first memory refresh frequency; on the basis of the first numerical value, adjusting the first memory refresh frequency to a second memory refresh frequency, wherein the second memory refresh frequency is greater than the first memory refresh frequency; and refreshing the memory according to the second memory refresh frequency. Thus, when the frequency at which CEs occurs in a memory is relatively large, a memory refresh frequency can be increased, so as to reduce the probability of CEs frequently occurring in the memory.

Provided are a computer program product, system, and method for compiling an application having polynomial operations to produce directed acyclic graphs having commands to execute in a near memory processing device. An application is compiled including operations on a polynomial having coefficients, decomposed into a number of levels of coefficient elements, to generate hierarchical directed acyclic graphs (DAGs) having nodes indicating commands for execution by a hierarchy of hardware components in a near memory processing (NMP) device. The hierarchy of hardware components includes a plurality of enclaves of tiles. Each tile includes memory and a processing element to perform operations on the decomposed coefficients stored in the memory of the tile. Each of the hardware components includes a controller to process the commands in the DAG generated for the hardware components. The DAGs are provided to a hierarchical DAG tracker to generate commands for the NMP device.

In accordance with the described techniques for condensed coherence directory entries for processing in memory, a computing device includes a core that includes a cache, a memory that includes multiple banks, a coherence directory that includes a condensed entry indicating that data associated with a memory address and the multiple banks is not stored in the cache, and a cache coherence controller. The cache coherence controller receives a processing-in-memory command to the memory address and performs a single lookup in the coherence directory for the processing-in-memory command based on inclusion of the condensed entry in the coherence directory.

A memory device includes a plurality of memory banks, and a processing-in-memory (PIM) block accessible to the plurality of memory banks, wherein the PIM block comprises a control circuit configured to receive a plurality of operation instructions from a host and, in response to a predicated instruction indicating a predication operation among the plurality of operation instructions, instruct an arithmetic logic unit (ALU) to perform the predication operation, a predicate register file (PRF) configured to store therein a predicate value determined by the predication operation, and the ALU configured to perform an operation according to a command signal translated by the control circuit based on the predicate value from an operation instruction that depends on the predicate value among the plurality of operation instructions.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

Systems and techniques for isolation-based confidentiality are described. In one example, a processor is communicatively coupled to memory accessible by multiple applications. The processor requests a private memory region in the memory for data of a first application of the multiple applications. The processor causes the data of the first application to be stored in the private memory region without encryption (e.g., in an unencrypted format). The data in the private memory region is not accessible by the other applications of the processor or other processors. In this way, confidentiality is provided for sensitive data without the overhead required of traditional encryption techniques.

The invention relates to a storage processing method and device based on a capacitance-free DRAM (Dynamic Random Access Memory), and the method comprises the steps: preparing a corresponding writing transistor and a corresponding reading transistor through a preset oxide semiconductor and a silicon transistor; based on a preset heterogeneous integration strategy, vertically stacking the write transistor on the read transistor to establish a capacitance-free DRAM memory unit; the method comprises the following steps: establishing a heterogeneous integrated capacitance-free DRAM memory macro based on a pre-established storage unit peripheral circuit and a capacitance-free DRAM memory unit, and establishing a corresponding in-memory processing architecture according to the heterogeneous integrated capacitance-free DRAM memory macro and a pre-established convolution kernel logic circuit, so as to execute corresponding storage operation through the in-memory processing architecture. Therefore, the technical problems that in the prior art, a DRAM memory processing framework is high in process cost, incompatible in preparation process, high in circuit complexity, poor in memory processing speed and the like are solved.

An embodiment includes a network connected device comprising a transceiver configured to receive network traffic from the network, a memory coupled to the transceiver, a processor coupled to the memory and the transceiver, the processor configured to: decompose the network traffic into a plurality of data flows based on source information and destination information, store the plurality of data flows in a traffic map, each entry of the traffic map includes a data flow identification and traffic information of the data flow in an observation time window, determine a service type for each of the data flows using machine learning; and prioritize a first data flow over a second data flow in the plurality of data flows based on the service type.

Disclosed in some examples are methods, systems, devices, and architectures which provide for techniques for memory device and memory fabric redundancy within distributed memory systems. In some examples, two memory devices are paired and each stores a same set of data such that writes to the memory devices are duplicated and reads may be satisfied from either device. In some examples, a memory processing unit (MPU) may be incorporated into the memory architecture to support these paired memory devices. The MPU may be placed between the host and a multi-planed memory fabric which connects to multi-ported CXL memory devices. In some examples, the MPU may also enable the use of alternative fabric links. That is, if a memory fabric link between the MPU and a memory device is unavailable, an alternative link may be utilized to restore connectivity to a memory device.

In accordance with the described techniques for host accesses to processing-in-memory oriented data structures, a computing device includes a memory, a host processing unit, and multiple processing-in-memory units each configured to access one or more banks of the memory. The host processor receives an access request to access an element of a data structure stored in the memory. In particular, the access request includes input parameters indicating a processing-in-memory unit of the multiple processing-in-memory units by which the element is accessible, and an offset of the element relative to other elements of the data structure. The host processor generates a memory address based on the processing-in-memory unit and the offset, and the element of the data structure is accessed based on the memory address.

A system includes memory hardware including a memory and a processing-in-memory component. A system includes a host including at least one core. A system includes a memory controller including a scheduling system. The scheduling system transforms an all-bank processing-in-memory command into multiple masked processing-in-memory commands. The scheduling system also schedules the multiple masked processing-in-memory commands to the processing-in-memory component.