66 results about "In-Memory Processing" patented technology

A memory device includes a plurality of memory banks, and a processing-in-memory (PIM) block accessible to the plurality of memory banks, wherein the PIM block comprises a control circuit configured to receive a plurality of operation instructions from a host and, in response to a predicated instruction indicating a predication operation among the plurality of operation instructions, instruct an arithmetic logic unit (ALU) to perform the predication operation, a predicate register file (PRF) configured to store therein a predicate value determined by the predication operation, and the ALU configured to perform an operation according to a command signal translated by the control circuit based on the predicate value from an operation instruction that depends on the predicate value among the plurality of operation instructions.

Systems and techniques for isolation-based confidentiality are described. In one example, a processor is communicatively coupled to memory accessible by multiple applications. The processor requests a private memory region in the memory for data of a first application of the multiple applications. The processor causes the data of the first application to be stored in the private memory region without encryption (e.g., in an unencrypted format). The data in the private memory region is not accessible by the other applications of the processor or other processors. In this way, confidentiality is provided for sensitive data without the overhead required of traditional encryption techniques.

The application discloses a processor, a data processing method, a chip and an electronic device, and belongs to the electronic technical field. The processor comprises an exchange module, a processing module and a local memory, the processing module and the exchange module are connected with the local memory and an extended memory, and the processing module is connected with the exchange module. Wherein, the processing module sends an exchange instruction to the exchange module when determining that the first data meeting the condition is located in the extended memory. The exchange module reads the first data from the extended memory and the second data from the local memory based on the exchange instruction, writes the first data into the local memory, and writes the second data into the extended memory. By exchanging the data that may be accessed from the extended memory to the local memory, the subsequent processing module can read data from the local memory, and the data reading delay is reduced.

The embodiment of the invention provides a security defense method and device based on Hypervisor, and relates to the technical field of virtualization. The method comprises the steps of determining a memory processing type in response to a preset trigger operation; and calling an hvc command by calling a virtual machine monitor corresponding to the memory processing type so as to indicate a Hypervisor to execute a Hypervisor processing function corresponding to the hvc command. According to the embodiment of the invention, the distribution or release of the internal memory of the process is realized through the Hypervisor with higher authority, even if the kernel of the operating system is broken by a malicious application program, the integrity of a security mechanism of the operating system can still be ensured, and the effective defense of security threats of the operating system is realized.

A method and apparatus for processing-in-memory (PIM) are disclosed. A method of generating a PIM request for an in-memory operation includes receiving configuration information for generating a PIM request from a processor, obtaining information about a PIM request command from a command table, based on the configuration information, and generating a PIM request based on the information about a PIM request command.

Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

An apparatus includes a global memory and a systolic array. The global memory is configured to store and provide an input feature map (IFM) vector stream from an IFM tensor and a kernel vector stream from a kernel tensor. The systolic array is configured to receive the IFM vector stream and the kernel vector stream from the global memory. The systolic array is on-chip together with the global memory. The systolic array includes a plurality of processing elements (PEs) each having a plurality of vector units, each of the plurality of vector units being configured to perform a dot-product operation on at least one IFM vector of the IFM vector stream and at least one kernel vector of the kernel vector stream per unit clock cycle to generate a plurality of output feature maps (OFMs).

The application provides an electronic device starting method and an electronic device. The electronic device comprises a processor, a memory and a CPLD. The CPLD comprises a static storage module in which SPD information is stored. After the electronic device is powered on, the CPLD completes its own starting, sends a storage address of the SPD information to the processor and triggers the processor to start up. The processor reads the SPD information according to the storage address and initializes the memory according to the SPD information. The processor completes the starting of an operating system. The SPD information is stored in the static storage module of the existing CPLD, and an EEPROM does not need to be arranged for each memory, so that the number of EEPROMs in the electronic device can be reduced, thereby saving the hardware cost. Moreover, the SPD information in the static storage module of the CPLD can be directly modified without being removed and burned, so that the replacement process of the memory can be simplified and errors can be reduced.

A processor, an operation method and a storage device are provided. The processor is adapted to access a memory. The processor includes a vector register file and the storage device. The storage device is coupled to the vector register file. The storage device performs a striding operation on the memory. In a current iteration of the striding operation, the storage device reads a plurality of first data elements at a plurality of non-contiguous addresses in the memory and writes the first data elements into the vector register file, or the storage device reads a plurality of second data elements from the vector register file and writes the second data elements into the memory at the plurality of non-contiguous addresses in the current iteration of the striding operation.

Provided are a computer program product, system, and method for compiling an application having polynomial operations to produce directed acyclic graphs having commands to execute in a near memory processing device. An application is compiled including operations on a polynomial having coefficients, decomposed into a number of levels of coefficient elements, to generate hierarchical directed acyclic graphs (DAGs) having nodes indicating commands for execution by a hierarchy of hardware components in a near memory processing (NMP) device. The hierarchy of hardware components includes a plurality of enclaves of tiles. Each tile includes memory and a processing element to perform operations on the decomposed coefficients stored in the memory of the tile. Each of the hardware components includes a controller to process the commands in the DAG generated for the hardware components. The DAGs are provided to a hierarchical DAG tracker to generate commands for the NMP device.

There is provided a load balancer including a computing platform having processing hardware and a memory storing a software code. The processing hardware is configured to execute the software code to receive production data describing a media workflow, determine, using the production data, a priority status of the media workflow, identify production resources for processing the media workflow, and allocate, based on the priority status, one or more of the production resources to processing of the media workflow. In some implementations, the priority status is determined based on the type of content included in the media workflow. Moreover, in some implementations, the priority status is determined further based on a distribution schedule of a content feed corresponding to the media workflow.

According to examples, a system for generating and providing organization-bounded spaces for a virtual community of users may include a processor and a memory storing instructions. The processor, when executing the instructions, may cause the system to generate an organization-bounded space; analyze user information to associate a user with the organization-bounded space; enable the user to receive and publish a content item; and implement a security feature for communications associated with an organization-bounded space and / or its associated users. The processor may further determine recommend a group to the user and identify a user representative for the organization-bounded space.

Provided is a storage device, memory processor, and an operating method thereof. More specifically, provided is an operating method of a storage device including acquiring quality of service (QoS) information, obtaining a read request or write request for data in the NVM from a host, and allocating a logical-to-physical (L2P) slot of a plurality of L2P slots including L2P mapping information corresponding to the data to at least one namespace among a plurality of namespaces of a dynamic random-access memory (DRAM) based on the QoS information.

A recommendation system and method for accelerating inference are disclosed. The recommendation system comprises a memory processing unit for performing a feature interaction on an embedding vector whenever the embedding vector is looked up on an embedding table with respect to a sparse feature. Here, the feature interaction is performed by an inner product between the embedding vector at the lookup and an embedding vector used in a previous lookup.

A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.

The application provides a memory processing method, an electronic device and related apparatuses, and relates to the technical field of terminals. The method is applied to an electronic device, the electronic device comprises a first storage space and a second storage space, and the second storage space stores a plurality of application data of a first application. In the method, in the case that the first application is switched from the background to the foreground, n times of first operations are performed, the first operation comprises: writing a data set into a cache block applied from the first storage space, wherein the data set comprises at least one piece of application data in the plurality of application data, the size of the data set is less than or equal to the size of the cache block, and n is an integer greater than or equal to 3. In the first operation, the first size of the cache block in the i-th time is greater than or equal to the second size of the cache block in the (i-1)-th time, and i is 2-n. In this way, the bandwidth utilization can be improved based on the aggregated submission IO of at least one piece of data.

To achieve higher performance by reducing row contention, an approach is provided for implementing a hardware-software cooperative address mapping scheme that enables mapping of data elements that are accessed together in the same row of one bank or across the same row of different banks. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved in a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved in a single channel row of a channel. A memory controller utilizes ICFS and / or IBFS to efficiently store and access data elements in a memory, such as a processing-in-memory (PIM)-enabled memory.

Provided in embodiments of the present disclosure are a memory processing method and apparatus, a multi-host system, and an electronic device. The method comprises: in response to a memory application request sent by a host, allocating a first memory area to the host in a first memory device in a memory pool, wherein the memory application request comprises copy indication information, the copy indication information is used for indicating whether to create a copy, and the first memory area is a primary memory area of the host; and if the copy indication information indicates that a copy could be created, allocating a second memory area to the host in a second memory device in the memory pool, wherein the second memory area is a backup memory area of the host, and the backup memory area is used for data backup of the primary memory area. The impact of memory device failures is reduced.

An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

This invention discloses a virtual machine memory processing method, apparatus, product, virtualization server, and medium, relating to the field of server virtualization. In this method, a virtual input / output backend module set on the virtual machine monitor in the host and a virtual input / output frontend module on the virtual machine ensure that the virtual input / output backend module can obtain information about direct memory access memory allocation events. Secondly, after obtaining the information about direct memory access memory allocation events, the virtual input / output backend module locks the addresses involved in the memory allocation events, meaning the locked addresses satisfy the direct memory access requirements. This dynamic locking of virtual machine memory improves memory utilization and reduces resource waste. Furthermore, since only a portion of the virtual machine memory is locked, when the host is replaced, only the locked memory portion needs to be migrated, reducing the amount of data to be migrated after a host replacement.

The invention provides a memory processing method and device and a computer storage medium. The memory processing method comprises the steps of obtaining a read-write request; determining whether target data accessed by the read-write request is hot data or not; if yes, a hot data memory cache pool is used for completing the read-write request, and the hot data memory cache pool is located in a block device driving layer. By means of the mode, read access is completely completed in the memory cache pool of the driving layer, and a fast path which does not need to access physical storage equipment is formed. According to the path, the physical I / O operation is thoroughly eliminated, and the performance bottleneck caused by read delay and track seeking time in the prior art is solved.

The invention provides a processor suitable for multi-segment memory access and an operation method thereof. The multi-segment memory access can be realized. The processor comprises a vector register file and a loading device. When the loading device carries out multi-section loading on the memory, the loading device reads a plurality of data elements from a source section of the memory, and then writes the data elements into the vector register file in a single write cycle, so that the data elements are written into the same positions in different vector registers of the vector register file. When the loading device performs multi-section storage on the memory, the loading device reads a plurality of data elements (the data elements are data elements at the same position in different vector registers) from the vector register file in a single read cycle, and then writes the data elements into a target section of the memory.

The application relates to a heap memory analysis method and device, computer equipment, a chip and a chip module. The method comprises the following steps: in response to a heap memory processing instruction for a to-be-analyzed heap memory, determining the array identifier of a preset array corresponding to the to-be-analyzed heap memory according to the heap memory address corresponding to the heap memory processing instruction; updating the array information of the preset array according to the heap memory processing instruction and the array identifier, to obtain the updated array information of the preset array; and generating a memory analysis report corresponding to the to-be-analyzed heap memory based on the updated array information. The method can improve the analysis efficiency of the heap memory.

The invention relates to a memory processing method and device, electronic equipment, a storage medium and a program product. The method comprises the following steps: determining a first number of times that a to-be-processed physical page is currently referenced by a process; determining the to-be-processed physical page of which the first frequency is greater than a preset frequency threshold value as a target page; wherein the preset number of times threshold is determined based on the number of times that the reversely mapped physical page is referenced by the process and the duration of reversely mapping the physical page; and obtaining current state information of a memory, and storing the target page to a corresponding storage space based on the current state information. Through the method provided by the invention, excessive consumption of system resources caused by repeated reverse mapping of the target page can be reduced.

Methods and systems for hardware and software techniques for interleaving compute commands and input data write operations to a PiM module to optimize execution of in memory computations. A PiM compute module executes the interleaved commands to perform multiply and accumulate (MAC) operations using parameters read from a memory array and input data read from an input queue. A memory controller interleaves the commands and input data writes to the PIM module based on the duration of the MAC operations and / or a timing parameter for issuing write commands or for consuming data from the input queue. The memory controller can interleave different types of commands concurrent with interleaving the commands with the input data write operations. The interleaving operations are timed to maintain a threshold quantity of input data in the input queue to minimize (or prevent) data underflow or overflow during execution of the MAC operations.

A multiplexor (MUX) for a processing unit of memory is described herein. The MUX and a plurality of multiply-accumulate (MAC) units coupled to the MUX can receive a plurality of data values. The MUX can provide a first half of the plurality of data values to the plurality of MAC units during a first half of a duration of time and can provide a second half of the plurality of data values to the plurality of MAC units during a second half of the duration of time. The plurality of MAC units can perform a first plurality of multiplication operations utilizing the first half of the plurality of data values and can perform a second plurality of multiplication operations utilizing the second half of the plurality of data values.

Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.

This invention discloses an edge AI dialogue interaction adaptation and inference optimization method for children's smart hardware, specifically involving the field of edge AI dialogue interaction adaptation and inference optimization technology. The method includes acquiring the current round of child speech, corresponding text, user age information, historical interaction sequences, remaining memory, processor usage, remaining battery power, and network connectivity status at the edge computing terminal; performing child semantic normalization on the current round of child speech and corresponding text to extract sentence length, word difficulty, intent category, emotion category, and context depth to form a joint state value; mapping the child's age adaptation results, semantic carrying requirements, and edge terminal resource status together into an age semantic resource state graph; and performing local inference and out-of-bounds backoff after filtering and perturbing the target inference trajectory in this state graph.

A method of operating a memory device which is configured to communicate with a host device, and which includes a memory cell array and a processing-in-memory (PIM) chip, including loading activation data and weight data from the memory cell array, by the PIM chip; generating pruned activation data by performing a first pruning operation on the activation data, by the PIM chip; providing the pruned activation data to the host device, by the PIM chip; generating pruned weight data by performing a second pruning operation on the weight data, by the PIM chip; providing the pruned weight data to the host device, by the PIM chip; and storing output data corresponding to a neural network operation performed based on the pruned activation data and the pruned weight data, by the memory cell array.