115 results about "In-Memory Processing" patented technology

The invention provides a hybrid parallel and dynamic scheduling method of a hybrid expert model based on 3D near-memory processing. The method comprises the following steps: establishing a joint performance analysis model; performing off-line linear programming optimization expert distribution; performing Bayesian optimization on physical node mapping; performing online reasoning; carrying out online dynamic priority detection; and an expert pre-broadcast and communication-friendly lexical element distribution strategy with optimal efficiency is provided. According to the method, node balancing optimization is realized through offline linear programming, and the problem of load imbalance of 3D NMP calculation is remarkably improved; in combination with a Bayesian optimization mapping strategy of link balance, the communication speed-up ratio is increased, and NoC link congestion is reduced; a dynamic scheduling strategy adapts to dynamic changes of expert activation in real-time reasoning through calculation load prediction and a pre-broadcast mechanism. Through cooperation of the offline automatic hybrid parallel mapping algorithm and the online dynamic scheduling strategy, the calculation load and the communication overhead are effectively balanced, and the reasoning efficiency of the hybrid expert model MoE on the 3D near-memory processing architecture is remarkably improved.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

The invention discloses a virtual machine memory processing method and device, a product, a virtualization server and a medium, and relates to the field of server virtualization. In the method, through a virtual input and output rear-end module arranged on a virtual machine monitor in a host and a virtual input and output front-end module on a virtual machine, it is ensured that the virtual input and output rear-end module can obtain information of a memory allocation event of direct memory access; secondly, after acquiring the information of the memory allocation event of the direct memory access, the virtual input / output rear-end module locks the address related to the memory allocation event, namely, the locked address meets the direct memory access requirement, and the memory of the virtual machine is dynamically locked, so that the memory utilization rate is improved, and the waste of resources is reduced; and only part of the memory of the virtual machine is locked, and only the locked memory part is migrated after the host is replaced, so that the amount of data to be migrated after the host is replaced is reduced.

The invention provides a memory database starting method, system and device and a medium, and belongs to the technical field of computers. The method comprises the following steps: detecting a current project scale and a performance index of an original server, and determining whether to trigger a memory processing mechanism; if a memory processing mechanism is triggered, selecting a memory server according to high-performance computing and expansibility requirements, accessing an original server by utilizing a hot plug technology, configuring a memory database and initializing a memory computing cluster; configuring a to-be-synchronized database table by utilizing a metadata management function, loading original data to a memory database through a full-amount synchronization and incremental updating mechanism, and starting real-time data synchronization; starting a memory computing cluster, automatically detecting a memory processing state on an original server when a service task is triggered, and routing a large quantity of data tasks meeting conditions to a memory server to execute parallel computing. According to the method, the memory can be dynamically started for data processing, the operation efficiency is improved, and the user experience is improved.

The concepts and technologies disclosed herein are directed to software runtime assisted co-processing acceleration with a memory hierarchy augmented with compute elements. An example system disclosed herein includes one or more switches and a plurality of hardware compute nodes connected via the one or more switches. Each hardware compute node of the plurality of hardware compute nodes includes an in-memory compute (IMC) element configured to perform in-memory processing operations on data, such as graph data. The system also includes a near-memory compute (NMC) element configured to perform near-memory processing operations on the data. The system also includes a far-memory compute (FMC) element configured to perform far-memory processing operations on the data.

In accordance with the described techniques for condensed coherence directory entries for processing in memory, a computing device includes a core that includes a cache, a memory that includes multiple banks, a coherence directory that includes a condensed entry indicating that data associated with a memory address and the multiple banks is not stored in the cache, and a cache coherence controller. The cache coherence controller receives a processing-in-memory command to the memory address and performs a single lookup in the coherence directory for the processing-in-memory command based on inclusion of the condensed entry in the coherence directory.

A memory device includes a plurality of memory banks, and a processing-in-memory (PIM) block accessible to the plurality of memory banks, wherein the PIM block comprises a control circuit configured to receive a plurality of operation instructions from a host and, in response to a predicated instruction indicating a predication operation among the plurality of operation instructions, instruct an arithmetic logic unit (ALU) to perform the predication operation, a predicate register file (PRF) configured to store therein a predicate value determined by the predication operation, and the ALU configured to perform an operation according to a command signal translated by the control circuit based on the predicate value from an operation instruction that depends on the predicate value among the plurality of operation instructions.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

Systems and techniques for isolation-based confidentiality are described. In one example, a processor is communicatively coupled to memory accessible by multiple applications. The processor requests a private memory region in the memory for data of a first application of the multiple applications. The processor causes the data of the first application to be stored in the private memory region without encryption (e.g., in an unencrypted format). The data in the private memory region is not accessible by the other applications of the processor or other processors. In this way, confidentiality is provided for sensitive data without the overhead required of traditional encryption techniques.

The invention relates to a storage processing method and device based on a capacitance-free DRAM (Dynamic Random Access Memory), and the method comprises the steps: preparing a corresponding writing transistor and a corresponding reading transistor through a preset oxide semiconductor and a silicon transistor; based on a preset heterogeneous integration strategy, vertically stacking the write transistor on the read transistor to establish a capacitance-free DRAM memory unit; the method comprises the following steps: establishing a heterogeneous integrated capacitance-free DRAM memory macro based on a pre-established storage unit peripheral circuit and a capacitance-free DRAM memory unit, and establishing a corresponding in-memory processing architecture according to the heterogeneous integrated capacitance-free DRAM memory macro and a pre-established convolution kernel logic circuit, so as to execute corresponding storage operation through the in-memory processing architecture. Therefore, the technical problems that in the prior art, a DRAM memory processing framework is high in process cost, incompatible in preparation process, high in circuit complexity, poor in memory processing speed and the like are solved.

In accordance with the described techniques for host accesses to processing-in-memory oriented data structures, a computing device includes a memory, a host processing unit, and multiple processing-in-memory units each configured to access one or more banks of the memory. The host processor receives an access request to access an element of a data structure stored in the memory. In particular, the access request includes input parameters indicating a processing-in-memory unit of the multiple processing-in-memory units by which the element is accessible, and an offset of the element relative to other elements of the data structure. The host processor generates a memory address based on the processing-in-memory unit and the offset, and the element of the data structure is accessed based on the memory address.

A system includes memory hardware including a memory and a processing-in-memory component. A system includes a host including at least one core. A system includes a memory controller including a scheduling system. The scheduling system transforms an all-bank processing-in-memory command into multiple masked processing-in-memory commands. The scheduling system also schedules the multiple masked processing-in-memory commands to the processing-in-memory component.

The invention discloses a data processing system, method and equipment, a medium and a program product in the technical field of computers. In the invention, a cache coherence root port of a computing device is connected with a cache coherence sub-port of a memory processing device through a cache coherence protocol, so that the computing device is used for synchronizing a query matrix of a model processing task and a first result output in a key value matrix calculation stage to the memory processing device through the cache coherence protocol; meanwhile, the memory processing device can synchronize the second result to the computing device through the cache coherence protocol, so that rapid data transmission between the computing device and the memory processing device is realized, the memory space of the computing device is saved, the overhead of a host processor in the execution process of the model processing task is reduced, and the performance of the model processing task is improved. And the task processing efficiency of the hardware computing equipment can be improved to a certain extent.

Methods, systems, and apparatus, including computational instructions / programs encoded on non-transitory computer-readable media, are disclosed to implement collaborative controls for dynamic voltage & frequency scaling ("DVFS") using an integrated circuit comprising a System-on-Chip ("SoC") and a memory device coupled to the SoC. The system identifies user-experience criteria for generating an output of a machine-learning ("ML") model implemented at the integrated circuit and determines a performance target required to satisfy the user-experience criteria. The system computes a first target operating point of a processing-in-memory ("PiM") block inside the memory device and a second target operating point of the host core. The system performs computations at the PiM block using the target operating point established based on the control signals. The first and second target operating points achieve the best energy efficiency, while the PiM block and the host core collaboratively satisfy the user-experience criteria.

A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of compute cores. The second memory can be coupled to the plurality of processing regions. The control logic can configure data flow between compute cores of one or more of the processing regions and corresponding adjacent regions of the first memory. The control logic can also configure data flow between the second memory and the compute cores of one or more of the processing regions. The control logic can also configure data flow between compute cores within one or more respective ones of the processing regions. The control logic can also configure array data for storage memory of the MPU.

The invention discloses a high-performance operation and maintenance monitoring method for energy storage equipment. The method comprises four steps of data acquisition, data processing, data analysis and data display. Through full-memory processing, multi-task queue and transaction batch updating mechanisms, the event processing efficiency is remarkably improved, and the database load is reduced. The data acquisition supports millisecond-level frequency and breakpoint resume; the data processing generates a structured event based on protocol analysis; data analysis dynamically marks event states and updates the event states in batches; and data display is realized through real-time visual alarm of a webpage end. The method is suitable for a large-scale energy storage system, and efficient and stable operation and maintenance monitoring is achieved.

The application discloses a processor, a data processing method, a chip and an electronic device, and belongs to the electronic technical field. The processor comprises an exchange module, a processing module and a local memory, the processing module and the exchange module are connected with the local memory and an extended memory, and the processing module is connected with the exchange module. Wherein, the processing module sends an exchange instruction to the exchange module when determining that the first data meeting the condition is located in the extended memory. The exchange module reads the first data from the extended memory and the second data from the local memory based on the exchange instruction, writes the first data into the local memory, and writes the second data into the extended memory. By exchanging the data that may be accessed from the extended memory to the local memory, the subsequent processing module can read data from the local memory, and the data reading delay is reduced.

The embodiment of the invention provides a security defense method and device based on Hypervisor, and relates to the technical field of virtualization. The method comprises the steps of determining a memory processing type in response to a preset trigger operation; and calling an hvc command by calling a virtual machine monitor corresponding to the memory processing type so as to indicate a Hypervisor to execute a Hypervisor processing function corresponding to the hvc command. According to the embodiment of the invention, the distribution or release of the internal memory of the process is realized through the Hypervisor with higher authority, even if the kernel of the operating system is broken by a malicious application program, the integrity of a security mechanism of the operating system can still be ensured, and the effective defense of security threats of the operating system is realized.

Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.

Methods, systems, and media comprising; a host device configured to execute one or more applications; and a processing-in-memory (PIM) subsystem comprising one or more memory arrays and one or more integrated compute elements, wherein the integrated compute elements comprise internal storage that is accessible during execution of instructions by the PIM subsystem operating on data stored in the one or more memory arrays, wherein the host device is configured to send commands over a command interface to initiate storing data in the one or more memory arrays over a data interface, and wherein the host device is configured to send data for storage in the internal storage of the PIM subsystem over the command interface.

Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

A processing-in-memory (PIM) device includes first to Lth multiplication / accumulation (MAC) operators, first to Lth memory banks, and a plurality of data input / output (I / O) circuits. The first to Lth MAC operators include first to Lth left MAC operators and first to Lth right MAC operators. The plurality of data I / O circuits include left data I / O circuits and right data I / O circuits. A Uth MAC operator among the first to Lth MAC operators is configured to output one of the first to Mth MAC result data through a Uth left MAC operator among the first to Lth left MAC operators or a Uth right MAC operator among the first to Lth right MAC operators. The PIM device is configured to output the MAC result data outputted through the left MAC operators through the left data I / O circuits, and output the MAC result data outputted through the right MAC operators through the right data I / O circuits.

A method and apparatus for processing-in-memory (PIM) are disclosed. A method of generating a PIM request for an in-memory operation includes receiving configuration information for generating a PIM request from a processor, obtaining information about a PIM request command from a command table, based on the configuration information, and generating a PIM request based on the information about a PIM request command.

Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

An apparatus includes a global memory and a systolic array. The global memory is configured to store and provide an input feature map (IFM) vector stream from an IFM tensor and a kernel vector stream from a kernel tensor. The systolic array is configured to receive the IFM vector stream and the kernel vector stream from the global memory. The systolic array is on-chip together with the global memory. The systolic array includes a plurality of processing elements (PEs) each having a plurality of vector units, each of the plurality of vector units being configured to perform a dot-product operation on at least one IFM vector of the IFM vector stream and at least one kernel vector of the kernel vector stream per unit clock cycle to generate a plurality of output feature maps (OFMs).

An apparatus and method for creating less computationally intensive nodes for a neural network. An integrated circuit includes a host processor and multiple memory channels, each with multiple memory array banks. Each of the memory array banks includes components of a processing-in-memory (PIM) accelerator and a scatter and gather circuit used to dynamically perform quantization operations and dequantization operations that offload these operations from the host processor. The host processor executes a data model that represents a neural network. The memory array banks store a single copy of a particular data value in a single precision. Therefore, the memory array banks avoid storing replications of the same data value with different precisions to be used by a neural network node. The memory array banks dynamically perform quantization operations and dequantization operations on one or more of the weight values, input data values, and activation output values of the neural network.

The application provides an electronic device starting method and an electronic device. The electronic device comprises a processor, a memory and a CPLD. The CPLD comprises a static storage module in which SPD information is stored. After the electronic device is powered on, the CPLD completes its own starting, sends a storage address of the SPD information to the processor and triggers the processor to start up. The processor reads the SPD information according to the storage address and initializes the memory according to the SPD information. The processor completes the starting of an operating system. The SPD information is stored in the static storage module of the existing CPLD, and an EEPROM does not need to be arranged for each memory, so that the number of EEPROMs in the electronic device can be reduced, thereby saving the hardware cost. Moreover, the SPD information in the static storage module of the CPLD can be directly modified without being removed and burned, so that the replacement process of the memory can be simplified and errors can be reduced.

An example apparatus includes a processing in memory (PIM) capable device having an array of memory cells and sensing circuitry coupled to the array. The PIM capable includes a row address strobe (RAS) component selectably coupled to the array. The RAS component is configured to select, retrieve a data value from, and input a data value to a specific row in the array. The PIM capable device also includes a RAS manager selectably coupled to the RAS component. The RAS manager is configured to coordinate timing of a sequence of compute sub-operations performed using the RAS component. The apparatus also includes a source external to the PIM capable device. The RAS manager is configured to receive instructions from the source to control timing of performance of a compute operation using the sensing circuitry.

The application aims to provide an efficient memory allocation and recovery method for Android devices, and relates to the technical field of memory processing, which comprises the following steps: step 1: obtaining the running data of the Android device, calculating the memory state entropy based on the running data, and combining the priority matrix and the running data to calculate the memory fragmentation risk degree; step 2: calculating the memory allocation dynamic threshold according to the memory fragmentation risk degree, and calculating the adaptive memory compression rate; step 3: using the adaptive memory compression rate to compress the current unused memory data of the Android device until the number of pages of the active process is lower than the set minimum page threshold; step 4: if the memory fragmentation risk degree exceeds the set fragmentation consolidation threshold, the Android device performs memory fragmentation consolidation, and the remaining memory capacity is evenly allocated to all active processes. The application realizes accurate allocation and efficient recovery of memory resources.