158 results about "In-Memory Processing" patented technology

The invention provides a hybrid parallel and dynamic scheduling method of a hybrid expert model based on 3D near-memory processing. The method comprises the following steps: establishing a joint performance analysis model; performing off-line linear programming optimization expert distribution; performing Bayesian optimization on physical node mapping; performing online reasoning; carrying out online dynamic priority detection; and an expert pre-broadcast and communication-friendly lexical element distribution strategy with optimal efficiency is provided. According to the method, node balancing optimization is realized through offline linear programming, and the problem of load imbalance of 3D NMP calculation is remarkably improved; in combination with a Bayesian optimization mapping strategy of link balance, the communication speed-up ratio is increased, and NoC link congestion is reduced; a dynamic scheduling strategy adapts to dynamic changes of expert activation in real-time reasoning through calculation load prediction and a pre-broadcast mechanism. Through cooperation of the offline automatic hybrid parallel mapping algorithm and the online dynamic scheduling strategy, the calculation load and the communication overhead are effectively balanced, and the reasoning efficiency of the hybrid expert model MoE on the 3D near-memory processing architecture is remarkably improved.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

The invention discloses a virtual machine memory processing method and device, a product, a virtualization server and a medium, and relates to the field of server virtualization. In the method, through a virtual input and output rear-end module arranged on a virtual machine monitor in a host and a virtual input and output front-end module on a virtual machine, it is ensured that the virtual input and output rear-end module can obtain information of a memory allocation event of direct memory access; secondly, after acquiring the information of the memory allocation event of the direct memory access, the virtual input / output rear-end module locks the address related to the memory allocation event, namely, the locked address meets the direct memory access requirement, and the memory of the virtual machine is dynamically locked, so that the memory utilization rate is improved, and the waste of resources is reduced; and only part of the memory of the virtual machine is locked, and only the locked memory part is migrated after the host is replaced, so that the amount of data to be migrated after the host is replaced is reduced.

The embodiment of the invention discloses a data caching and memory processing method, system, device, equipment, medium and program, and the data caching method comprises the following steps: receiving a data caching request; the data caching request comprises the size of an application space of to-be-cached data; the application space represents the space occupied by the memory applied by the to-be-cached data; comparing the size of the application space with the size of a first fixing block; the first fixed block is the largest idle fixed block in the main memory blocks of the memory pool; the memory pool is used for realizing data caching, and the fixed block is a preset storage space in the main memory block; the main memory block comprises a plurality of fixed blocks with different sizes; and when the size of the application space is larger than that of the first fixed block, searching for an available memory from a standby memory block of the memory pool.

The invention provides a memory database starting method, system and device and a medium, and belongs to the technical field of computers. The method comprises the following steps: detecting a current project scale and a performance index of an original server, and determining whether to trigger a memory processing mechanism; if a memory processing mechanism is triggered, selecting a memory server according to high-performance computing and expansibility requirements, accessing an original server by utilizing a hot plug technology, configuring a memory database and initializing a memory computing cluster; configuring a to-be-synchronized database table by utilizing a metadata management function, loading original data to a memory database through a full-amount synchronization and incremental updating mechanism, and starting real-time data synchronization; starting a memory computing cluster, automatically detecting a memory processing state on an original server when a service task is triggered, and routing a large quantity of data tasks meeting conditions to a memory server to execute parallel computing. According to the method, the memory can be dynamically started for data processing, the operation efficiency is improved, and the user experience is improved.

A processing-in-memory (PIM) device may include a plurality of memory banks configured to provide plural groups of weight data, a global buffer configured to provide plural sets of vector data, and a plurality of multiplication / accumulation (MAC) operators configured to perform MAC operations of the plural groups of weigh data and the plural sets of vector data. Each of the plurality of MAC operators includes a plurality of multiple operation circuits. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

The concepts and technologies disclosed herein are directed to software runtime assisted co-processing acceleration with a memory hierarchy augmented with compute elements. An example system disclosed herein includes one or more switches and a plurality of hardware compute nodes connected via the one or more switches. Each hardware compute node of the plurality of hardware compute nodes includes an in-memory compute (IMC) element configured to perform in-memory processing operations on data, such as graph data. The system also includes a near-memory compute (NMC) element configured to perform near-memory processing operations on the data. The system also includes a far-memory compute (FMC) element configured to perform far-memory processing operations on the data.

Provided are computer program product, system, and method for mapping data for nodes in a first transform network to input nodes of near-memory processing units implementing a smaller transform network. A plurality of processing units, which are interconnected, receive input data for n input nodes for a second transform network to process at interlinked stages of nodes in the processing units. A mapping maps N input nodes for the first transform network to the n input nodes of the second transform network. N is greater than n and a plurality of the N input nodes of the first transform network map to one of the n input nodes of the second transform network. A transform manager uses the mapping to map the N input nodes to n input nodes and loads received input data for the n input nodes into the processing units to perform computations in the processing units.

Provided in the present application is a method for handling a CE in a memory. In an embodiment, the method is applied to a computing device, and comprises: acquiring information of corrected errors (CEs) generated in a memory; on the basis of the information of the CEs, determining a first numerical value, wherein the first numerical value indicates the frequency at which the CEs occur in the memory during the process of a computing device refreshing the memory according to a first memory refresh frequency; on the basis of the first numerical value, adjusting the first memory refresh frequency to a second memory refresh frequency, wherein the second memory refresh frequency is greater than the first memory refresh frequency; and refreshing the memory according to the second memory refresh frequency. Thus, when the frequency at which CEs occurs in a memory is relatively large, a memory refresh frequency can be increased, so as to reduce the probability of CEs frequently occurring in the memory.

Provided are a computer program product, system, and method for compiling an application having polynomial operations to produce directed acyclic graphs having commands to execute in a near memory processing device. An application is compiled including operations on a polynomial having coefficients, decomposed into a number of levels of coefficient elements, to generate hierarchical directed acyclic graphs (DAGs) having nodes indicating commands for execution by a hierarchy of hardware components in a near memory processing (NMP) device. The hierarchy of hardware components includes a plurality of enclaves of tiles. Each tile includes memory and a processing element to perform operations on the decomposed coefficients stored in the memory of the tile. Each of the hardware components includes a controller to process the commands in the DAG generated for the hardware components. The DAGs are provided to a hierarchical DAG tracker to generate commands for the NMP device.

In accordance with the described techniques for condensed coherence directory entries for processing in memory, a computing device includes a core that includes a cache, a memory that includes multiple banks, a coherence directory that includes a condensed entry indicating that data associated with a memory address and the multiple banks is not stored in the cache, and a cache coherence controller. The cache coherence controller receives a processing-in-memory command to the memory address and performs a single lookup in the coherence directory for the processing-in-memory command based on inclusion of the condensed entry in the coherence directory.

A memory device includes a plurality of memory banks, and a processing-in-memory (PIM) block accessible to the plurality of memory banks, wherein the PIM block comprises a control circuit configured to receive a plurality of operation instructions from a host and, in response to a predicated instruction indicating a predication operation among the plurality of operation instructions, instruct an arithmetic logic unit (ALU) to perform the predication operation, a predicate register file (PRF) configured to store therein a predicate value determined by the predication operation, and the ALU configured to perform an operation according to a command signal translated by the control circuit based on the predicate value from an operation instruction that depends on the predicate value among the plurality of operation instructions.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

Systems and techniques for isolation-based confidentiality are described. In one example, a processor is communicatively coupled to memory accessible by multiple applications. The processor requests a private memory region in the memory for data of a first application of the multiple applications. The processor causes the data of the first application to be stored in the private memory region without encryption (e.g., in an unencrypted format). The data in the private memory region is not accessible by the other applications of the processor or other processors. In this way, confidentiality is provided for sensitive data without the overhead required of traditional encryption techniques.

The invention relates to a storage processing method and device based on a capacitance-free DRAM (Dynamic Random Access Memory), and the method comprises the steps: preparing a corresponding writing transistor and a corresponding reading transistor through a preset oxide semiconductor and a silicon transistor; based on a preset heterogeneous integration strategy, vertically stacking the write transistor on the read transistor to establish a capacitance-free DRAM memory unit; the method comprises the following steps: establishing a heterogeneous integrated capacitance-free DRAM memory macro based on a pre-established storage unit peripheral circuit and a capacitance-free DRAM memory unit, and establishing a corresponding in-memory processing architecture according to the heterogeneous integrated capacitance-free DRAM memory macro and a pre-established convolution kernel logic circuit, so as to execute corresponding storage operation through the in-memory processing architecture. Therefore, the technical problems that in the prior art, a DRAM memory processing framework is high in process cost, incompatible in preparation process, high in circuit complexity, poor in memory processing speed and the like are solved.

In accordance with the described techniques for host accesses to processing-in-memory oriented data structures, a computing device includes a memory, a host processing unit, and multiple processing-in-memory units each configured to access one or more banks of the memory. The host processor receives an access request to access an element of a data structure stored in the memory. In particular, the access request includes input parameters indicating a processing-in-memory unit of the multiple processing-in-memory units by which the element is accessible, and an offset of the element relative to other elements of the data structure. The host processor generates a memory address based on the processing-in-memory unit and the offset, and the element of the data structure is accessed based on the memory address.

A system includes memory hardware including a memory and a processing-in-memory component. A system includes a host including at least one core. A system includes a memory controller including a scheduling system. The scheduling system transforms an all-bank processing-in-memory command into multiple masked processing-in-memory commands. The scheduling system also schedules the multiple masked processing-in-memory commands to the processing-in-memory component.

The invention belongs to the technical field of semiconductors, and particularly relates to a two-channel memory addressing and bus system based on 3D stacking, which comprises at least one intelligent memory processing unit, and the intelligent memory processing unit comprises a DRAM (Dynamic Random Access Memory) storage layer and a logic calculation layer of 3D stacking; a memory in the intelligent memory processing unit is divided into two independent memory channels, each memory channel comprises a plurality of calculation engine groups, each calculation engine group comprises a plurality of calculation engine blocks, and each calculation engine block is correspondingly connected with one DRAM storage unit, one instruction scheduling engine and one memory controller. The dual-channel design is suitable for high-bandwidth and low-delay application scenes such as high-performance calculation, real-time data analysis and image processing.

The invention discloses a data processing system, method and equipment, a medium and a program product in the technical field of computers. In the invention, a cache coherence root port of a computing device is connected with a cache coherence sub-port of a memory processing device through a cache coherence protocol, so that the computing device is used for synchronizing a query matrix of a model processing task and a first result output in a key value matrix calculation stage to the memory processing device through the cache coherence protocol; meanwhile, the memory processing device can synchronize the second result to the computing device through the cache coherence protocol, so that rapid data transmission between the computing device and the memory processing device is realized, the memory space of the computing device is saved, the overhead of a host processor in the execution process of the model processing task is reduced, and the performance of the model processing task is improved. And the task processing efficiency of the hardware computing equipment can be improved to a certain extent.

Methods, systems, and apparatus, including computational instructions / programs encoded on non-transitory computer-readable media, are disclosed to implement collaborative controls for dynamic voltage & frequency scaling ("DVFS") using an integrated circuit comprising a System-on-Chip ("SoC") and a memory device coupled to the SoC. The system identifies user-experience criteria for generating an output of a machine-learning ("ML") model implemented at the integrated circuit and determines a performance target required to satisfy the user-experience criteria. The system computes a first target operating point of a processing-in-memory ("PiM") block inside the memory device and a second target operating point of the host core. The system performs computations at the PiM block using the target operating point established based on the control signals. The first and second target operating points achieve the best energy efficiency, while the PiM block and the host core collaboratively satisfy the user-experience criteria.

A memory system includes an external memory device and a first memory processing unit of a main memory device. The external memory device and a host may be disposed on different boards, and the external memory device may transfer compressed data to the host in response to a swap-in request from the host. The first memory processing unit and the host may be disposed on the same board. The first memory processing unit may load the compressed data, decompress the compressed data to obtain decompressed data, and store the decompressed data in a main memory of the main memory device.

A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of compute cores. The second memory can be coupled to the plurality of processing regions. The control logic can configure data flow between compute cores of one or more of the processing regions and corresponding adjacent regions of the first memory. The control logic can also configure data flow between the second memory and the compute cores of one or more of the processing regions. The control logic can also configure data flow between compute cores within one or more respective ones of the processing regions. The control logic can also configure array data for storage memory of the MPU.

The invention discloses a high-performance operation and maintenance monitoring method for energy storage equipment. The method comprises four steps of data acquisition, data processing, data analysis and data display. Through full-memory processing, multi-task queue and transaction batch updating mechanisms, the event processing efficiency is remarkably improved, and the database load is reduced. The data acquisition supports millisecond-level frequency and breakpoint resume; the data processing generates a structured event based on protocol analysis; data analysis dynamically marks event states and updates the event states in batches; and data display is realized through real-time visual alarm of a webpage end. The method is suitable for a large-scale energy storage system, and efficient and stable operation and maintenance monitoring is achieved.

The application discloses a processor, a data processing method, a chip and an electronic device, and belongs to the electronic technical field. The processor comprises an exchange module, a processing module and a local memory, the processing module and the exchange module are connected with the local memory and an extended memory, and the processing module is connected with the exchange module. Wherein, the processing module sends an exchange instruction to the exchange module when determining that the first data meeting the condition is located in the extended memory. The exchange module reads the first data from the extended memory and the second data from the local memory based on the exchange instruction, writes the first data into the local memory, and writes the second data into the extended memory. By exchanging the data that may be accessed from the extended memory to the local memory, the subsequent processing module can read data from the local memory, and the data reading delay is reduced.

Provided are a computer program product, system, and method for compiling an application having polynomial operations to produce directed acyclic graphs having commands to execute in a near memory processing device. An application is compiled including operations on a polynomial having coefficients, decomposed into a number of levels of coefficient elements, to generate hierarchical directed acyclic graphs (DAGs) having nodes indicating commands for execution by a hierarchy of hardware components in a near memory processing (NMP) device. The hierarchy of hardware components includes a plurality of enclaves of tiles. Each tile includes memory and a processing element to perform operations on the decomposed coefficients stored in the memory of the tile. Each of the hardware components includes a controller to process the commands in the DAG generated for the hardware components. The DAGs are provided to a hierarchical DAG tracker to generate commands for the NMP device.

The embodiment of the invention provides a security defense method and device based on Hypervisor, and relates to the technical field of virtualization. The method comprises the steps of determining a memory processing type in response to a preset trigger operation; and calling an hvc command by calling a virtual machine monitor corresponding to the memory processing type so as to indicate a Hypervisor to execute a Hypervisor processing function corresponding to the hvc command. According to the embodiment of the invention, the distribution or release of the internal memory of the process is realized through the Hypervisor with higher authority, even if the kernel of the operating system is broken by a malicious application program, the integrity of a security mechanism of the operating system can still be ensured, and the effective defense of security threats of the operating system is realized.

A method, system, and apparatus comprising an operation instruction / program encoded on a non-transient computer-readable medium are disclosed to reduce state transition latency by determining a target idle mode type. The system determines a first sequence of mode transitions. Each mode transition in the first sequence is a transition of a memory device from an execution mode to an idle mode of a memory device. Before the occurrence of each mode transition in the first sequence, the system determines an idle mode type among a plurality of mode types based on a dynamically updated energy model. The system repeatedly generates and pre-programs a first set of control signals based on the idle mode type corresponding to each mode transition in the first sequence, and based on the first set of control signals, the system repeatedly triggers the occurrence of each mode transition in the first sequence. Each triggered occurrence causes the memory device to transition to the corresponding idle mode type.

Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.

A processing-in-memory (PIM) device includes processing elements (PEs), memory banks, control logic, and a command decoder. Each of the PEs includes a selection circuit configured to select a path from among a transmission path of memory data, a transmission path of PIM data for a multiply-accumulate (MAC) operation, and a transmission path of an instruction for an internal processor. The memory banks are configured to store data corresponding to the PEs. The control logic is configured to generate a selection signal configured to cause the selection circuit to select the path to a memory bank among the memory banks. The command decoder is configured to decode a memory command for the memory bank and the control logic.