22 results about "Boolean function" patented technology

The invention discloses a fault tree Boolean function equivalent mapping method based on an untrained neural network, and relates to the field of fault tree analysis. In order to solve the problems that in the prior art, a Boolean function mapping structure is not beneficial to parallel expansion, the calculation efficiency is limited, and the Boolean function mapping structure is difficult to efficiently realize on high-parallel platforms such as a GPU, the invention provides a method for generating topological structure data by analyzing a fault tree model; the basic events, the intermediate events and the top events are mapped into neurons of an input layer, a hidden layer and an output layer respectively, a feedforward network with fixed weight and bias is constructed, and a logic activation function is defined in nodes to realize Boolean logic propagation. The input layer receives a basic event state vector, outputs a top event result through forward propagation, and can realize large-scale Boolean function mapping on a parallel platform through batch input matrixes. The method is suitable for reliability analysis, minimum cut set simplification, top event probability calculation, parallelization fault tree solving and the like of a large-scale complex system.

The invention relates to a Boolean function calculation method and device based on fully homomorphic encryption and electronic equipment, and the method comprises the steps: carrying out the format conversion of each received first type of ciphertext based on a target conversion format, and obtaining at least one second type of ciphertext; constructing a multi-layer cascaded CMUX circuit, and based on a preset logic rule, controlling the multi-layer cascaded CMUX circuit to dynamically select pre-encrypted truth table data by taking the second type ciphertext as a control signal to obtain at least one third type ciphertext; and extracting the third type ciphertext coefficient to obtain at least one fourth type ciphertext, and performing blind rotation operation reconstruction on the fourth type ciphertext to obtain at least one encrypted data. Therefore, the problems of low function calculation efficiency, poor expandability and limited calculation precision in the prior art are solved, the resource utilization rate and the parallel processing capability of fully homomorphic encryption in ciphertext calculation are remarkably improved, and meanwhile, the calculation precision and the safety of encrypted data are ensured.

The embodiment of the application discloses a decoding logic derivation method, a failed storage particle positioning method and related equipment, comprising: collecting all first error physical addresses generated by testing a same failed storage particle in a first physical slot to form a first error physical address set; collecting all second error physical addresses generated by testing the same failed storage particle in a second physical slot to form a second error physical address set; searching the first error physical address set and the second error physical address set to find k address bits, or a logical combination thereof, which is always a same value in binary logic values of all the first error physical addresses and is always an opposite value of the same value in binary logic values of all the second error physical addresses; and generating a Boolean function of the k address bits or the logical combination thereof as decoding logic. The application can automatically restore hidden physical address decoding logic and realize automatic, accurate and efficient positioning of the physical position of the failed storage particle.

The invention provides a self-anti-S box construction method and system based on m-sequence generation and logic optimization, and belongs to the technical field of cryptography and hardware security. The method comprises the following steps: firstly, constructing an n-level linear feedback shift register according to a set S box number n and a primitive polynomial, generating an m sequence in a non-all-zero initial state, and adding an all-zero state at the tail; a self-reverse S box lookup table is constructed through a symmetric mapping strategy, so that the ith element in the sequence and the element at the symmetric position form mapping, and the same S box is used for encryption and decryption. Thirdly, the lookup table serves as a Boolean function truth table, is simplified into a simplest expression through a logic minimization algorithm and is decomposed into a layered logic circuit; during actual processing, N data blocks are converted into a bit plane format from block type storage, then parallel operation is carried out through a hierarchical circuit, and finally a result is transposed back to block type storage. According to the method, the same S box hardware module can be reused in the encryption and decryption process, and hardware resources are remarkably saved.

The embodiment of the invention discloses a decoding logic derivation method, a failure storage particle positioning method and related equipment, and the method comprises the steps: collecting all first error physical addresses generated by testing the same failure storage particle in a first physical slot, and forming a first error physical address set; collecting all second error physical addresses generated by testing the same invalid storage particle in the second physical slot to form a second error physical address set; the first error physical address set and the second error physical address set are searched, k address bits are found, the binary logic values of the k address bits or the logic combination of the k address bits at all the first error physical addresses are constantly the same value, and the binary logic values of the k address bits or the logic combination of the k address bits at all the second error physical addresses are constantly the inverse value of the same value; and generating a Boolean function of the k address bits or the logical combination thereof as decoding logic. According to the method, hidden physical address decoding logic can be automatically restored, and automatic, accurate and efficient positioning of the physical position of the failure storage particle is realized.

This invention discloses a post-mapping optimization method for RSFQ circuits based on path balancing, comprising: parsing the topological connection relationships of nodes in the netlist and presetting the number of iterations; constructing candidate supergates and calculating P-class truth tables, classifying and storing them after P-class transformations, with each P-class truth table storing only the candidate supergate with the fewest JJs, forming a supergate library; perturbing the node hierarchy of the netlist, randomly assigning logic levels, and inserting DFFs; traversing the netlist in reverse to extract fan-out free cones, calculating Boolean function truth tables and performing P-class transformations, matching equivalent structures, and if the number of JJs in the library is smaller, performing an inverse P-class transformation and replacing them in the netlist; performing retiming optimization on the netlist, deleting D flip-flops and continuing iterations or outputting the final netlist. This method has significant advantages in reducing the number of JJs, reducing DFF overhead, and improving the optimization space and efficiency of the mapped RSFQ circuit netlist.

The invention relates to an electronic computing device for generating Boolean functions. The device comprises a conductive module comprising one or more first electrodes, to allow the application of electrical input signals to the conductive module, and one or more second electrodes, to make available electrical output signals from the conductive module. The device comprises one or more input terminals, each of which is selectively connectible to one of said one or more first electrodes for applying electrical input signals to said first electrodes during a step of processing of the device, and one or more output terminals, each of which is selectively connectible to one of said second electrodes to make electrical output signals available on said second electrodes during the step of processing.

The invention discloses a method for generating a non-periodic complementary sequence set signal, and belongs to the technical field of communication systems. The method comprises the following steps: setting variables, basic parameters m, b and q and permutation; the replacement is used for rearranging indexes of the variables; defining a residual class ring and an extended Boolean function; the residual class rings are used for defining the value range of the variables and expanding the output space of the Boolean function; the Boolean function is expanded as mapping of an output space and is used for constructing diversity and complementarity of the sequence; constructing an extended Boolean function set; mapping the function into a q-element sequence; and intercepting the sequence and obtaining a complementary sequence set, and outputting the complementary sequence set. According to the method, the basic parameters are set, the parameters are flexibly selected under the condition that basic constraints such as division are met, the parameters of the sequence set are allowed to be customized according to actual requirements, and therefore the inherent limitation of an existing method on parameter selection is improved.

The application discloses a kind of method for realizing distributed quantum amplitude amplification and related equipment, method includes: the initial success probability of quantum state is quantified based on target unitary operator, and configuration unitary operator is obtained from target unitary operator based on division parameter;Based on division parameter, Boolean function is split into the subfunction of preset quantity and sequentially distributed to each quantum node;Based on configuration unitary operator, the probability upper limit value of each quantum node is quantified using amplitude estimation;According to probability upper limit value, iteration number is obtained, and according to initial success probability, iteration upper limit is obtained;Based on iteration number, the measurement string corresponding to quantum node is iteratively output by quantum amplitude amplification algorithm, and then target string is verified and determined;Quantum operation result is obtained by summarizing the target string corresponding to all quantum nodes.The application can effectively avoid the dependence of existing distributed quantum computation on quantum communication means such as quantum teleportation, and can be widely applied in the field of data processing.

Apparatus and method for implementing an Artificial Neural Network (ANN) which eliminates the need for backpropagation during training. The ANN uses integer gate logic (IGL) nodes arranged into input, output and hidden layers. Each node has multiple inputs and a single output, and uses a non-differentiable linear logic output (LLO) activation function to emulate Boolean logic functions (including XOR), near-Boolean functions, and unknown functions, based on integer-based parameters. A chain isolation optimization process is used to select and isolate each node during training to assess the impact of the different weight parameters on the output. Enhanced error functions, random node selection and pruning techniques can be used during training. The ANN can be used across multiple domains including image processing, RF signal analysis and natural language processing (LLMs). Smaller parameter counts, faster inference times, and greater processor utilization rates have been empirically demonstrated as compared to existing models.

The invention discloses an information security encryption method, system and device, and relates to the technical field of cryptography and information security, and the method comprises the following steps: constructing a generalized Boolean function; with minimization of a golf norm of a generalized Boolean function as an optimization target, constructing an optimization model constrained by multiple cryptographic properties; on the basis of the optimization model, an optimization algorithm is adopted to iteratively update function parameters, and an optimization function meeting all cryptographic property constraints is output; generating a session key based on the linear term coefficient matrix and the nonlinear term index set of the optimization function in combination with an initial key input by a user; plaintexts are grouped, nonlinear confusion is carried out by using an optimization function and a session key, and a ciphertext is generated; calculating a golf norm value of the optimization function, integeting the golf norm value, and adding the integeted golf norm value as a check bit to the ciphertext to complete encryption; according to the method, the characteristics of the data can be more accurately captured, the password cracking difficulty of an attacker is increased, and more powerful and reliable guarantee is provided for information security.

Machine-leaming-aided logic synthesis using do-not-care-based backpropagation, including constructing a neural network (NN) model based on a functional specification of a circuit design, training the NN model to perform a function of the circuit design, where nodes of the neural network perform a first Boolean function (e.g., AND), and where the training comprises do-not-care-based backpropagating, which may include explicitly computing target functions at fanins of the nodes. The NN may be converted to a two-input graph having nodes that represent a second Boolean function (e.g., AND). The function of the circuit design may include a multiplier function, and the graph may include an AND-inverter graph (AIG). A Boolean patch may be constructed to correct an error in the graph.

This invention relates to the field of cryptography and discloses a lightweight stream cipher generation method and system. It involves setting up three shift registers A, B, and C. A and B are linear feedback shift registers, while C is a non-linear feedback shift register. A and B are clocked by C. Two different sets of taps are selected from shift register C, and their Hamming weights W1 and W2 are calculated respectively. Shift registers A and B are then clocked by shifting by W1 and W2 times respectively. Several taps are selected from shift registers A and B as inputs to a non-linear Boolean function H, and a key sequence is output. The plaintext sequence is encrypted using the key sequence to obtain the ciphertext sequence. The method enhances the security of the algorithm by introducing Hamming weight clocking of other shift registers only and by utilizing feedforward Boolean function inputs. The design is simple, and the algorithm has high security.

This application provides a device sensing method and apparatus, offering various Gray complement pairs (GCPs) of different lengths to increase GCP capacity and meet the needs of simultaneous sensing by multiple devices. The method includes: a sensing device transmitting a sensing signal, receiving the echo signal of the sensing signal, and processing the echo signal. The sensing signal is generated based on a GCP of length N, where N is greater than or equal to 32. When N equals 32, 64, 128, 256, 512, or 1024, the GCP can be generated by a generalized Boolean function mapping. When N equals 160, 320, 640, or 832, the GCP is the direct product of a first GCP and a second GCP, where the length of the first GCP is N1, the length of the second GCP is N2, and N1 × N2 = N. The first GCP is generated through a generalized Boolean function mapping; the second GCP is any of the following: x1 = 1, 1, -1, 1, -1, 1, -1, -1, 1, 1; y1 = 1, 1, -1, 1, 1, 1, 1, 1, -1, -1; or x2 = 1, 1, 1, 1, 1, -1, 1, -1, -1, 1; y2 = 1, 1, -1, -1, 1, 1, 1, -1, 1, -1, 1, -1.

The obfuscation circuit relies on tamper-resistant non-volatile memory that encodes a trusted Boolean function. The Boolean function is used to implement several operations related to circuit obfuscation, including obfuscation of logic circuits, obfuscation of operand data, and release of IP blocks. The tamper-resistant non-volatile memory is part of a trusted integrated circuit structure, i.e., an integrated circuit structure manufactured by a trusted foundry, that is separate from another integrated circuit structure that contains various operational logic circuits of the design and is manufactured by an untrusted foundry. The Boolean function is encoded based on a look-up table implemented as a cascaded multiplexer circuit. Multiple obfuscation functions can be encoded this way. The obfuscation functions can be reprogrammed using a protocol that relies on a symmetric key, one of which is stored in the tamper-resistant non-volatile memory.

The invention discloses a neural network method with an architecture-level backdoor based on neural architecture search (NAS). According to the method, under the condition that a backdoor sample does not need to be introduced, a parameter-free sub-detector is embedded in an NAS search space, a cross-layer interleaving path and a nonlinear gating mechanism are constructed, and a search loss function with a backdoor path reward and a mistaken killing punishment is combined, so that a controller is guided to automatically select and retain a structure embedded backdoor path. The generated backdoor logic is solidified in the network architecture in the form of a deterministic Boolean function, and stable triggering is still kept even after retraining. The method has high flexibility in logic design, and can adapt to various implementation scenes such as centralized training or federated learning. Compared with a traditional method which depends on data poisoning and manually constructs an architecture backdoor, the method has the advantages of being high in concealment, high in defending capability, diversified in architecture and the like, can adapt to various task scenes, and remarkably improves the flexibility and durability of backdoor injection.

The application discloses an iterative function perception sampling method and system for a logistic regression, and the method comprises the following steps: based on the input / output (IO) history samples of an oracle, the IO history samples are encoded by a pre-built function extraction model (FEM) to obtain function embedding vectors; sampling is performed by a pre-built sampling distribution model (SDM) to output a sampling distribution on an input space; a plurality of candidate inputs are generated from the input space according to the sampling distribution to form a candidate set, the candidate set is de-redundant screened by a pre-built budget subset selector (BSS) to select a plurality of input samples; and an external or built-in logistic regression algorithm is called for the selected input samples to update the IO history samples. The method improves the logistic regression precision and sampling efficiency under the condition that the oracle input and output are used to query and access a target Boolean function.

The invention discloses a memristor array optimization method. The method comprises the following steps: obtaining a Boolean function to be calculated and a memristor array to be optimized; processing the Boolean function to be calculated by using a genetic algorithm to obtain an optimal binary decision diagram; and according to the optimal binary decision diagram, the memristor array is optimized, and an optimal memristor array is obtained. The method is low in calculation energy consumption and low in calculation cost.

The invention relates to the technical field of data privacy protection, in particular to an industrial data multi-party sharing method based on a differential privacy technology, and aims to solve the problems that in the prior art, a binary counting function and a continuous approximation form thereof cannot be constructed, accurate modeling and privacy protection support of a stable structure in a graph cannot be realized, and data privacy protection cannot be realized. The problems that a trapezoidal function cannot be combined to enhance model stability, parameter control and pruning strategy optimization performance cannot be fused, and privacy security and result reliability cannot be guaranteed are solved. According to the method, accurate modeling and privacy protection support of a stable structure in a graph are realized by constructing a binary counting function and a continuous approximation form thereof, the calculation efficiency is improved by utilizing an adjacency relation and a Boolean function, the model stability is enhanced by combining a trapezoidal function, and the influence of edge change is calculated and evaluated through local sensitivity; parameter control and pruning strategy optimization performance are fused, final output provides a basis for a disturbance mechanism, and privacy security and result reliability are guaranteed.

Circuit 101 combines voltage level shift function with Boolean logic function, comprising: first logic gate circuit 102 (e.g NAND) implementing first Boolean function, having first input connected to

The invention discloses a Boolean function-based sequence-adjustable quantum multi-valued decision diagram construction method and system, and belongs to the technical field of quantum computing, and the method comprises the following steps: S1, Boolean function representation; s2, representing a decision diagram; and S3, combining the decision diagrams. According to the method, the Boolean function is used for representing the quantum circuit, the quantum decision diagram representation of each quantum gate is generated based on the reversible logic, and the quantum decision diagram representations of the multiple quantum gates are combined to generate the quantum multi-valued decision diagram representation of the whole layer of quantum circuit by using the idea of multi-root fusion. The designed quantum multi-valued decision diagram representing the quantum circuit based on the Boolean function can conveniently change the sequence of variables, and is more compact (smaller in size) and efficient (shorter in operation time).