145 results about "Boolean function" patented technology

A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.

Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. Under another embodiment of the invention, the control electrode is arranged in relation to the nanotube channel element to form said conductive channel by causing electromechanical deflection of said nanotube channel element. Under another embodiment of the invention, the output node includes an isolation structure disposed in relation to the nanotube channel element so that channel formation is substantially invariant from the state of the output node. Under another embodiment of the invention, the isolation structure includes electrodes disposed on opposite sides of the nanotube channel element and said electrodes produce substantially the same electric field. Under another embodiment of the invention, a Boolean logic circuit includes at least one input terminal and an output terminal, and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. The Boolean function transformation includes a Boolean inversion within the function, such as a NOT or NOR function.

The present invention teaches a variety of methods for building and searching secure, indexed database tables. Sensitive portions of the database tables and database indexes are encrypted, ordered and searched according to Boolean functions arranged to work with encrypted data. Also disclosed is a database management system that allows authorized users to build and search encrypted tables.

A computerized method and system for solving non-linear Boolean equations is disclosed comprising at least partially solving a Boolean function; developing at least one inference regarding said Boolean function and saving said inference to a state machine; and accessing said inference from said state machine to develop at least one heuristic for determining whether said Boolean function is satisfiable.

A multi-memory cell operator includes a non-destructive memory array, an activation unit and a multiple column decoder. The non-destructive memory array has first and second bit lines per column. The activation unit activates at least two cells in a column of the memory array at the same time thereby to generate multiple Boolean function outputs of the data and of complementary data of the at least two cells on the first bit line and different multiple Boolean function outputs of the data and of the complementary data on the second bit line. The multiple column decoder at least activates the first and second bit lines of multiple selected columns for reading or writing. The multiple column decoder also includes a write unit to write the output of the first bit line, the second bit line or both bit lines of the selected columns into the memory array.

An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.

Data structures for storing subscription predicates for transmission in a publish-subscribe network. Subscriptions include Boolean-valued predicates defining content desired by a subscriber. An agent application converts the predicates into a suitable form for storing them in a common data structure. The predicates are used to generate filters to encapsulate the subscriptions, and the filters are specified in the data structure in addition to the Boolean relationships of the predicates. Routers in a network core use the data structure for content-based routing, which involves applying attributes in received packets to the filters.

A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array. The method includes simultaneously activating a vector-matrix pair of rows R-vector-bit-j and R-matrix-row-j to concurrently receive a result of a Boolean function on all associated columns, using the results to calculate a product between the vector-matrix pair of rows, and writing the product to an R-product-j row in the array.

One embodiment of the present invention provides a system that refines an abstract model. Note that abstraction refinement is commonly used in formal property verification. During operation, the system receives an abstract model which is a subset of a logic design which can be represented using a set of variables and a set of Boolean functions. Next, the system receives a safety property for the logic design which is desired to be proven. The system also receives a set of counter-examples. A counter-example is a sequence of states that violates the safety property. Note that a state is an assignment of values to the variables, which are determined using the set of Boolean functions and the variable values in the previous state. The system then determines a set of cooperative variables using the set of counter-examples. A cooperative variable is a variable that can help invalidate all counter-examples. The system then refines the abstract model using the set of cooperative variables.

The invention discloses an ordered binary decision diagram modeling method for distribution network fault recovery. The method includes a first step of carrying out partition on a power distribution network, and using an on-off state as a decision variable, a second step of forming an adjacent matrix of the power distribution network according to a forming method of the adjacent matrix of an undirected graph, a third step of forming a reachable matrix of the power distribution network, a fourth step of forming boolean functions of each restriction of fault recovery, a fifth step of combining to generate a final binary decision diagram, and obtaining a contractive solution space, a sixth step of carrying out load flow calculation on feasible solutions one by one in the solution space after contraction, and carrying out safety verification, and a seventh step of obtaining an optimal recovery scheme according to priority levels of optimized objective functions. The modeling method has the advantages of effectively reducing the solution complexity of fault recovery problems, overcoming the defect that a traditional artificial intelligence algorithm is prone to premature convergence in local optimal solution, and improves understanding reliability and the like.

The invention discloses a modeling method for achieving distributed-generation-contained power distribution system fault recovery. The modeling method comprises the following steps of (1) reading original data of a distribution network, using a switch as the boundary to carry out partition on the distribution network, and using the switch as a decision variable; (2) forming an adjacency matrix of a region to be recovered; (3) forming a reachable matrix of the region to be recovered; (4) forming the Boolean function about various fault recovery constraints; (5) carrying out merging to form a final mixed decision diagram, carrying out conversion to form an orderly binary decision diagram, and contracting a solution space; (6) determining an optimal fault recovery scheme for the contracted solution space according to a priority of an objective function. The modeling method for achieving distributed-generation-contained power distribution system fault recovery can effectively reduce the complexity for solving the distributed-generation-contained power distribution network fault recovery problem, and can have the advantages of being high in computation speed, high in credibility of solutions, good in actual operability of projects and the like.

Some embodiments provide a method for locking in a mathematical relationship between a set of at least two parameters in a computer program. The method selects a first parameter. The method defines a mathematical relationship that ties the value of the first parameter to the value of a second parameter. In some embodiments, the mathematical relationship can be a mathematical function, a Boolean function, or a lookup table. The relationship could be directly entered by the user, or the computer program itself could derive it from the user's actions. In some embodiments, the first parameter can be locked to the mathematical relationship. The lock prevents the value of that parameter from being changed, except by changing the value of the second parameter. Some embodiments implement this method by using a GUI with an intuitive set of controls.

The embodiment of the invention provides a method for performing on-demand play quantity prediction and memory scheduling on programs, which comprises the following steps: acquiring input data of a neural network according to on-demand play quantities of every program in a number of days preset before specific days; training the previously established neural network according to the input data and the on-demand play quantities of every program within the specific days; and acquiring the input data of the trained neural network according to the on-demand play quantities of every program within the number of days preset before the current day, inputting the input data into the trained neural network, and using the computed output data of the trained neural network as the predicted on-demand play quantities of every program within the current day. According to the embodiment of the invention, the on-demand play quantities of the program is predicted by using the neural network, thereby acquiring the heat of every program; and the three-layer neural network approaches to the characteristics of any Boolean function, thereby enhancing the prediction accuracy and prediction efficiency of hot programs.

A system for clustering Boolean functions for clock gating according to various exemplary embodiments can include a computer configured to identify at least two small gating groups within a clock tree representative of an electrical network and at least two gating functions of the at least two small gating groups, wherein the at least two gating functions are Boolean functions; perform hierarchical clustering on the at least two gating functions using a similarity measure that describes a distance between the at least two gating functions such that the clustering forms a merge function of a cluster generated and displayed in a form of a dendrogram; assign to each gating domain a merit value according to a power consumption profile of the gating domain using a merit function; and partition the cluster into gating groups using the dendrogram to construct a directed acyclic graph to determine a partition which maximize the overall power saving.

The invention discloses a method for forecasting the demand of a wind generating set for spare parts based on fault tree analysis. The method comprises the steps of firstly building an abstract model of a wind generating set fault tree; then acquiring the daily annual fault probability of components corresponding to each bottom event in the fault tree; building a fault tree simulation model by using a Simulink platform, and simplifying a Boolean function expression of a top event; solving a minimum cutest of the fault tree; compiling a numerical operation sub-function for calculating the probability importance degree and key importance indexes of each bottom event; inputting the daily annual fault probability of each bottom event by a user, and calling the sub-function to output the probability importance degree and key importance indexes; and calculating the number of spare parts of each component in a future stage. The method disclosed by the invention is based on the wind generating set fault tree, adjustable in model parameter, capable of adapting to product differentiation of different manufacturers and different working conditions, fault reasons of the wind generating set are detailed, the utilization efficiency of the spare parts is improved, the inventory cost is reduced, and so that the objective of reducing the operation and maintenance cost of wind power generation enterprises is achieved.

Method and system for personalizing a chip, intended to be integrated into a smart card, comprising a tester associated to an FPGA device connected to the chip, the chip being part of a wafer comprising a plurality of chips and a disposable hardware module for verifying presence of the chip on the wafer. The tester sends a first secret code to the FPGA device, which commands the chip to initiate a test mode activation. The FPGA device encrypts a second secret code by using a secret encryption algorithm parameterized with a random number received from the chip and the first secret code to obtain a first cryptogram which is sent to the chip. The chip determines a second cryptogram by carrying out a Boolean function over a result obtained by decryption of the first cryptogram using the inverse algorithm parameterized with the random number and the first secret code. The second cryptogram is compared with a result obtained by carrying out the Boolean function over the second secret code temporarily stored on the chip. The FPGA device personalizes the chip only if the second cryptogram matches the calculated result.

A semiconductor integrated circuit having a reverse engineering protection part that can be easily implemented without additional circuitry or process using a method for protecting against reverse engineering of the semiconductor integrated circuit. The semiconductor integrated circuit includes a logic gate and a reverse engineering protection part. The reverse engineering protection part alters the apparent Boolean functions of a logic gate. Further, the reverse engineering protection part includes at least one PMOS transistor and at least one NMOS transistor. The PMOS and NMOS transistors are constructed to remain in a state of constant on or off irrespective of an input signal applied to their gates. The PMOS transistors and the NMOS transistors are included in transistors forming the logic gate. The PMOS transistors and the NMOS transistors that remain in a state of constant on or off are formed by implanting ions into their gate channels or blocking ion implantation into their gate channels during manufacturing.

For a programmable logic cell, an output assumes a value, which is dependent on values of inputs and on a Boolean function, which determines a value for the output for each setting of the inputs. The logic cell includes at least one ALU and additional logic via which the Boolean function of the logic cell is configurable. In a preferred embodiment, the logic cell contains two 1-bit ALUs and a block generator with four configuration bit memory cells. Here the logic cell can be configured in such a way that it replicates any desired Boolean function with four parameters or any two Boolean functions with two parameters, or is operated in an arithmetic mode.