46 results about "Boolean function" patented technology

In various examples, systems and methods for decomposition of quantum oracles for simulating quantum circuits are provided. A simulation platform may receive as input a representation of a quantum circuit that comprises decomposable Boolean functions that define a quantum oracle and convert a Boolean representation of the quantum oracle to a set of Boolean functions. The Boolean functions may be used to create an oracle tensor network (e.g., a MPO sub-tensor network) comprising an exact representation of the Boolean representation of the quantum oracle. The oracle tensor network representation may be incorporated into a tensor network representation of the quantum circuit and passed to the simulation platform in order to simulate the quantum circuit.

Techniques, for secure processing of encrypted data on public resources, include receiving first data, indicating a sequence of reversible Boolean function control (BFC) gates, including a first segment for decrypting, a second segment for operating on the decrypted data, and a third segment for encrypting the resulting data. Second data indicates generic BFC gate rules for replacing a first sequence of two gates operating on an input N-bit word with a second sequence of one or more gates that produce the same output N-bit word. The second data is used to propagate: a gate from the first segment a distance into the second segment or beyond; and, a gate from the third segment a distance into the second segment or before. This produces an obfuscated sequence of reversible gates. Obfuscated instructions based on the obfuscated sequence of gates are sent to the public resources.

The invention discloses a memristor circuit-based implication logic synthesis and optimization method, which comprises the following steps of: acquiring a gate-level netlist for representing a Boolean function by using an ABC and a simulated annealing algorithm based on a node sensing cost function, and converting a circuit topology connection relationship in the gate-level netlist into an IMG; calculating the optimal IIG of all the four-input NPN Boolean functions by using an SAT-based precise synthesis algorithm and NPN equivalent classification, establishing an IMG off-line database by using IMG logic to represent an inverter in the IIG, and converting an input circuit into an IMG structure by using a logic rewriting algorithm and the IMG off-line database; based on a heuristic algorithm of logic reconstruction, all structures with a fan-out problem in an IMG structure are solved, and an implication network without the fan-out problem and with the number of memristors and the number of pulses reduced is obtained. According to the method, the number of operation pulses in the memristor circuit is reduced, the number of memristors is reduced, and the design cost is reduced.

The invention discloses a fault tree Boolean function equivalent mapping method based on an untrained neural network, and relates to the field of fault tree analysis. In order to solve the problems that in the prior art, a Boolean function mapping structure is not beneficial to parallel expansion, the calculation efficiency is limited, and the Boolean function mapping structure is difficult to efficiently realize on high-parallel platforms such as a GPU, the invention provides a method for generating topological structure data by analyzing a fault tree model; the basic events, the intermediate events and the top events are mapped into neurons of an input layer, a hidden layer and an output layer respectively, a feedforward network with fixed weight and bias is constructed, and a logic activation function is defined in nodes to realize Boolean logic propagation. The input layer receives a basic event state vector, outputs a top event result through forward propagation, and can realize large-scale Boolean function mapping on a parallel platform through batch input matrixes. The method is suitable for reliability analysis, minimum cut set simplification, top event probability calculation, parallelization fault tree solving and the like of a large-scale complex system.

The invention provides an S-box optimization method and device based on a moss growth optimization algorithm, and relates to the technical field of information security. The method comprises the following steps: generating a pseudo-random number based on a two-dimensional hyperchaotic system, constructing a Boolean function according to the pseudo-random number, and optimizing the nonlinearity of the Boolean function to generate an S box; the difference uniformity of the S box is optimized to obtain an initial optimized S box, and the overall performance of the initial optimized S box is optimized based on a moss growth optimization algorithm to obtain a final optimized S box. The device executes the method. According to the S-box optimization method and device based on the moss growth optimization algorithm provided by the embodiment of the invention, the pseudo-random number can be reasonably and efficiently generated, and the overall performance of the S-box is improved through a multi-objective optimization method.

The invention relates to a Boolean function calculation method and device based on fully homomorphic encryption and electronic equipment, and the method comprises the steps: carrying out the format conversion of each received first type of ciphertext based on a target conversion format, and obtaining at least one second type of ciphertext; constructing a multi-layer cascaded CMUX circuit, and based on a preset logic rule, controlling the multi-layer cascaded CMUX circuit to dynamically select pre-encrypted truth table data by taking the second type ciphertext as a control signal to obtain at least one third type ciphertext; and extracting the third type ciphertext coefficient to obtain at least one fourth type ciphertext, and performing blind rotation operation reconstruction on the fourth type ciphertext to obtain at least one encrypted data. Therefore, the problems of low function calculation efficiency, poor expandability and limited calculation precision in the prior art are solved, the resource utilization rate and the parallel processing capability of fully homomorphic encryption in ciphertext calculation are remarkably improved, and meanwhile, the calculation precision and the safety of encrypted data are ensured.

Apparatus and method for implementing an Artificial Neural Network (ANN) section which eliminates the need for backpropagation during training. The ANN section has a plurality of integer gate logic (IGL) nodes respectively arranged into an input layer, an output layer, and at least one hidden layer. Each node has multiple inputs and a single output, and uses a non-differentiable activation function to emulate Boolean logic functions (including XOR), near-Boolean functions, and unknown functions, based on one or more selectable weight values. A chain isolation optimization process is used to select and isolate each node during training to assess the impact of the different weight parameters on the output. Enhanced error functions, batch processing scheduling, and random node selection techniques can be used during training. The nodes can be singly connected, or arranged into convolutional filters or localized fully interconnected layers.

The invention provides a privacy protection decision tree model reasoning method based on partial homomorphic encryption, and relates to the technical field of data privacy protection, and the method comprises the steps: obtaining to-be-predicted sample data, carrying out the preprocessing of each participant, and converting a ciphertext permutation matrix into a secret share matrix; performing bit decomposition on the to-be-predicted sample data to obtain a decomposition matrix, selecting an input sharing mode of the decomposition matrix according to the source of the to-be-predicted sample data, and then converting the input obtained decomposition matrix into a secret sharing share form; each participant performs comparative calculation by using the secret sharing share and the threshold share, evaluates Boolean functions of all leaf nodes to obtain indication result vectors, and randomly arranges the indication result vectors by using a secret share matrix to generate comparative result shares; and each participant constructs a vector pointing to a prediction output leaf node by using the comparison result share to obtain a prediction result, and outputs the prediction result to the sample data provider according to the to-be-predicted sample data source.

The embodiment of the application discloses a decoding logic derivation method, a failed storage particle positioning method and related equipment, comprising: collecting all first error physical addresses generated by testing a same failed storage particle in a first physical slot to form a first error physical address set; collecting all second error physical addresses generated by testing the same failed storage particle in a second physical slot to form a second error physical address set; searching the first error physical address set and the second error physical address set to find k address bits, or a logical combination thereof, which is always a same value in binary logic values of all the first error physical addresses and is always an opposite value of the same value in binary logic values of all the second error physical addresses; and generating a Boolean function of the k address bits or the logical combination thereof as decoding logic. The application can automatically restore hidden physical address decoding logic and realize automatic, accurate and efficient positioning of the physical position of the failed storage particle.

The invention provides an analysis method of a digital logic circuit, computer equipment and a storage medium. The method comprises the following steps: acquiring a digital logic circuit to be analyzed; performing circuit grading by taking a trigger of the digital logic circuit as a node, and selecting the digital logic circuit between any two adjacent stages as a target circuit; wherein the target circuit comprises at least one path, and the at least one path comprises at least one combinational logic unit; determining a variable sequence of the target circuit, and based on the variable sequence, determining a first result of the at least one combinational logic unit according to a Boolean function; wherein the first result corresponds to Boolean difference of output to input of at least one combinational logic unit; determining a target path in the at least one path, and performing ITE operation according to a first result corresponding to the target path; and determining an identification result of the target path according to the operation result.

A processing system configured to execute one or more processing operations, the execution of the one or more processing operations involving the evaluation of at least one Boolean function. The processing system includes an evaluation device configured to evaluate each Boolean function ƒ defined from 2n over 2, in a variable x of length n over 2n. The evaluation device includes: a differential calculation unit configured to calculate differentials Δƒ(y)=ƒ(y)⊕ƒ(y−1) for each integer intermediary variable y ranging from 1 to 2n−1; an accumulation unit configured to sum, using the XOR operator, the product of the differential Δƒ(y) and cn2<sup2>n< / sup2>−y(x) for each value of y ranging from 1 to 2n−1, according to the following XOR accumulation term ⊕y=12<sup2>n< / sup2>−1(Δƒ(y))cn2<sup2>n< / sup2>−y(x), where cnz(x) is the function associating x to the outbound carry of arithmetic summation x+z; a XOR adder configured to add ƒ(0) to the result of the accumulation unit, wherein the output of the XOR adder provides the result of the evaluation of the Boolean function ƒ.

The invention provides a self-anti-S box construction method and system based on m-sequence generation and logic optimization, and belongs to the technical field of cryptography and hardware security. The method comprises the following steps: firstly, constructing an n-level linear feedback shift register according to a set S box number n and a primitive polynomial, generating an m sequence in a non-all-zero initial state, and adding an all-zero state at the tail; a self-reverse S box lookup table is constructed through a symmetric mapping strategy, so that the ith element in the sequence and the element at the symmetric position form mapping, and the same S box is used for encryption and decryption. Thirdly, the lookup table serves as a Boolean function truth table, is simplified into a simplest expression through a logic minimization algorithm and is decomposed into a layered logic circuit; during actual processing, N data blocks are converted into a bit plane format from block type storage, then parallel operation is carried out through a hierarchical circuit, and finally a result is transposed back to block type storage. According to the method, the same S box hardware module can be reused in the encryption and decryption process, and hardware resources are remarkably saved.

The embodiment of the invention discloses a decoding logic derivation method, a failure storage particle positioning method and related equipment, and the method comprises the steps: collecting all first error physical addresses generated by testing the same failure storage particle in a first physical slot, and forming a first error physical address set; collecting all second error physical addresses generated by testing the same invalid storage particle in the second physical slot to form a second error physical address set; the first error physical address set and the second error physical address set are searched, k address bits are found, the binary logic values of the k address bits or the logic combination of the k address bits at all the first error physical addresses are constantly the same value, and the binary logic values of the k address bits or the logic combination of the k address bits at all the second error physical addresses are constantly the inverse value of the same value; and generating a Boolean function of the k address bits or the logical combination thereof as decoding logic. According to the method, hidden physical address decoding logic can be automatically restored, and automatic, accurate and efficient positioning of the physical position of the failure storage particle is realized.

The invention belongs to the technical field of digital circuit design, and particularly relates to a polynomial time discriminant solver, which comprises the following steps of: S1, researching, applying and developing a Boolean function and a Boolean satisfiability discriminant solver in digital circuit design; comprising the following steps: judging whether a satisfiability condition exists or not by utilizing a Boolean satisfiability judgment solver and quickly finding out a working condition; and S2, selecting a proven NPC problem SAT, giving a solution of the SAT, and proving that the solution is completed in polynomial time, thereby proving that P is equal to NP. According to the method, by utilizing examples of three groups of circuit algebras, the high efficiency and usefulness of the given SAT solver are explained, and a complete mathematical proof is given, so that the method has the advantages of high efficiency, high efficiency and high efficiency. Therefore, the cracking of the Pvs NP problem, which is one of seven unsolved problems, is declared. The solver is specially designed for a circuit, and the major problems in the aspects of computer science and application are solved.

This invention discloses a post-mapping optimization method for RSFQ circuits based on path balancing, comprising: parsing the topological connection relationships of nodes in the netlist and presetting the number of iterations; constructing candidate supergates and calculating P-class truth tables, classifying and storing them after P-class transformations, with each P-class truth table storing only the candidate supergate with the fewest JJs, forming a supergate library; perturbing the node hierarchy of the netlist, randomly assigning logic levels, and inserting DFFs; traversing the netlist in reverse to extract fan-out free cones, calculating Boolean function truth tables and performing P-class transformations, matching equivalent structures, and if the number of JJs in the library is smaller, performing an inverse P-class transformation and replacing them in the netlist; performing retiming optimization on the netlist, deleting D flip-flops and continuing iterations or outputting the final netlist. This method has significant advantages in reducing the number of JJs, reducing DFF overhead, and improving the optimization space and efficiency of the mapped RSFQ circuit netlist.

The invention relates to an electronic computing device for generating Boolean functions. The device comprises a conductive module comprising one or more first electrodes, to allow the application of electrical input signals to the conductive module, and one or more second electrodes, to make available electrical output signals from the conductive module. The device comprises one or more input terminals, each of which is selectively connectible to one of said one or more first electrodes for applying electrical input signals to said first electrodes during a step of processing of the device, and one or more output terminals, each of which is selectively connectible to one of said second electrodes to make electrical output signals available on said second electrodes during the step of processing.

A processing system (1) is provided that is configured to perform one or more processing operations involving an evaluation of at least one Boolean function. The processing system includes an evaluation device (20) configured to evaluate each Boolean function of a variable x of length n on # imgabs0 # defined by # imgabs2 # on # imgabs1 #. The evaluation device (20) comprises:-a difference calculation unit (203) configured to calculate, for each integer intermediate variable y ranging from 1 to 2n-1, a difference # imgabs3 #-an accumulation unit (201) configured to summing, for each value of y ranging from 1 to 2n-1, a product of the difference [Delta] f (y) and # imgabs5 # using an XOR operator according to the following XOR accumulation term # imgabs4 #, in which the sum of the products of the difference [Delta] f (y) and # imgabs5 # is greater than the sum of the products of the difference [Delta] f (y) and # imgabs5 # for each value of y ranging from 1 to 2n-1; # imgabs6 # is a function associating x with an outward carry of an arithmetic summation x + z; -an XOR adder (204) configured to add f (0) to the result of the accumulation unit (201), where the output of the XOR adder provides the evaluation result of the Boolean function f.

The invention discloses a method for generating a non-periodic complementary sequence set signal, and belongs to the technical field of communication systems. The method comprises the following steps: setting variables, basic parameters m, b and q and permutation; the replacement is used for rearranging indexes of the variables; defining a residual class ring and an extended Boolean function; the residual class rings are used for defining the value range of the variables and expanding the output space of the Boolean function; the Boolean function is expanded as mapping of an output space and is used for constructing diversity and complementarity of the sequence; constructing an extended Boolean function set; mapping the function into a q-element sequence; and intercepting the sequence and obtaining a complementary sequence set, and outputting the complementary sequence set. According to the method, the basic parameters are set, the parameters are flexibly selected under the condition that basic constraints such as division are met, the parameters of the sequence set are allowed to be customized according to actual requirements, and therefore the inherent limitation of an existing method on parameter selection is improved.

This application provides a device sensing method and an apparatus. The method includes: A sensing device sends a sensing signal, receives an echo signal of the sensing signal, and performs processing based on the echo signal. The sensing signal is generated based on a GCP with a length of N, where N is greater than or equal to 32. When N is equal to 32, 64, 128, 256, 512, or 1024, the GCP may be generated through generalized Boolean function mapping. When N is equal to 160, 320, 640, or 832, the GCP is a direct product of a first GCP and a second GCP, a length of the first GCP is N1, a length of the second GCP is N2, and N1×N2=N.

The application discloses a kind of method for realizing distributed quantum amplitude amplification and related equipment, method includes: the initial success probability of quantum state is quantified based on target unitary operator, and configuration unitary operator is obtained from target unitary operator based on division parameter;Based on division parameter, Boolean function is split into the subfunction of preset quantity and sequentially distributed to each quantum node;Based on configuration unitary operator, the probability upper limit value of each quantum node is quantified using amplitude estimation;According to probability upper limit value, iteration number is obtained, and according to initial success probability, iteration upper limit is obtained;Based on iteration number, the measurement string corresponding to quantum node is iteratively output by quantum amplitude amplification algorithm, and then target string is verified and determined;Quantum operation result is obtained by summarizing the target string corresponding to all quantum nodes.The application can effectively avoid the dependence of existing distributed quantum computation on quantum communication means such as quantum teleportation, and can be widely applied in the field of data processing.

The present invention discloses a logic synthesis and verification method based on memristor-assisted logic, comprising the following steps: S1, logic synthesis: using ABC to obtain a gate-level netlist for representing a Boolean function, converting the circuit topology connection relationship in the gate-level netlist into a DAG; using DFS to obtain the execution sequence of each node in the DAG, and calculating the mapping cost value of each node; obtaining the execution order of the root node in the circuit; for each root node, recursively collecting child nodes and obtaining the corresponding execution sequence, mapping the nodes in the execution sequence to the memristor array in sequence, and generating corresponding micro-operators; S2, verification: parsing the generated micro-operators, and performing logical equivalence and design rule verification on them. This method not only reduces the number of memristor units, but also has a very limited increase in the calculation cycle, and can effectively verify the correctness of the mapping result, and the verification takes a short time.

The present invention discloses a rapid search method and system for three-component second-order threshold implementation solutions, comprising: determining a component coordinate combination based on incompleteness in second-order safety threshold implementation characteristics; determining initial component function expressions of a vector Boolean function based on the component coordinate combination and the correctness of the safety threshold implementation; determining candidate linear additions for each component function based on the component function expressions and the combination probability identical distribution and uniformity in the safety threshold implementation characteristics; placing the component functions corresponding to the coordinate functions that satisfy the probability identical distribution and uniformity and to which the candidate linear additions are added in the memory unit space of the coordinate function; extracting a component function from the memory unit space corresponding to each coordinate function, combining all the extracted component functions into a whole, and taking the whole that satisfies the probability identical distribution, uniformity, and correctness as the final threshold implementation solution. Rapid search for threshold implementation solutions is achieved.

Apparatus and method for implementing an Artificial Neural Network (ANN) which eliminates the need for backpropagation during training. The ANN uses integer gate logic (IGL) nodes arranged into input, output and hidden layers. Each node has multiple inputs and a single output, and uses a non-differentiable linear logic output (LLO) activation function to emulate Boolean logic functions (including XOR), near-Boolean functions, and unknown functions, based on integer-based parameters. A chain isolation optimization process is used to select and isolate each node during training to assess the impact of the different weight parameters on the output. Enhanced error functions, random node selection and pruning techniques can be used during training. The ANN can be used across multiple domains including image processing, RF signal analysis and natural language processing (LLMs). Smaller parameter counts, faster inference times, and greater processor utilization rates have been empirically demonstrated as compared to existing models.

The invention discloses an information security encryption method, system and device, and relates to the technical field of cryptography and information security, and the method comprises the following steps: constructing a generalized Boolean function; with minimization of a golf norm of a generalized Boolean function as an optimization target, constructing an optimization model constrained by multiple cryptographic properties; on the basis of the optimization model, an optimization algorithm is adopted to iteratively update function parameters, and an optimization function meeting all cryptographic property constraints is output; generating a session key based on the linear term coefficient matrix and the nonlinear term index set of the optimization function in combination with an initial key input by a user; plaintexts are grouped, nonlinear confusion is carried out by using an optimization function and a session key, and a ciphertext is generated; calculating a golf norm value of the optimization function, integeting the golf norm value, and adding the integeted golf norm value as a check bit to the ciphertext to complete encryption; according to the method, the characteristics of the data can be more accurately captured, the password cracking difficulty of an attacker is increased, and more powerful and reliable guarantee is provided for information security.

The invention provides a PUF (Physical Unclonable Function) security measurement method based on differential analysis and related equipment. The method comprises the steps of 1, generating an original challenge set; 2, performing bit flipping on challenge vectors in the original challenge set to obtain a flipped challenge set; 3, respectively inputting the original challenge set and the overturned challenge set into the target PUF to obtain a corresponding original response set and an overturned response set; and 4, regarding the target PUF as a Boolean function, performing differential analysis on the original response set and the overturned response set, and regarding a differential analysis result as a security evaluation index of the target PUF. According to the invention, the evaluation standard of the safety of the PUF is perfected.

Machine-leaming-aided logic synthesis using do-not-care-based backpropagation, including constructing a neural network (NN) model based on a functional specification of a circuit design, training the NN model to perform a function of the circuit design, where nodes of the neural network perform a first Boolean function (e.g., AND), and where the training comprises do-not-care-based backpropagating, which may include explicitly computing target functions at fanins of the nodes. The NN may be converted to a two-input graph having nodes that represent a second Boolean function (e.g., AND). The function of the circuit design may include a multiplier function, and the graph may include an AND-inverter graph (AIG). A Boolean patch may be constructed to correct an error in the graph.

The invention discloses a ship electronic information system task reliability qualitative analysis method and device, a medium and a product, and relates to the field of task reliability analysis. The method comprises the steps that after an SFT model is constructed based on external influence factors, features and a probability function equation are solved; constructing a reliability block diagram of each stage based on a solving result and the internal influence factors, converting the reliability block diagram into an SFT model, and performing equivalence on the SFT model based on an infinitesimal substitution principle and performing integration to obtain an ISFT model of the whole stage; representing a structure function as a Boolean function based on an overall stage ISFT model, and obtaining system reliability through non-intersection; a basic event is determined based on system reliability, an AHP model is established, after an AHP judgment matrix is obtained, the weight of each layer in the AHP model is determined, hierarchical sorting and consistency verification are carried out, and qualitative analysis of task reliability is achieved. The problems that an existing reliability analysis method is poor in qualitative effect, incomplete in analysis and the like can be solved.

This invention relates to the field of cryptography and discloses a lightweight stream cipher generation method and system. It involves setting up three shift registers A, B, and C. A and B are linear feedback shift registers, while C is a non-linear feedback shift register. A and B are clocked by C. Two different sets of taps are selected from shift register C, and their Hamming weights W1 and W2 are calculated respectively. Shift registers A and B are then clocked by shifting by W1 and W2 times respectively. Several taps are selected from shift registers A and B as inputs to a non-linear Boolean function H, and a key sequence is output. The plaintext sequence is encrypted using the key sequence to obtain the ciphertext sequence. The method enhances the security of the algorithm by introducing Hamming weight clocking of other shift registers only and by utilizing feedforward Boolean function inputs. The design is simple, and the algorithm has high security.

A construction method for dynamic linear diffusion transformation in block cipher comprises the following steps: performing circle decomposition on a binomial expression xn-1 to obtain all irreducible factors in a decomposition formula, recording all irreducible factors in the decomposition formula of xn-1, constructing all main ideal complementary sets generated by a polynomial ring GF (2) [x] / (xn-1) with respect to the irreducible factors, the complementary set is a Boolean function selection range; selecting a limited number of Boolean functions about x in the obtained Boolean function selection range, and constructing a Boolean equilibrium function f (x) containing a parameter by adopting a mode of combining a plurality of functions; combining and arranging the obtained Boolean equilibrium function f (x) containing the parameter, rewriting the Boolean equilibrium function f (x) containing the parameter into a function of a multivariate, and constructing a multi-output Boolean function by adopting a circulation mode, the multi-output Boolean function being required dynamic linear diffusion transformation on a finite field with the characteristic of 2.