19 results about "Binary decision diagram" patented technology

The invention discloses a data processing method and device of a data center network, equipment, a medium and a product, and relates to the technical field of data processing, and the method comprises the steps: obtaining network topology information and a data forwarding table rule corresponding to each equipment subnet in the data center network; performing parallel coding on each piece of network topology information and each data forwarding table rule based on a network parallel binary decision diagram to obtain a data forwarding path structure between subnets on each piece of equipment, the network parallel binary decision diagram being generated based on a lockless index and hierarchical cache; based on the path connectivity corresponding to the data forwarding path structure, constructing a data forwarding graph corresponding to the subnet on each device; and verifying the data reachability between the subnets on each device according to the data forwarding graph, and generating a data reachability verification result. According to the technical scheme, the concurrency limitation is overcome, high concurrency can be achieved, and the data plane verification efficiency of the data center network is improved.

The invention belongs to the technical field of electronic design automation, and provides a waveform propagation method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design and a waveform file; initial waveform information matched with the target design hierarchy of the circuit design is determined in the waveform file; establishing a binary decision diagram for each instance of the target design hierarchy, and packaging the established binary decision diagrams to a uniform interface to call the binary decision diagram of each instance through the uniform interface; and based on the initial waveform information, starting from a first instance in each instance, performing waveform propagation by using a uniform interface until complete waveform information of the target design hierarchy is obtained. Waveforms of all devices in the whole design can be quickly established in the early stage of integrated circuit design, and the problem that it is difficult for a designer to obtain post-simulation waveforms to accurately calculate circuit power consumption in the early stage is solved.

The invention relates to the technical field of unmanned aerial vehicles. Particularly relates to an unmanned aerial vehicle cluster multi-stage task reliability analysis method and system, a storage medium and a program. According to the method, a task stage process, a subsystem dependency relationship and reliability parameters are embedded into a SysML architecture model, a fault tree of each stage is automatically generated and converted into a binary decision diagram (BDD), and single-machine multi-stage task reliability calculation is achieved. On this basis, the reliability of the cluster in each stage and in the whole task is evaluated in combination with a k-out-of-n system model and a Monte Carlo simulation method, and the minimum delivery quantity is automatically optimized based on a reliability target. Finally, simulation and optimization results are automatically written back to the MBSE model through a parameter diagram, and design-simulation-decision closed-loop linkage is achieved. The method has the advantages of high modeling consistency, high calculation efficiency, optimal resource configuration and the like, and is suitable for reliability evaluation and optimal configuration of unmanned aerial vehicle cluster tasks in a complex environment.

This invention discloses a two-end reliability assessment method and system for SDN based on OBDD. Leveraging the centralized control and easy programming characteristics of SDN, this method establishes an SDN two-end reliability assessment model. By designing the topology management module and path calculation module within the network model, a two-end minimum path set that meets bandwidth and latency constraints is obtained. A minimum path set-breadth-first search algorithm is used to determine the variable ordering of the BDD. The corresponding OBDD is constructed using the Shannon formula in the OBDD construction module. Finally, the reliability assessment module recursively calculates network reliability from the bottom up, completing the SDN two-end reliability assessment. This method combines methods such as the constrained adjacency endpoint matrix algorithm, the minimum path set-breadth-first search algorithm, and the ordered binary decision diagram (OBDD) to assess connectivity reliability in SDN, demonstrating good scalability.

The present application discloses a reliability optimization method, equipment, medium and product for multi-stage peak-shaving tasks of a virtual power plant, which relates to the field of virtual power plant peak-shaving. The method includes constructing a virtual power plant information channel availability model and a virtual power plant information-physical equipment availability model; establishing a binary decision diagram model for all-stage tasks of the virtual power plant; determining the reliability index of all-stage tasks of the virtual power plant based on the above model; establishing and solving a reliability optimization model that considers the uncertainty of real-time peak-shaving service demand and a reliability optimization model that considers the uncertainty of the main scheme equipment state, optimizing the reliability index of all-stage tasks of the virtual power plant, and completing the optimization of the reliability of the multi-stage peak-shaving tasks of the virtual power plant. The present application can take into account the impact of information-physical interaction on the expressiveness of the virtual power plant in the process of participating in the electricity market, and realize the optimization of the reliability of the multi-stage peak-shaving tasks of the virtual power plant.

This application belongs to the field of electronic design automation technology, and proposes a waveform propagation method, an electronic device, and a storage medium. The method includes: obtaining a circuit design and a waveform file; determining initial waveform information in the waveform file that matches the target design level of the circuit design; establishing a binary decision diagram for each instance at the target design level, and encapsulating the established binary decision diagrams into a unified interface to call the binary decision diagrams of each instance through the unified interface; based on the initial waveform information, starting from the first instance in each instance, using the unified interface for waveform propagation until the complete waveform information of the target design level is obtained. This application can quickly establish the waveforms of all devices in the entire design in the early stage of integrated circuit design, solving the pain point that designers are difficult to obtain post-layout simulation waveforms to accurately calculate circuit power consumption in the early stage.

Methods and systems for partially or fully distributed network verification are described. In partially distributed network verification, each network device generates a respective device-level binary decision diagram (BDD) representing the logical behavior of the respective network device for a network property of interest. The device-level BDDs from each network device are received by a verification service that performs verification by generating an input BDD representing an input header space, and applies each device-level BDD in a logical path from a source device to a destination device, and reports the output BDD. In fully distributed network verification, each network device is responsible for calculating a device-specific output BDD by applying a device-specific BDD, which represents the logical behavior of the network device, to a device-specific input BDD.

The invention discloses a human-computer interaction task failure evolution path identification method based on a binary decision diagram, and aims to solve the problem that a task failure path in a complex human-computer interaction system is difficult to accurately identify. The method comprises the following steps: constructing a man-machine interaction task event tree and converting the man-machine interaction task event tree into BDD; determining a top event based on the event tree, constructing a fault tree and converting the fault tree into BDD; integrating the event tree BDD and the fault tree BDD to form a unified BDD corresponding to the ET-FT model; and traversing and identifying a failure evolution path based on the integrated BDD. Unified modeling of static logic and dynamic evolution is achieved through BDD, the causal relationship is quantified by combining Shannon decomposition and the ITE method, and the method has the advantages of being accurate in modeling, efficient in analysis and high in expansibility, can be widely applied to the fields of aerospace, medical equipment and the like and provides support for system reliability optimization.

The invention relates to the technical field of computers, and discloses a method for generating a minimum test case set of a genetic algorithm based on combinatorial optimization. Comprising the following steps: S1, extracting a logic dependency relationship in software, constructing a causal diagram, mapping a conditional branch and variable relationship into a Boolean expression, simplifying the causal diagram, merging invalid paths, reducing input, and converting the Boolean expression into a simplified ordered binary decision diagram; s2, according to the simplified ordered binary decision diagram obtained in the step 1, a combination number is obtained, and the combination number is the number of every two combinations of parameters in the simplified ordered binary decision diagram; and S3, optimizing and simplifying the ordered binary decision diagram by adopting an improved genetic algorithm to obtain an optimal minimum test case set. According to the method, the causal diagram is simplified, the binary decision diagram is simplified into a simplified ordered binary decision diagram, input path branches are reduced, the problem of path explosion is effectively solved, and the cost of test work is reduced.

The invention provides a firewall policy processing method and device, equipment, a storage medium and a program product, and is applied to the field of information security. The method comprises the steps that ni firewall policies of each target device in m target devices are acquired, and each firewall policy comprises a source internet protocol address, a source port number, a destination internet protocol address, a destination port number, a protocol type and a policy action; converting each firewall policy into binary symbol representation; according to ni binary symbol representation, same nodes are merged, a multi-terminal binary decision diagram of each target device is constructed, a source internet protocol address, a source port number, a target internet protocol address, a target port number and a protocol type are represented as intermediate nodes, and a strategy action is represented as a terminal node; performing aggregation operation on the multi-terminal binary decision diagrams of the m target devices, and merging the same nodes to obtain a global decision diagram; and exporting a firewall policy set table according to the global decision diagram.

The invention relates to a quantum circuit processing method and device based on binary decision diagram counting. The method comprises the steps that a quantum circuit recorded in a quantum circuit file is converted into a corresponding initial power sum formula; based on a task type of a to-be-processed task for the quantum circuit, processing the power sum formula to obtain a target power sum formula; and constructing a corresponding multi-terminal binary decision diagram based on the target power sum expression, and processing the multi-terminal binary decision diagram to obtain a processing result of the to-be-processed task.

The invention belongs to the field of probabilistic security analysis, and particularly relates to an event tree analysis method based on a binary decision diagram. Comprising the following steps: 1, representing an event tree by using a BDD structure; 2, preprocessing the structure according to a simplification rule of the BDD, deleting redundant nodes and isomorphic subgraphs in the BDD, and merging final nodes to obtain a simplified BDD structure; step 3, optimizing a BDD structure based on a dynamic variable sorting algorithm of adjacent variable exchange; step 4, obtaining a corresponding optimized event tree by utilizing the BDD after the simplification in the step 2 and the dynamic sorting optimization of the variable sequence in the step 3; and 5, performing qualitative analysis and quantitative analysis on the optimized event tree by using a BDD structure. The method has the beneficial effects that a dynamic variable sorting algorithm suitable for simplifying various event trees is provided for the purpose of minimizing the CD sequence of the event tree, the effectiveness of the algorithm is verified through examples, the space and time complexity of the algorithm can be effectively reduced, and the analysis efficiency of the event tree is improved.

A program according to one embodiment of the present disclosure causes a computer to execute: a first input procedure for inputting a first nonterminal node and a second nonterminal node on a zero-suppressed binary decision diagram; a second input procedure for inputting at least designation of a first function representing a condition to be satisfied by a set pair of a set included in a set group represented by the first nonterminal node and a set included in a set group represented by the second nonterminal node; and a calculation procedure for executing a set group calculation of the set group represented by the first nonterminal node and the set group represented by the second nonterminal node, on the basis of the first nonterminal node, the second nonterminal node, the first function, and a template of an algorithm for achieving the set group calculation.

Data is encrypted using only first and second stages of only 3-bit gates, that are linear, and non-linear, respectively. Each 3-bit gate for a function is conjugated by the first stage, i.e., straddled with the first stage and its inverse, to form a set of gates that are replaced using a finite set of substitution rules to form an ordered set of daughter gates. The daughter gates are conjugated by the second stage to form for each output bit of each layer of a daughter gate, a binary decision diagram (BDD). A module chip is formed by combining all BDDs for each daughter gate. The obfuscated module is configured by combining the module chips. The obfuscated module is sent to an unsecured device for execution thereon.

Methods and systems for network verification are described. An input binary decision diagram (BDD) is defined to represent an input header space for querying a network property of interest. The input BDD is provided as input to a device-level BDD representing a source device in a logical topology representing connections between devices in the network. Each device in the network is represented by a respective device-level BDD in the logical topology. An output BDD is computed, the output BDD representing an output header space output by a destination device in the logical topology. The output BDD is computed by sequentially applying each device-level BDD in a logical path from the source device to the destination device to the input BDD. The output BDD is then reported and the reported output BDD is compared to an expected output BDD to verify the network property of interest.

Data is encrypted using only first and second stages of only 3-bit gates, that are linear, and non-linear, respectively. Each 3-bit gate for a function is conjugated by the first stage, i.e., straddled with the first stage and its inverse, to form a set of gates that are replaced using a finite set of substitution rules to form an ordered set of daughter gates. The daughter gates are conjugated by the second stage to form for each output bit of each layer of a daughter gate, a binary decision diagram (BDD). A module chip is formed by combining all BDDs for each daughter gate. The obfuscated module is configured by combining the module chips. The obfuscated module is sent to an unsecured device for execution thereon.

The application provides a train control system reliability model construction and analysis method based on operation task division. The method comprises the following steps: determining a plurality of stage sub-tasks of a train according to a train transport organization process and a train operation task; establishing a plurality of stage reliability models of a train control system with the train as the core according to the plurality of stage sub-tasks; constructing a fault tree of a basic task reliability model of each stage, and converting the fault tree into a binary decision diagram (BDD) representation; obtaining a failure path leading to a basic task of each stage according to the BDD representation of the basic task of each stage, and calculating the reliability of the basic task of each stage according to the failure path of the basic task of each stage and a fault distribution of each specific device; and calculating a reliability index of the entire train transport task based on the reliability of the basic task of each stage. The method can process system behaviors under real-time dynamic running of a train, and can also perform reliability evaluation on the entire train running process, thereby providing technical support for efficient completion of a train transport task.

The invention relates to a method for quickly predicting the task reliability of a multi-stage control system based on binary decision diagram generation. The invention relates to the technical field of reliability prediction of a control system, and the method comprises the steps: building a system model and task logic, and defining a state variable; generating a global BDD according to the defined state variable; based on the global BDD, the system task reliability is calculated. According to the method, the BDD which is an efficient and graphical representation Boolean logic function is utilized, the static conversion and recursion construction technology is combined, the problem of combinatorial explosion is effectively avoided, the binary decision diagram of the whole system is finally integrated, and the binary decision diagram of the whole task stage of the system is generated at a time through a heuristic method. Dynamic task logic which changes along with stages is coded into a static and uniform BDD structure. And the prediction speed of the task reliability of the multi-stage control system is greatly improved.

Methods and systems for partial or full distributed network verification are described. In partial distributed network verification, each network device generates a respective device-level binary decision diagram (BDD) that represents the logical behavior of the respective network device with respect to a network property of interest. The device-level BDD from each network device is received by a verification service that performs verification by generating an input BDD that represents an input header space, applying each device-level BDD in a logical path from a source device to a destination device, and reporting an output BDD. In full distributed network verification, each network device is responsible for computing a device-specific output BDD by applying a device-specific BDD that represents the logical behavior of the network device to a device-specific input BDD.