Local minimization ROBDD (reduced ordered binary decision diagram) and area delay optimization based process mapping method

Abstract

The invention discloses a local minimization ROBDD (reduced ordered binary decision diagram) and area delay optimization based process mapping method. The process mapping method includes: generating partial optional partitions through domain nodes of the ROBDD, and loosening node delay on non-critical paths to optimize area. For a logical optimization part, shared data structure of a minimization Local ROBDD is adopted, circuit decomposition efficiency is improved by the aid of domain nodes and operation of the ROBDD, and waste of time and memory due to the fact that all the optional partitions are enumerated is avoided; for a structure optimization part, the idea that a classical algorithm Flowmap is used for delay tag minimization of the nodes of a circuit is improved, min-height min-cost coverage is performed in critical paths, and min-cost coverage is performed in the non-critical paths. The shortcomings of mutual restriction of inefficiency as well as delay with the area of all the generated optional partitions are overcome, requirements of a field-programmable device chip on input number of LUTs (look up table) are met, and the objectives of circuit area and delay optimization can be achieved.

Description

technical field [0001] The invention belongs to the technical field of SOPC development of Field Programmable Devices, in particular to a process mapping method based on local minimum ROBDD and area delay optimization. Background technique [0002] With the rapid development of microelectronics technology, digital system applications have basically experienced discrete components, small-scale integrated circuits (SSI), medium-scale integrated circuits (MSI), large-scale integrated circuits (LSI) and very large-scale integrated circuits (VLSI). In the application process, the basic characteristics of digital system applications have experienced the development of small and medium-sized standard general-purpose integrated circuits, user-customized application-specific integrated circuits (ASICs) and field programmable devices (FPGAs). Although application-specific integrated circuits (ASICs) have high speed and low power consumption, their design and manufacturing cycle is lon...

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Problems solved by technology

[0007] The purpose of the embodiments of the present invention is to provide a process mapping method based on local minimization of ROBDD and area delay optimization, which aims to solve the inefficiency of generating all alternative partitions and the interaction between delay and area existing in the existing process mapping method. Constraints

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