258 results about "Electronic design" patented technology

The invention discloses a PCB component layout method, device and equipment based on a multi-modal large model, and relates to the technical field of electronic design automation, the method comprises the following steps: carrying out quality screening on a plurality of PCB design files which have been laid out to obtain a qualified design file set; constructing a serialized training sample set based on the qualified design file set; each training sample sequence comprises a plurality of training samples arranged according to a layout logic sequence; each training sample comprises multi-modal data representing a current layout state and a real position coordinate of a next component to be laid out; based on the serialized training sample set, training the open-source multi-modal large model to obtain a PCB component layout model; and iteratively generating a layout file of the target PCB based on the netlist file of the target PCB and the PCB component layout model. The method is high in generalization capability and low in cost based on the PCB component layout model trained by the layout data, and can realize rapid layout of components of a new PCB.

The invention belongs to the field of electronic design automation, and discloses a multi-agent radio frequency circuit netlist generation method and system based on a large language model, and the method comprises the steps: preparing a data set, and constructing a knowledge base; the method comprises the following steps: receiving and analyzing a natural language demand of a user, combining a cue word project and an RAG mechanism, carrying out chained reasoning, introducing a radio frequency design rule, and converting the information into structured parameter information; combining RAG knowledge base retrieval and new topology generation, and fusing PDK process constraints to obtain candidate topologies and a simulation netlist; a simulation tool is called to execute parameter analysis, iterative optimization is conducted on parameters in combination with a closed-loop feedback mechanism, and a final netlist meeting user requirements is obtained. Automatic decomposition, parallel cooperation and high-speed iteration of design tasks are achieved through multi-agent cooperation and in combination with the radio frequency knowledge graph and the RAG; introducing physical constraints to enable the generated topological structure and parameters to meet the physical constraints; and a closed-loop simulation feedback mechanism is fused, so that the dependence on manpower is reduced.

The invention relates to the technical field of electronic design automation, and discloses a standard cell layout legalization method and system based on a graph theory constraint graph, and the method comprises the steps: building a bidirectional directed constraint graph based on an existing layout and a design rule, and building a directed edge between adjacent graph edges according to the design rule; traversing the constraint graph, detecting whether a directed edge which does not meet a constraint condition exists, and if so, identifying the directed edge as a constraint violation edge; for two end points of each constraint violation edge, searching a key path based on a depth-first search algorithm, and determining a maximum movable distance in combination with a greedy strategy; moving the endpoint to a legal position according to the critical path and the maximum movable distance, and updating the position of a related node in the constraint graph; and mapping the position changes of the nodes in the constraint graph back to the corresponding graph edges in the layout, and outputting the legalized layout, so that efficient and automatic repair of design rule violation is realized through the method, and the layout compliance rate and the area optimization effect are remarkably improved.

A method for data center switching fabric path emulation in an electronics design automation (EDA) environment includes generating emulated data center traffic. The method further includes, at a path emulation element, modifying the emulated data center traffic to emulate passing of the emulated data center traffic through a data center switching fabric. The method further includes outputting, by the path emulation element, the modified emulated data center traffic to an EDA emulator emulating an electronics design under test. The method further includes receiving and storing a response of electronics design under test to the modified emulated data center traffic.

The invention relates to the technical field of electronic design automation, and provides a printed circuit board wiring method and device, equipment, a medium and a program, and the method comprises the steps: classifying an obstacle as a pushable object or a non-pushable object; based on the relative position relationship between the initial path and the pushing object, constructing a geometric occupied area of the pushing object, and performing path offset on the pushing object according to the geometric occupied area; in the deviation process, if the distance between any deviated object capable of being pushed and any deviated object not capable of being pushed is smaller than a preset safety distance, further deviation is stopped, and the deviated object capable of being pushed is reversely returned along the deviation track of the object until the distance between the object capable of being pushed and the object not capable of being pushed is larger than or equal to the safety distance; and re-planning a final path of the signal line according to the position of each pushable object after returning, and outputting a wiring result according with a wiring rule. The method is used for optimizing and completing signal path optimization and distribution in an environment with obstacles.

The invention provides a DFT process monitoring method and device, electronic equipment and a storage medium, and belongs to the technical field of DFTs. The DFT process monitoring method comprises the steps that in response to monitoring that execution of a current test task is finished, a process state and a current log file generated in the process of executing the current test task are obtained; determining a target predefined analysis rule corresponding to the type of the EDA tool adopted for executing the current test task through a mapping relation between the type of the EDA tool and the predefined analysis rule; analyzing the current log file through a target predefined analysis rule to obtain semantic keywords; and determining a final execution state of the current test task based on the process state and the semantic keyword. According to the scheme, massive unstructured log files generated by different EDA tools can be analyzed, and the final execution state of each test task can be determined.

The invention relates to a defect analysis and process optimization method based on artificial intelligence multi-mode fusion, and the method comprises the steps: respectively inputting virtual data of a chip or device design layout, an expected process flow and parameters, and an expected electrical performance curve into an image encoder, a process encoder, and an electrical encoder, extracting a corresponding feature vector; performing cross-modal information interaction on the corresponding feature vectors according to a cross attention fusion mechanism; determining a representation image, a defect category, a root cause category and a process parameter correction suggestion; and based on a manufacturing execution system (MES), an electronic design automation (EDA) tool or an equipment interface, process parameters are corrected, and a closed-loop control result from defect analysis to process optimization is obtained. Therefore, the problems of single data dimension, mutual coupling of various defects, influence of background noise, limited machine identification accuracy, overlarge workload of artificial expert judgment and low efficiency are solved.

The invention discloses a circuit netlist conversion method, a circuit netlist conversion control method and a circuit netlist conversion control device. The method comprises the steps that a circuit netlist is obtained and analyzed, netlist intermediate data are constructed, the netlist intermediate data comprise netlist element data and netlist topological data, the netlist element data are used for representing electrical parameters of circuit elements, and the netlist topological data are used for representing the connection relation of the circuit elements; converting the netlist element data into schematic diagram element data according to an element configuration rule of the target electronic design automation tool; determining position information of the circuit elements and routing information between the circuit elements based on the netlist topological data, and generating schematic diagram layout data adaptive to the target electronic design automation tool; and according to the schematic diagram element data and the schematic diagram layout data, generating a circuit schematic diagram file through the target electronic design automation tool. The circuit netlist conversion method has the technical effect of improving the circuit netlist conversion efficiency.

The invention provides a DFT resource configuration prediction method and device, electronic equipment and a storage medium, and belongs to the technical field of electronic design automation, and the method comprises the steps: determining a reference device density based on a process node of a target chip; determining an effective digital logic layout area based on the chip planning area of the target chip and the estimated non-digital logic function region; according to a utilization rate factor corresponding to the physical design constraint of the target chip, correcting the effective digital logic layout area to obtain an available standard cell layout capacity; according to the standard unit layout capacity and the reference device density, generating a time sequence element number prediction interval of the target chip through a logic depth mapping model; and according to the time sequence element number prediction interval, generating testability design DFT architecture configuration parameters of the target chip. The number of chip registers can be quickly and accurately predicted and the DFT architecture configuration parameters can be generated in the early stage of chip design.

The invention relates to the field of electronic design automation, provides a method for semi-automatically processing an EDA (Electronic Design Automation) project file and generating a YOLO format annotation data set, and aims to solve the technical problems of low efficiency and poor precision of the traditional pure manual data annotation data set. According to the main scheme, the method comprises the steps of reading an engineering file of a jia-creative EDA project, analyzing and extracting element information, generating a standardized CSV data format, converting the standardized CSV data format into a label in a YOLO format, calculating normalized bounding box coordinates of elements, and recognizing special original elements and supplementing labeling information in combination with a template matching technology; drawing a bounding box on the schematic diagram image according to a YOLO label, highlighting different element types by using different colors, and generating a visual annotation image; revising and combining the newly generated YOLO label and a preliminary YOLO label generated by the AI model to obtain a label set; then importing into Labelimg for manual correction, and generating a final label set; and training a target detection model by using the final label set, and improving the pre-labeling precision through data set expansion iteration.

The invention provides a logic synthesis optimization method and device, electronic equipment and a computer storage medium, and belongs to the technical field of EDA, and the logic synthesis optimization method comprises the steps: determining a target module included in an optimization strategy based on a time sequence report generated in a logic synthesis process; in the optimization strategy, a register retiming function and a register optimization function of the target module are enabled, so that the electronic design automation tool allows the registers between the modules to be moved when optimizing the target module; and based on the optimization strategy, executing logic synthesis on the to-be-synthesized design. A key bottleneck module influencing time sequence convergence can be optimized in a targeted manner in a logic synthesis process.

The present invention relates to a method of optimizing design (201) comprising the steps of obtaining at least one design (201) from at least one electronic design automation (EDA) tool (113); defining said design's at least one goal (205) and optimizing said design's at least one parameter (203) with at least one multi-agent design optimizer (107).

The invention discloses an electronic design multi-agent system with graph structure control and feedback iteration capabilities and an operation method thereof. The electronic design multi-agent system comprises a natural language analysis module, a decision planning agent, a functional module agent set, a schematic diagram construction agent, an assembly agent, a simulation verification agent and a feedback iteration module. The system receives a circuit design requirement described by a natural language, automatically constructs a sub-task dependency graph, distributes parallel tasks, retrieves matched components and generates a local schematic diagram through a multi-agent cooperation mechanism, and assembles the local schematic diagram into a complete schematic diagram. The system automatically triggers task re-planning, device re-matching and graph structure optimization through simulation verification and error feedback to form closed-loop iterative control. According to the method, automatic conversion from the natural language to the schematic diagram conforming to the electrical specification is achieved, the problems that a traditional EDA tool is complex in operation and existing AI aided design lacks systematicness and self-optimization capacity are solved, the design threshold is remarkably lowered, and the design efficiency and quality are improved.

The invention relates to the technical field of electronic design automation design, in particular to a snapshot output method for effective paths in a network, electronic equipment and a storage medium, and the method comprises the steps: obtaining all effective paths in the current network, and obtaining an effective path set; in the process of acquiring the effective path, acquiring a node of which the role type is an end point; according to the effective path set and attribute information carried by nodes and edges in each effective path, a current network name is output, nodes and snapshot information thereof are output according to a node sequence in each effective path, and the snapshot information comprises a current node name, a role type, a node position and an accumulated path length of each node; the cumulative path length is the cumulative sum of all continuous routing and fly line lengths from the starting node of the effective path to which the current node belongs to the current node, the technical problem that the effective path in the network and related information of the nodes in the path cannot be effectively acquired at present is solved, and effective data is provided for simplifying simulation.

The invention discloses a BGA simultaneous escape wiring method based on shared node and combined congestion negotiation, and belongs to the technical field of electronic design automation. The method comprises the following steps: constructing a directed graph representing a wiring space, and determining a starting point and an ending point of each to-be-wired network; adopting a bidirectional Dijkstra algorithm to carry out parallel path search on all the networks; dividing the line network into a single line network and a conflict line network containing shared nodes; the conflicting networks are grouped, so that the networks in the group only share nodes with one another; on the basis of a network quality evaluation model, selecting one network from each group to remove the network, and dynamically updating the cost value of wiring nodes; and iteratively executing the steps of searching, grouping, clearing and cost adjustment until all the wire nets are single wire nets, and outputting a final wiring result. According to the method, wiring congestion can be effectively reduced, path bypassing is avoided, and the success rate, the wiring quality and the algorithm convergence efficiency of BGA packaging and escape wiring are remarkably improved.

This application discloses a computing system to obtain a wafer image of an electronic device having physical structures manufactured using one or more lithographic masks associated with a layout design describing the electronic design. The computing system can implement an unsupervised deep learning algorithm to process the wafer image to remove at least some noise from the wafer image, which generates a denoised wafer image. The computing system can extract contours corresponding to the physical structures of the electronic device from the denoised wafer image of the electronic device without use of the layout design or a mask design. The computing system can calibrate the layout design or the mask design describing the one or more lithographic masks based, at least in part, on the contours extracted from the denoised wafer image.

The application discloses an excitation automatic generation method and system and a computer readable medium, and relates to the technical field of electronic design. The method comprises the following steps: based on a pre-acquired test case file, a target test case is acquired from a plurality of pre-stored test cases; case key information of the target test case is acquired, and the case key information is used for representing basic signals to be simulated by the target test case; and based on the case key information, an excitation signal is generated. Therefore, in the face of different target test cases, a control excitation signal with a unified style is automatically generated based on the case key information of the target test case, thereby reducing the dependence of cases on manual checking of logic functions and manual writing of excitations for the functions, and improving the design and development efficiency of integrated circuits.

This invention introduces an advanced method for manufacturing printed circuit boards (PCBs) featuring an embedded shield, enhancing the integrity and functionality of electronic devices. The process involves forming trenches on the PCB, filling them with solder paste, and seamlessly integrating a shield with a frame through a meticulous soldering procedure. This refined technique offers superior reliability and paves the way for more intricate and robust electronic designs.

The present disclosure provides a Boolean formula unsatisfiability core prediction method based on hypergraph modeling. A CNF formula generated by a software and hardware formal verification problem coding in the field of electronic design automation is received from the outside, input into a hypergraph representation learning model, and modeling for solving a SAT problem corresponding to the software and hardware formal verification problem is obtained. The model is constructed in the following manner: first, SAT problem representation based on hypergraph is performed. Specifically, the CNF formula is modeled as a clause-literal hypergraph by using a SAT problem modeling method based on hypergraph and a message passing method based on hypergraph, and a clause correlation graph is further constructed to obtain problem representation. Then, a polarity-aware variable decomposition method is applied to the clause correlation graph, and the problem representation is structured and modeled. The hypergraph representation learning model is trained by using a training method based on polarity-aware consistency constraints, and is integrated with a SAT problem solver, so that the model can be used to solve the problems that the existing graph neural network-based SAT learning method has in the aspects of polarity modeling and high-order structure expression.

The application provides a radio frequency device behavior model parameter extraction method based on transfer learning, extracts polynomial model coefficients through a neural network model, reduces the amount of data required for establishing the neural network model, improves the portability and optimization efficiency of the model, realizes seamless integration of the neural network model and EDA software, and accelerates the progress of the electronic design process; the neural network model uses a test model in an old working state as a starting point for a new working state, avoids re-extracting model coefficients, and saves test time and instrument cost.

This invention belongs to the field of integrated circuit design technology, specifically relating to a method for optimizing integrated circuit design data. This method first constructs a "tool-layer-semantic" data acquisition architecture, integrating multi-channel parallel acquisition units to collect heterogeneous data from multiple sources. Compliance pre-verification is performed through hardware logic circuits and a verification rule base, extracting key data identifiers. A three-level incremental compression strategy based on key data priority, combined with an intelligent index integrating multi-dimensional indexes, is used for compression and storage. The stored data undergoes multi-dimensional optimization, including semantic deduplication, priority optimization, format conversion, and source quality backtracking, forming a unified format optimized semantic. Through an interactive interface, it is adapted and interacted with electronic design automation tools. After consistency verification and performance testing feedback loops, the final design data and full-process traceability information are obtained and stored. This invention achieves unified management, efficient compression, intelligent optimization, and full-process traceability of design data.

Various embodiments provide for assigning portions of a net based on one or more non-default design rules, which may be part of electronic design automation (EDA). For example, a net of a circuit design can be a clock network, and the assigning can comprise a layer assignment process, a track assignment process, or both. Additionally, various embodiments described herein can permit a plurality of non-default design rules to be applied to a single net of a circuit design.

The application relates to the field of photonic device modeling, and discloses a parameterized optoelectronic joint simulation platform construction method for optoelectronic chip design, which is characterized in that, in an electronic design automation platform, a unified model framework of a photonic device is constructed based on a hardware description language, and conversion between frequency domain response and time domain response is realized in the model, including the following steps: a general VerilogA model framework is constructed based on the frequency domain response of the photonic device; a frequency-time domain numerical conversion mechanism is realized in the model; and for the photonic device with dispersion characteristics, a parameterized time domain model is constructed based on a finite impulse response. The application can directly embed the photonic device model into an electronic circuit simulation environment, co-simulate the electronic device, support time-frequency domain analysis of the cascade structure and the loop structure, thereby avoiding the complicated steps of separate simulation by relying on external simulation tools in the process of optoelectronic chip design, and further improving the design efficiency and iteration speed of the chip.

A method for developing a design of an electronic circuit in Electronic Design Automation (EDA) environments is disclosed. The method comprises receiving data regarding an event related to a specific

Embodiments included herein are directed towards a method for use in an electronic design. The embodiments may include receiving, at a graphical user interface, a command associated with a currently displayed electronic design session and determining, using a processor, that a modal dialog from a non-currently displayed electronic design session is triggered by the command. Embodiments may further include causing a display at the graphical user interface of a form associated with the modal dialog that requires user action.

The application belongs to the technical field of electronic design automation, and discloses a PCB schematic diagram picture labeling and data set generation method and system. The method automatically reads a PCB schematic diagram picture through a YOLO model to generate a YOLO format file to obtain component information, then cuts the picture by using a QT tool and classifies based on a label, then carries out label inspection and labeling to generate a log file, and finally processes the log file to modify a YOLO format output label data set. The method greatly improves the labeling efficiency, reduces the labor cost and error rate, enhances the adaptability to different EDA tools for generating schematic diagrams, simplifies the construction of high-quality data sets, and thus accelerates the landing application of artificial intelligence in circuit design automation.

The invention is applicable to the technical field of electronic design automation, and provides a cross-design software netlist data co-processing method, which comprises the following steps: acquiring first netlist data; wherein the first netlist data is used for representing a logic connection relationship among a plurality of electrical components in the first schematic diagram, packaging library information corresponding to the electrical components and the like; wherein the first schematic diagram is a schematic diagram constructed based on first design software; performing data format conversion on the first netlist data to obtain second netlist data; importing the second netlist data into second design software; wherein the second design software is different from the first design software; and generating a circuit diagram corresponding to the printed circuit board based on the second netlist data and the second design software. According to the method, when cross-software circuit diagram design is carried out, an engineer does not need to consume extra time in format adaptation and data verification, so that the method focuses on core design links such as circuit diagram layout and wiring, the design period is shortened on the whole, and the working efficiency is improved.

Systems for training a convolutional neural network to register images for masks or wafers in semiconductor manufacturing include a computer processor configured to receive a first pair of images aligned in a first modality and a second pair of images aligned in a second modality. Images in the first pair of images and the second pair of images are a computer aided design (CAD) image pre-aligned with a scanning electron microscope (SEM) image. An affine transformation is generated with a convolutional neural network, using one image from the first pair of images and one image from the second pair of images. The one image from the first pair of images is in the first modality and the one image from the second pair of images is in the second modality. Systems for registering images for masks or wafers in semiconductor manufacturing use the trained convolutional neural network.

The invention relates to a defect analysis and process optimization method based on artificial intelligence multi-modal fusion, and the method comprises the steps: respectively inputting a representation image, an electrical curve and process parameters in a reasoning stage into an image encoder, an electrical encoder and a process encoder, so as to extract corresponding feature vectors; performing cross-modal information interaction on the corresponding feature vectors according to a cross attention fusion mechanism, and quantifying the responsibility degree of the process parameters to obtain fusion features; determining a defect category, a defect root cause, a process parameter correction amount and a process parameter correction suggestion; and based on a manufacturing execution system (MES), an electronic design automation (EDA) tool or an equipment interface, process parameters are corrected, and a closed-loop control result from defect analysis to process optimization is obtained. Therefore, the problems of single data dimension, mutual coupling of various defects, influence of background noise, limited machine identification accuracy, overlarge workload of artificial expert judgment and low efficiency are solved.

A macro cell layout method and a related apparatus, relating to the technical field of electronic design automation. The method comprises: acquiring connection relationship information and alternative layouts of t macro cells; inputting the connection relationship information and position information into an indicator prediction model so as to output predicted values of evaluation indicators; and obtaining a target layout of the t macro cells on the basis of the predicted values of the evaluation indicators and the alternative layouts. In the present application, the evaluation indicators may be any indicators, such as worst negative slack, total negative slack, half-perimeter wirelength, and degree of congestion. The problem that existing macro cell layout methods mainly focus on optimizing intermediate proxy indicators which are easy to acquire at a current stage and ignore cross-stage indicators which truly reflect final chip quality is solved and the timing performance of a circuit is optimized, ensuring that the circuit has a higher design quality and higher manufacturability. In the present application, the objective of improving evaluation indicators of a circuit in an "end-to-end" manner is achieved, manual intervention is not needed, costs are lower, and efficiency is higher.