558 results about "Electronic design" patented technology

The invention relates to the technical field of electronic design automation, in particular to a local layout wiring method based on sequence value correction and historical guidance search, which comprises the following steps: calling a multi-source dynamic sequence value wave diffusion path search sub-algorithm, generating initial paths for all wire nets, and initializing a historical solution set and a current solution sequence; random disturbance is carried out based on the current solution sequence, and candidate solutions are generated; judging whether the candidate solutions meet design rule constraints or not; checking whether the maximum iteration frequency is reached or no improvement frequency limit exists, if yes, entering the step of outputting the optimal solution, and otherwise, returning to the step of generating the candidate solution; selecting a wiring path which has an optimal target function value and meets all constraints from the historical solution set, and outputting a final result; according to the local layout wiring method based on sequence value correction and historical guidance search, the problems of high-density region wiring feasibility, complex design rule satisfaction, multi-objective optimization, calculation efficiency and the like can be solved.

The invention belongs to the technical field of electronic design automation, and provides a dynamic power consumption optimization method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design, and determining a starting point of a specific type in the circuit design; performing backward traversal on the circuit design along a signal propagation direction from the starting point to determine circuit branch structure information and a specific type of termination point in the circuit design; starting from the termination point, establishing an ODC expression, performing forward traversal on the circuit design in an inverse signal propagation direction, and in the forward traversal process, based on the circuit branch structure information, propagating the ODC expression in the circuit design until ODC distribution of the circuit design is determined; based on the ODC distribution, dynamic power consumption optimization is performed on the circuit design. According to the method, the ODC expression can be quickly and efficiently propagated in the whole circuit design, so that a designer can conveniently optimize the dynamic power consumption through ODC distribution.

The invention discloses a FinFET process standard unit wiring control method and related equipment, and relates to the field of electronic design automation, and the method comprises the steps: preprocessing basic design rule inspection data, and generating two-dimensional and three-dimensional design rule inspection rules; reading a user chip design file to form pre-design data; and evaluating a three-dimensional design rule predicted value in combination with engine rule data and three-dimensional coordinate values, selecting a pin access sequence, and executing basic wiring, through hole generation and inspection operations. And correcting illegal wiring, and finally generating target wiring data through iterative time sequence optimization and rule check.

The invention belongs to the field of electronic design automation and static time sequence analysis, particularly relates to a parallel optimization method for FPGA static time sequence analysis, and aims to solve the problems of low calculation efficiency and long compiling time of static time sequence analysis in the prior art. The method comprises the following steps: performing memory layout optimization on a time sequence diagram and time sequence constraints according to a built FPGA-oriented STA data structure; task decomposition is carried out, calculation tasks of nodes and edges of each hierarchy are allocated to a plurality of parallel kernels to be executed in parallel, and single CPU threads are allocated to different hierarchies to be executed in sequence; during execution, traversing the time sequence diagram, and marking to-be-updated nodes and edges; and obtaining effective arrival time and effective demand time of the nodes through bidirectional traversal calculation, determining a key path in FPGA (Field Programmable Gate Array) time sequence static analysis, and generating a parallel optimization report of the FPGA static time sequence analysis. According to the method, the calculation efficiency in static time sequence analysis is improved, and the compiling time is shortened.

The invention relates to a software and hardware SOC (System On Chip) verification system and method based on EDA (Electronic Design Automation) and an FPGA (Field Programmable Gate Array), and belongs to the field of SOC chip verification. The software part comprises an SOC UVM TESTBENCH SOC verification platform, a disk network disk and a T CP protocol client side; and the hardware part mainly comprises a TCP (Transmission Control Protocol) SERVER protocol server side and a SOCTOP (System On Chip Over Programmable). The method is characterized in that advantages of EDA verification and FPGA prototype verification are combined, cross-platform accelerated verification of the SOC chip is realized, the verification period of the chip is shortened, and the verification quality of the chip is improved.

The invention discloses a PCB component layout method, device and equipment based on a multi-modal large model, and relates to the technical field of electronic design automation, the method comprises the following steps: carrying out quality screening on a plurality of PCB design files which have been laid out to obtain a qualified design file set; constructing a serialized training sample set based on the qualified design file set; each training sample sequence comprises a plurality of training samples arranged according to a layout logic sequence; each training sample comprises multi-modal data representing a current layout state and a real position coordinate of a next component to be laid out; based on the serialized training sample set, training the open-source multi-modal large model to obtain a PCB component layout model; and iteratively generating a layout file of the target PCB based on the netlist file of the target PCB and the PCB component layout model. The method is high in generalization capability and low in cost based on the PCB component layout model trained by the layout data, and can realize rapid layout of components of a new PCB.

An electronic design automation tool and method of operating the same are provided for placement and routing of intra-cell devices in integrated circuits (ICs). Generally the method includes: receiving inputs, creating an instance of a Satisfiability Modulo Theory (SMT) problem for placement and routing by translating the inputs into a set of SMT constraints relating to the placement of intra-cell transistors and routing for interconnects to intra-cell transistors, calling a SMT solver and using the set of SMT constraints generating a solution to the SMT problem, and if the solution satisfies requirements of the inputs and a predetermined area requirement specified by a user, creating and outputting a layout for placement and routing of intra-cell transistors in the IC. The process may be repeated until a predetermined number of ranked solutions or an optimal solution is found. Other embodiments are also disclosed.

The invention discloses a PCBA (Printed Circuit Board Assembly) processing component layout optimization method and system, and relates to the technical field of electronic design automation. Data stream information of each functional module of a PCBA is collected, data stream characteristics are analyzed, and key signal paths and interaction relationships are determined; the method comprises the following steps of: dividing priorities for different data streams according to functional requirements and signal importance of a PCBA (Printed Circuit Board Assembly), and determining a core signal; by optimizing component layout, reducing roundabout and intersection of signal paths, reducing signal transmission loss and interference, reasonably dividing functional areas and compactly arranging associated components according to data stream directions and core signals, it is ensured that the signal transmission paths are clear and efficient, meanwhile, the transmission quality of high-priority signals is preferentially guaranteed, and the transmission efficiency is improved. By adopting a transmission line with strong anti-interference capability, adding a signal buffer and filter circuit and other measures, the signal integrity is obviously improved, and the signal is kept stable and reliable in the transmission process, so that the performance of the whole PCBA system is improved.

The invention discloses a PCB layout optimization method, system and device based on an evolutionary algorithm and a medium, and relates to the field of electronic design automation, and the method comprises the steps: S1, obtaining an initial layout generated by a PCB; s2, judging whether the number of iterations is greater than or equal to the maximum number of iterations; s3, if yes, ending; s4, if not, random disturbance is generated according to the current layout, and a new layout is generated; s5, comparing the new layout with the current layout by adopting an objective function, and judging whether the new layout is superior to the current layout or not; s6, if not, whether the acceptance probability function is larger than a set value or not is judged; s7, if not, returning to S2; s8, if the acceptance probability function is greater than a set value or the new layout is superior to the current layout, taking the new layout as the current layout; and S9, when the current layout is superior to the optimal layout, updating the optimal layout by using the current layout, and returning to S2. According to the method, optimization of the layout of the PCB is realized, and a more ideal layout effect is achieved.

The invention relates to the field of electronic design automation (EDA), and provides an AMS circuit automatic design method using a large language model. The method aims at solving the problem that an existing AMS circuit design is insufficient in automation degree, and mainly comprises the steps that a schematic circuit diagram and text description are extracted from literatures, and a data set containing the schematic circuit diagram, a netlist and annotation information is constructed; performing connectivity detection on the schematic circuit diagram, and extracting a netlist; carrying out annotation processing to obtain annotation information; constructing a knowledge graph for storing circuit information; obtaining a design strategy by using a large language model, and describing a circuit architecture; according to the design strategy and the local annotation, relevant circuits and test platforms are retrieved, a complete circuit topology is assembled, and simulation is carried out; size optimization is carried out based on constraints, and a Bayesian optimization algorithm is used for solving; and if the initial topological structure cannot meet the performance target, carrying out topological reconstruction. According to the invention, the automation level and efficiency of analog and mixed signal circuit design are improved.

The invention provides a method and a system for automatically checking and correcting a PCB (Printed Circuit Board) design rule, belonging to the technical field of PCB design. The method comprises the following steps of: analyzing data such as texts, images and tables in a PCB design document through a multi-modal large model, extracting a structured signal information table, automatically generating a dynamically adaptive checking rule, and automatically checking and correcting the PCB design rule. Comprising bit width check, connectivity verification and functional analysis. And the generated rule is optimized by combining a retrieval enhancement generation (RAG) technology with a verification rule base, so that the coverage is comprehensive and the accuracy is high. The system further evaluates the rule through a form verification tool, automatically corrects potential defects, and improves the quality and adaptability of the rule. According to the method, the efficiency and accuracy of PCB design inspection are remarkably improved, the manual intervention requirement is reduced, the method can be widely applied to complex electronic design scenes, and the rapid changing technology and market requirements are met.

The invention provides an electronic design automation simulation system-on-chip double-rate synchronous dynamic random access memory verification method and verification system, a test device and computing equipment, the method is applied to a startup program, and the method comprises the following steps: obtaining a test case designed according to the characteristics of a double-rate synchronous dynamic random access memory needing to be verified; running a first-stage boot loader; running a second-stage boot loader, and completing initialization of the double-rate synchronous dynamic random access memory; running a third-stage boot loader, loading the test cases in sequence, and carrying out electronic design automation simulation verification; and outputting a verification result through the central processing unit to complete the characteristic verification of the double-rate synchronous dynamic random access memory. According to the technical scheme of the invention, the complexity of DDR verification can be reduced, and high-efficiency DDR verification is realized.

The invention relates to the technical field of electronic design automation, in particular to a coverage rate-based index database management method, coverage rate-based index database management equipment and a storage medium. Meanwhile, extracting design level information in the coverage rate database to establish an index database consisting of a plurality of index tables; when the visual query window initiates a query request, the index database queries the identifier of the target object according to the query request, and processes and updates the target window of the coverage rate visual system according to the identifier in the coverage rate data structure, so that the search efficiency is greatly improved, and the search time is shortened. And the purpose of real-time searching is achieved.

The invention relates to the technical field of electronic component data processing, in particular to a database construction method and system based on electronic components. The method comprises the following steps: carrying out component information acquisition through an electronic component transaction platform to obtain an original component data set; performing component relation mapping construction according to the original component data set to obtain a component association graph; performing multi-dimensional attribute extraction on the component association map to obtain component attribute vectors; performing component similarity calculation and clustering analysis according to the component attribute vector to obtain a component cluster; and extracting pin information according to the component cluster to obtain a cluster pin data set. According to the method, multi-dimensional condition screening, sorting and result explanation are realized, an accurate, reliable and easily understood component replacement recommendation scheme is provided for a user, the user is helped to quickly find a proper component, and the electronic design efficiency is improved.

Embodiments included herein are directed towards a method for use in an electronic design. The embodiments may include causing, at a graphical user interface, a display of a portion of the electronic design. The method may further include determining a location of a mouse cursor at the graphical user interface. The method may also include automatically displaying at the graphical user interface one or more shapes associated with a current fabric. The method may additionally include automatically performing a cross fabric shape query associated with the location of the mouse cursor. Furthermore, the method may include automatically displaying one or more cross fabric shapes at the graphical user interface.

Example implementations include a method, apparatus and computer-readable medium for automated analog electronic system design and analysis, comprising receiving a user query via a user interface. The implementations further include identifying, by a conversation agent of a machine learning model (MLM), at least one attribute of the user query. Additionally, the implementations further include selecting from a plurality of agents, by the conversation agent of the MLM, two or more agents that can collectively generate a response to the user query when executed in a specific sequence based on the at least one attribute of the user query. Additionally, the implementations further include prompting, by the conversation agent of the MLM, the two or more agents in the specific sequence to collectively generate the response. Additionally, the implementations further include outputting, by the conversation agent of the MLM, the response via the user interface.

The invention discloses a rapid automatic time sequence ECO method and system based on graph interpretability. The rapid automatic time sequence ECO method based on graph interpretability comprises the steps that topological features and electrical features are extracted from a design file, a process library and a time sequence report of a circuit, and a path delay predictor based on a graph neural network is built; forward propagation is carried out on a given key path based on a path delay predictor to predict delay; obtaining the importance of each node, edge and feature on the key path based on a graph interpretability method; and according to importance, an appropriate ECO action is automatically selected for iteration. The method aims at solving the problems that in an existing electronic design automation (EDA) process, when time sequence analysis and optimization are conducted on a complex integrated circuit path, the accuracy of path delay prediction is insufficient, an explanatory analysis tool is lacked, and the efficiency of the ECO process is low.

The invention belongs to the field of electronic design automation, and discloses a multi-agent radio frequency circuit netlist generation method and system based on a large language model, and the method comprises the steps: preparing a data set, and constructing a knowledge base; the method comprises the following steps: receiving and analyzing a natural language demand of a user, combining a cue word project and an RAG mechanism, carrying out chained reasoning, introducing a radio frequency design rule, and converting the information into structured parameter information; combining RAG knowledge base retrieval and new topology generation, and fusing PDK process constraints to obtain candidate topologies and a simulation netlist; a simulation tool is called to execute parameter analysis, iterative optimization is conducted on parameters in combination with a closed-loop feedback mechanism, and a final netlist meeting user requirements is obtained. Automatic decomposition, parallel cooperation and high-speed iteration of design tasks are achieved through multi-agent cooperation and in combination with the radio frequency knowledge graph and the RAG; introducing physical constraints to enable the generated topological structure and parameters to meet the physical constraints; and a closed-loop simulation feedback mechanism is fused, so that the dependence on manpower is reduced.

The invention relates to a logic comprehensive sequence optimization space exploration method and system for reinforcement learning based on reward correction, and belongs to the technical field of electronic design automation. A logic comprehensive process is embedded into a reinforcement learning algorithm based on reward correction, and the logic comprehensive process is modeled as a reinforcement learning environment; and the logic comprehensive sequence optimization space is automatically explored. A reinforcement learning algorithm is improved for a logic comprehensive scene, feature extraction and action coding are carried out, the circuit state expression precision is improved, and the search space is expanded. According to the method, by adding award correction, the exploration ability in the early stage of training is improved, a self-adaptive award function is obtained through intelligent agent training, performance reduction caused by limitation of priori knowledge on the circuit optimization direction is reduced, and a better logic comprehensive area result is obtained under the condition that delay constraints are met.

The invention provides a device model updating method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the simulation of a device required by a to-be-processed process node through electronic design automation simulation software, constructing a device simplified model based on the model simulation parameters of the device extracted in the simulation process, and carrying out the simulation of a device model. Generating a corresponding standard unit circuit according to the device simplification model; in electronic design automation simulation software, a simulation test circuit comprising a standard unit circuit is built by using a simulation circuit simulator, and netlist simulation is carried out on the simulation test circuit; calculating a difference value between the netlist simulation result and an actual circuit test result of the device, and adjusting model simulation parameters according to the difference value; and generating an updated device model of the device by using the adjusted model simulation parameters.

The invention belongs to the technical field of electronic design automation, and provides a waveform propagation method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design and a waveform file; initial waveform information matched with the target design hierarchy of the circuit design is determined in the waveform file; establishing a binary decision diagram for each instance of the target design hierarchy, and packaging the established binary decision diagrams to a uniform interface to call the binary decision diagram of each instance through the uniform interface; and based on the initial waveform information, starting from a first instance in each instance, performing waveform propagation by using a uniform interface until complete waveform information of the target design hierarchy is obtained. Waveforms of all devices in the whole design can be quickly established in the early stage of integrated circuit design, and the problem that it is difficult for a designer to obtain post-simulation waveforms to accurately calculate circuit power consumption in the early stage is solved.

The invention relates to the technical field of electronic design automation, and discloses a neural network training method and system for automatic circuit generation, and the method comprises the steps: carrying out the preprocessing of initial circuit design data, obtaining target circuit design data, recognizing the module type of each circuit function module in the target circuit design data, and carrying out the recognition of the module type of each circuit function module; marking circuit function modules by using the module types, identifying module features corresponding to the circuit function modules, training the initial convolutional neural network by using the module features corresponding to the circuit function modules of the same module type, and obtaining a target convolutional neural network corresponding to each module type, and training the initial graph neural network according to the associated information to obtain a target graph neural network. The circuit design efficiency can be improved.

The invention discloses a bimodal industrial package defect detection method, and belongs to the technical field of industrial package label quality detection, and the method comprises the steps: collecting a label electronic design drawing and a label object image on an industrial package; respectively separating the label physical image and the label electronic design drawing into a text image and a label area image; identifying a text region in the text image by adopting an enhanced real-time scene text detection network; recognizing a text region by adopting a scene text recognition model, and detecting text defects; detecting label area image defects based on a gray scale matching method; and fusing the text image and the label area image to the original position, and marking the positions of the image defect and the text defect. According to the invention, the efficiency and precision of label defect detection are improved, the adaptability and robustness of the algorithm are significantly enhanced through the adaptive image acquisition module and the bimodal detection method, the requirements of high precision and high efficiency of modern industrial production are met, and the method has a wide application prospect.

The invention relates to the technical field of electronic design automation, and discloses a standard cell layout legalization method and system based on a graph theory constraint graph, and the method comprises the steps: building a bidirectional directed constraint graph based on an existing layout and a design rule, and building a directed edge between adjacent graph edges according to the design rule; traversing the constraint graph, detecting whether a directed edge which does not meet a constraint condition exists, and if so, identifying the directed edge as a constraint violation edge; for two end points of each constraint violation edge, searching a key path based on a depth-first search algorithm, and determining a maximum movable distance in combination with a greedy strategy; moving the endpoint to a legal position according to the critical path and the maximum movable distance, and updating the position of a related node in the constraint graph; and mapping the position changes of the nodes in the constraint graph back to the corresponding graph edges in the layout, and outputting the legalized layout, so that efficient and automatic repair of design rule violation is realized through the method, and the layout compliance rate and the area optimization effect are remarkably improved.

A method for data center switching fabric path emulation in an electronics design automation (EDA) environment includes generating emulated data center traffic. The method further includes, at a path emulation element, modifying the emulated data center traffic to emulate passing of the emulated data center traffic through a data center switching fabric. The method further includes outputting, by the path emulation element, the modified emulated data center traffic to an EDA emulator emulating an electronics design under test. The method further includes receiving and storing a response of electronics design under test to the modified emulated data center traffic.

The embodiment of the invention relates to the field of electronic design automation, and provides a method and equipment for electronic design automation. Boolean logic representing the circuit is logically optimized to obtain optimized Boolean logic. The Boolean logic is process mapped to obtain a netlist representing the circuitry. And performing netlist optimization on the netlist to obtain an optimized netlist. In response to determining that the optimized netlist is superior to the locally optimal netlist representing the circuit, the locally optimal netlist is replaced with the optimized netlist, and the optimized netlist is process mapped. In this way, the efficiency of logic synthesis can be significantly improved.

The invention relates to the technical field of electronic design automation, and provides a printed circuit board wiring method and device, equipment, a medium and a program, and the method comprises the steps: classifying an obstacle as a pushable object or a non-pushable object; based on the relative position relationship between the initial path and the pushing object, constructing a geometric occupied area of the pushing object, and performing path offset on the pushing object according to the geometric occupied area; in the deviation process, if the distance between any deviated object capable of being pushed and any deviated object not capable of being pushed is smaller than a preset safety distance, further deviation is stopped, and the deviated object capable of being pushed is reversely returned along the deviation track of the object until the distance between the object capable of being pushed and the object not capable of being pushed is larger than or equal to the safety distance; and re-planning a final path of the signal line according to the position of each pushable object after returning, and outputting a wiring result according with a wiring rule. The method is used for optimizing and completing signal path optimization and distribution in an environment with obstacles.

A method of designing a programming and / or emulation tool for a processor includes developing a single model of the processor from a group including: the processor; hardware description of the processor; and a specification of the processor that is confirmed to represent the processor and / or hardware description; and automatically generating, by the electronic design automation tool, a programming and / or simulation tool of the processor from the single model of the processor and the set of design parameters. The method also includes validating a programming and / or emulation tool of the processor using the one or more validation applications and the reference entity.

The invention relates to the technical field of electronic design, and discloses a bit stream verification method and device, equipment, a storage medium and a program product.The bit stream verification method comprises the steps that an execution file corresponding to a target test case is executed, and a bit stream file and a routing file of the target test case are obtained; determining configuration information of the target test case based on the bit stream file and the routing file, and configuring a test file of the target test case based on the configuration information; based on the routing file, configuring an input signal and a reference model corresponding to the target test case; and based on the input signal, respectively testing the test file and the reference model, and determining a bit stream verification result of the target test case. Thus, simulation verification of the bit stream file of the target integrated circuit is deconstructed, simulation verification of the bit stream file is performed on each test unit in the target integrated circuit, simulation verification of the bit stream file is realized through the reference model, simulation of the bit stream file is simplified, simulation efficiency of the bit stream file is further improved, and simulation time is shortened.

The invention provides a DFT process monitoring method and device, electronic equipment and a storage medium, and belongs to the technical field of DFTs. The DFT process monitoring method comprises the steps that in response to monitoring that execution of a current test task is finished, a process state and a current log file generated in the process of executing the current test task are obtained; determining a target predefined analysis rule corresponding to the type of the EDA tool adopted for executing the current test task through a mapping relation between the type of the EDA tool and the predefined analysis rule; analyzing the current log file through a target predefined analysis rule to obtain semantic keywords; and determining a final execution state of the current test task based on the process state and the semantic keyword. According to the scheme, massive unstructured log files generated by different EDA tools can be analyzed, and the final execution state of each test task can be determined.