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663 results about "Design specification" patented technology

A Product design specification is a detailed document providing information about a designed product or process. For example, the design specification must include all necessary drawings, dimensions, environmental factors, ergonomic factors, aesthetic factors, maintenance that will be needed, etc. It may also give specific examples of how the design should be executed, helping others work properly (a guideline for what the person should do).

Method of constructing fine discrete road grid in urban drainage simulation system

InactiveCN103399990ARealize the expression of micro-topographic featuresBuild accuratelySpecial data processing applicationsTerrainMathematical model
The invention relates to a method of constructing a fine discrete road grid in an urban drainage simulation system and belongs to the cross field of municipal engineering information technology, database technology and geologic information system technology. From the demand on construction of a waterlogging simulation model, under the restraint conditions in road design specifications and on the basis of conventional map measured elevation points, the number and positions of interpolation points are optimized under the drainage simulation system platform by the fitting method of local elevation change curves of cross-longitudinal road section and by road characteristic terrain vector layers according to mathematical model interpolation encryption plane and elevation information of physical road tomography; accordingly, a fine discrete road elevation grid unit is constructed, true tomographic road features are expressed quickly and economically, the demand on precise simulation of waterlogging models is met, especially the dredging and resisting actions of road micro-tomographic features upon waterflow can be correctly expressed, and the method is significant to promotion and application of the drainage simulation technology.
Owner:BEIJING UNIV OF TECH

Extraction and modeling method for Chinese speech sensibility information

The invention provides a method for extracting and modeling the emotional information of a Chinese sound; the extracting method for the emotional information of the Chinese sound is that: formulate the specification of a emotional speech database, which includes the pronouncer specification, the recording play book design specification and the naming specification of audio files and so on; collect the emotional speech data; evaluate the validity of the emotional speech, namely, at least ten evaluators apart from a speaker carry out a subjective listen evaluation experiment on the emotional speech data. The modeling method of the emotional information of the Chinese sound is that: extract the emotional characteristics of the sound, define and distinguish the characteristic combination of each emotion type; adopt different characteristic combinations to train the SVM model of a multilevel sound emotion recognition system; verify the identification effect of the classifying models, namely, verify the classification effect of the multilevel classification models of sound emotion in a situation unrelated to the speaker by adopting a cross leave-one-out method. The method solves the problems that the domestic emotional speech databases are less in emotion type and the number of the domestic emotional speech database is very limited; at the same time, the method realizes an efficient speech emotion identification system.
Owner:BEIHANG UNIV

Bidirectional punching method for underground excavation of subway station

The invention provides a bidirectional punching method for underground excavation of a subway station. A light-section five-layer channel is arranged at the middle part of the station and runs through the station horizontally; the excavation is carried out from the middle part to the two sides of the station; and with adopting of a layering excavation mode and a crossed and segmented excavation mode as well as necessary preliminary bracing construction measures, the variation, caused by large-area multi-direction excavation, of surrounding rock stress around pilot tunnels can be distributed reasonably, the influences of surrounding soil bodies on the excavation among the different pilot tunnels are alleviated, a multi-cavity effect is prevented, and the top arch settling and lateral convergence and deformation in preliminary bracing of the pilot tunnels are alleviated so as to ensure that the preliminary bracing deformation of the pilot tunnels can meet design specification requirements; and meanwhile, the pilot tunnels can be excavated in advance at the middle part of the station, and can be excavated synchronously with the symmetrical excavation of air ducts toward the station direction, so that the integral preliminary bracing construction period of the station can be shortened by half, and comprehensive economic and social benefits are obvious.
Owner:中铁城建集团第三工程有限公司 +1

Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization

An innovative hardware / software design tool provides four modes of operation for converting an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. The first mode of operation compiles design and logic technology specifications into a model which can be utilized for behavioral analysis (such as simulation or formal verification) of logical characteristics (the model). The second mode of operation translates (compiles) partitions of the design and one or more logic technologies into one or more processor intermediates or binaries (embedded binary) suitable for execution on multi-purpose processing units (embedded or general purpose processors). The third mode of operation translates (synthesizes) partitions of the design and logic technology into a collection of cells and interconnects (net-list implementation) suitable for input to physical design processes such as is required to target a field-programmable logic array (FPGA), application specific integrated circuit (ASIC), system-on-a-chip (SOC) or custom logic). The fourth mode of operation analyzes (verifies) behavior of the embedded binaries running on processing units and implementations augmented by additional physical technology and parameters, yielding a more detailed (accurate) prediction of the resulting hardware / software system behavior when realized through manufacturing. Critically, the design specification, logic specifications, physical specifications and definition of each multi-purpose processing unit may be defined external to the hardware / software design tool using an innovative augmentation of standard hardware description or programming languages taught in this patent application. In the prior art, specification of the logic technology, physical technology and embedded or general purpose processor architecture are either incorporated directly into the design tool by the tool developer or are maintained entirely external to the design tool (such as an encapsulated component model or intermediate code interpreter). The present invention is an innovative and valuable improvement over prior art in that design specifications are combined by the tool from distinct specification(s) of generalized logic, physical and processor technology, leading to more efficient behavioral design, opportunities for third parties to add functionality by incorporating generalized logic and physical technology modules into the analysis and synthesis process and opportunities for semi-automatic, goal-directed optimization through application of various logic, physical and processor technologies by the design tool.
Owner:FTL SYST

Simplified process to design integrated circuits

A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I / O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and / or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.
Owner:BELL SEMICON LLC

Full three-dimensional digital knowledge base system and application method of knowledge base

The invention discloses a full three-dimensional digital knowledge base system and an application method of a knowledge base. The knowledge base system comprises a flow control module, a specific knowledge design module, an interaction control module, an equation editing module, a search control module, a computing control module and a knowledge base small functional module and is an independent knowledge driving system capable of being hung on different CAD (Computer-Aided Design). The application method of the knowledge base can be applied to various fields such as products, processes, tool design, product inspection and the like in the mechanism manufacture industry. A designer expresses knowledge such as purposes, industry design specifications, standard manuals, design experience, computational formulas and the like through an open programming-free visual knowledge editing function and stores the knowledge into the knowledge base, a database and a model base for reusing; and wizard design is realized through parameter passing, data acquisition and interaction and platform interaction. The system has the advantages of strong generality, convenience and rapidness, no leakage of enterprise core technology experience knowledge and the like and provides means for technical innovation and knowledge and experience accumulation.
Owner:西安易博软件有限责任公司

Suite of tools to design integrated circuits

A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.
Owner:BELL SEMICON LLC
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