244 results about "General purpose" patented technology

Disclosed is a method and tidying robot system that performs it. A robot of a tidying robot system receives a starting location, a target cleaning area, and obstructions in its path navigating the target cleaning area. It determines a tidying strategy including vacuuming and obstruction handling. It executes the tidying strategy, vacuuming the target cleaning area and moving and / or avoiding obstructions, which are tidyable and / or movable objects. Where the obstruction may be picked up, the robot determines and executes a pickup strategy. Where the obstruction may be relocated but not picked up, it pushes the obstruction to a different location. Where the obstruction cannot be relocated / picked up, it alters its path to avoid the obstruction. The robot determines if the dirt collector is full, and if so, navigates to a base station configured to charge the robot and empty the dirt collector. Otherwise, it continues to execute the tidying strategy.

The invention relates to the technical field of GPGPU (General Purpose Graphics Processing Unit), and relates to an SIMT stack and thread scheduling optimization method and device for GPGPU (General Purpose Graphics Processing Unit) branch instructions, a medium and a GPGPU architecture. The method comprises the steps that in a GPGPU, an SIMT stack is optimized, an SM unit is expanded to be a double-instruction assembly line, and a main thread beam scheduler and an auxiliary thread beam scheduler are arranged. And in a non-branch state, half threads of each tube of the scheduler are executed in parallel by the assembly line. When a branch instruction is encountered, instruction addresses, thread masks and branch reunion points of the two branch paths are pressed into the SIMT stack. Judging conflicts according to the thread masks; if conflicts exist, performing serial execution; and if no conflict exists, executing on double pipelines in parallel. And when the branch is completed to a reunion point, the SIMT stack pops up an entry, and the execution is continued. The method has remarkable effects in the aspects of improving the thread resource utilization rate, improving the calculation efficiency, simplifying the branch control complexity, enhancing the GPGPU flexibility and the like.

The invention provides a parallel optimization method and system for a GPGPU (General Purpose Graphics Processing Unit) instruction execution stage, and the method comprises the steps: splitting an input instruction into a plurality of sub-instructions which can be independently scheduled based on an instruction type, operand dependency analysis and a hardware resource real-time state, and generating a dependency table to record the input and output association of the sub-instructions; acquiring real-time load data of the calculation unit, the storage unit and the communication unit, and distributing the sub-instructions to the calculation unit, the storage unit or the communication unit by adopting a priority dynamic adjustment algorithm and combining instruction key path analysis; according to the dependency relationship of the sub-instructions and the availability of hardware resources, the execution sequence of the sub-instructions is adjusted to maximize the degree of parallelism; and analyzing the dependency relationship among the sub-instructions in real time to maximize the degree of parallelism to dynamically adjust a parallel execution strategy so as to realize serial execution of dependent instructions and parallel execution of non-dependent instructions. According to the method, the complexity of instruction compiling is reduced, the efficiency of instruction compiling is improved, and meanwhile extra consumed time is reduced.

The invention discloses an inter-thread operand collection strategy and an application system, and relates to the technical field of cross-thread data sharing of a GPGPU (General Purpose Graphics Processing Unit). In order to solve the problems of read-write delay and cache occupation caused by synchronous operation of the GPGPU in a data sharing scene, the scheme adopted by the invention comprises a decoding unit, a transmitting unit and a write-back unit, and the three units cooperate with one another to form a complete cross-thread data read-write path. Wherein the decoding unit is responsible for decoding a self-defined instruction and remapping a thread index; the transmitting unit undertakes the tasks of instruction caching, data synchronization control and cross-thread data reading; and the write-back unit is responsible for writing an instruction execution result back to the storage space and updating the state of a related register. According to the method, the parallel performance of the GPGPU in a multi-thread parallel computing scene can be improved.

The invention discloses a path decision-making method for optimizing the punctual arrival probability in combination with a Decision Transform and a GPG (General Purpose Graphics). The method comprises the following steps: acquiring a vehicle initial path data set; constructing a vehicle path decision model based on a Decision Transform, and obtaining probability distribution of vehicle path node selection by using the vehicle initial path data set and the vehicle path decision model to generate a vehicle prediction path; and calculating a strategy gradient by taking the punctual arrival probability as an optimization target based on the vehicle predicted path and the GPG, carrying out back propagation training on the vehicle path decision model by utilizing the strategy gradient, and carrying out vehicle path decision by utilizing the vehicle path decision model. According to the method, the problem that spatial correlation modeling is insufficient in the prior art can be solved, the accuracy and stability of path decision making are improved, meanwhile, dependence on priori knowledge can be reduced in the optimization decision making process, and then the punctual arrival probability of optimization path decision making can be achieved.

A GPI device includes a communication port for receiving a GPI signal from a first device, one or more processors; and a memory comprising program instructions. The program instructions, when executed by the one or more processors, cause the GPI device to assign a command to the GPI signal when the GPI device receives the GPI signal from the first device and transmit the command to a second device. The transmission of the command may be triggered by the received GPI signal. The command may include a script, such as a python script. The command may also include triggering transmission of a live broadcast, switching between graphics during the live broadcast, or a combination thereof.

To improve utilization of a systolic array, each row of the array is provided with two or more general purpose row input buses. Each of the general purpose row input data buses can be operable to transfer either feature map (FMAP) input elements or weight values into the processing elements of the corresponding row of the array. The flexibility of the general purpose row input buses allows weights to be loaded in parallel into the array to speed up weight loading times to reduce the overall latency.

Some implementations relate to receiving input data; generating, using a low-rank representation of a machine-learned generative model, a generative output from the input data; determining, based on a machine-learned reward model, a corresponding reward from the generative output, and updating, based on the corresponding reward, one or more parameters of the low-rank representation of the machine-learned model. Further, some additional or alternative implementations relate to receiving input data associated with a client device; generating, using a general purpose agent, responsive content to the input data, wherein the general purpose agent is configured based on a machine-learned generative model and a low-rank representation of the machine-learned generative model; and causing the client device to render the responsive content.

An anomalous scenario synthesizer apparatus includes a rotatable shaft configured to be rotationally driven about a rotation axis, a data acquisition system operably associated with the rotatable shaft and configured to measure attributes of the rotatable shaft, and a dynamic anomaly generator operably connected to the rotatable shaft. The dynamic anomaly generator is configured to generate at least one anomaly in the rotatable shaft while the rotatable shaft is rotating, and is configured to generate at least one dynamic label for each anomaly while the rotatable shaft is rotating. The dynamic label for each anomaly includes at least one descriptor corresponding to the anomaly that describes the anomaly such that a machine learning method may utilize the descriptor for machine learning.

The invention provides a computer system based on a multi-agent reinforcement learning network and a network optimization method, and relates to the technical field of deep reinforcement learning. The computer system based on the multi-agent reinforcement learning network comprises a strategy network module used for receiving local state information and capability vectors corresponding to target agents, processing the local state information and the capability vectors and outputting probability values of action information corresponding to the target agents, the local state information comprises observation information of at least two other agents except the target agent, and the observation information is sequentially input to the strategy network module in a parallel stacking mode; and the value network module is used for receiving the global state information or the local state information corresponding to the target agent, and obtaining the long-term value information corresponding to the target agent according to the global state information or the local state information, so as to optimize the strategy network module and the value network module. According to the invention, the universality of a network algorithm can be improved.

A GPI device includes a communication port for receiving a GPI signal from a first device, one or more processors; and a memory comprising program instructions. The program instructions, when executed by the one or more processors, cause the GPI device to assign a command to the GPI signal when the GPI device receives the GPI signal from the first device and transmit the command to a second device. The transmission of the command may be triggered by the received GPI signal. The command may include a script, such as a python script. The command may also include triggering transmission of a live broadcast, switching between graphics during the live broadcast, or a combination thereof.

A cleaning system and a method of cleaning are provided. The cleaning system comprises a liquid comprising 4-50 wt % glyceride wherein the glyceride is the condensation reaction product of at least 1.10 moles of a mixture of acids to no more than 2.1 moles of the mixture of acids per mole of glycerin. The mixture of acids comprises at least 0.275 to no more than 0.990 moles of a first acid comprising a branched acid with 16-20 aliphatic carbons; at least 0.250 to no more than 0.810 moles of a second acid comprising an alkyl acid with 9-11 carbons and at least 0.250 to no more than 0.810 moles of a third acid comprising an alkyl acid with 7-9 carbons. The third acid has a lower molecular weight than the second acid. The cleaning system also has 6-45 wt % surfactant, optionally up to 90 wt % cleaning agent and up to 90 wt % solvent. The liquid has a BYV of at least 50 dyn / cm2.

The invention provides a general purpose computing unit and computing equipment. The general-purpose computing unit comprises a plurality of execution units, wherein each execution unit is used for executing an operation instruction by taking a thread bundle as a unit; and a thread local register for each execution unit, including a plurality of thread beam registers allocated for a plurality of thread beams run by the execution unit, the plurality of thread beam registers being non-overlapping, where the thread local register further includes a shared register shared by the plurality of thread beams.

Disclosed is a method and tidying robot system that performs it. A robot of a tidying robot system receives a starting location, a target cleaning area, and obstructions in its path navigating the target cleaning area. It determines a tidying strategy including vacuuming and obstruction handling. It executes the tidying strategy, vacuuming the target cleaning area and moving and / or avoiding obstructions, which are tidyable and / or movable objects. Where the obstruction may be picked up, the robot determines and executes a pickup strategy. Where the obstruction may be relocated but not picked up, it pushes the obstruction to a different location. Where the obstruction cannot be relocated / picked up, it alters its path to avoid the obstruction. The robot determines if the dirt collector is full, and if so, navigates to a base station configured to charge the robot and empty the dirt collector. Otherwise, it continues to execute the tidying strategy.

An electronic device is provided. The electronic device includes a communication circuitry, memory storing one or more computer programs, and one or more processors operatively connected to the communication circuitry and the memory, wherein the one or more computer programs include computer-executable instructions that, when executed by the one or more processors indivudally or collectively, cause the electronic device to establish at least one multimedia broadcast and multicast service (MBMS) subchannel with a mission critical push to talk (MCPTT) server, and, while the at least one MBMS subchannel has been established, sends a message related to switching to a unicast method, to the MCPTT server, if the reception delay time of a control message related to the MBMS subchannel received through a general purpose MBMS subchannel (GPMS) satisfies a specified first switching condition.

A GPI device includes a communication port for receiving a GPI signal from a first device, one or more processors; and a memory comprising program instructions. The program instructions, when executed by the one or more processors, cause the GPI device to assign a command to the GPI signal when the GPI device receives the GPI signal from the first device and transmit the command to a second device. The transmission of the command may be triggered by the received GPI signal. The command may include a script, such as a python script. The command may also include triggering transmission of a live broadcast, switching between graphics during the live broadcast, or a combination thereof.

A coordinated control system designed with a small form factor that can be located within a robot or an automated inline manufacturing system, comprising: an on board advanced distributed control hardware configured with artificial intelligence enabled processors incorporated within a System on Module (SOM) board, each SOM comprising four processors or nodes; interfaced with a cameras, motors, general purpose I / O through I2C expander, audio interface, Internet, wireless communication such as WiFi and Bluetooth to send and receive commands and any other data; electrically connected to a plurality of sensors for perceiving the environment and collecting data from infrared, tactile, proximity and other types of sensors; an external host flashing computer dedicated for uploading / downloading firmware, cloning and configuration setup; a non-volatile memory for storing control algorithms, configuration files and other essential data; a HDMI based user interface for robot operation, training and setup; USB C or Ethernet based internal star network for high-speed communication bypassing the standard PCI bus interface bus; an Ethernet switch board enabling multiple boards to access the Ethernet for both internal communication within the star network as well as external Internet access.

A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

A new approach is proposed that contemplates system and method to support a new network architecture for secure AI computing based on one or more secure, multi-core (SMC) data processing units (DPUs). Each of the SMC DPUs includes a gateway that ensures a secure interface and operating environment for the SMC DPU through encryption. Each of the SMC DPUs may further include a microprocessor core, one or more general purpose processing units (XPU cores) and / or customized processing units (CXPU cores), and a communications interface (COMM I / F) to external memories and other processing units. In some embodiments, a secure AI cloud cluster is constructed using multiple SMC DPUs along with one or more of switches, memories, separate XPUs, and high-speed interconnects (including optical interconnects) to ensure protection of client data for cloud-based AI services.

The utility model relates to the technical field of shell punching dies, and discloses a universal type shell punching male die, a shell punching female die and a shell punching die, the universal type shell punching male die comprises a male die base plate and a male die core, the male die base plate which is originally designed in an integrated mode is improved to be designed in a split mode, namely the universal type shell punching male die comprises a male die base plate body and a male die base block, then, the male die base block is designed to be movably arranged in the first mounting cavity of the male die base plate body, so that the male die base block can be matched with the first mounting cavity to form a first penetrating through hole through which the male die core can penetrate, and when male die cores of different sizes need to be used for manufacturing punching pits of different sizes, the male die core can be inserted into the first penetrating through hole; compared with the prior art, male die cores with different sizes can be adapted only by utilizing relative movement of the male die base block and the male die base plate body and changing the size of the first penetrating through hole, so that the purpose that the die is universal is achieved, the die opening cost can be saved, the die opening period is shortened, and production and popularization of the soft package battery are facilitated.

The utility model discloses a general purpose interface bus (GPIB) adapter plate structure, which relates to the technical field of GPIB adapter plates, and aims to solve the problems that the adapter plate is easy to be damaged and the use is influenced after the adapter plate is collided due to the lack of a protective structure on the outer side of the conventional GPIB adapter plate, and the key point of the technical scheme is that the GPIB adapter plate structure comprises a GPIB adapter plate main body, a bottom plate is arranged on the outer side of the GPIB adapter plate body, a supporting column is fixedly connected to one end of the outer side of the bottom plate, a cover plate is arranged on the outer side of the supporting column, a side plate is fixedly connected to one end of the outer side of the cover plate, a mounting block is fixedly connected to the other end of the outer side of the bottom plate, and a threaded hole is formed in the mounting block. And a screw is inserted into the GPIB adapter plate main body. And the effects of convenient use and protection are achieved.

A coordinated control system designed to have a small form factor can be located within a robotic or automated online manufacturing system, the coordinated control system comprising: on-board advanced distributed control hardware configured with artificial intelligence enabled processors incorporated within a System-on-Module (SOM) board, each SOM comprising four processors or nodes; wireless communication with cameras, motors, general purpose I / O via I2C extenders, audio interfaces, the Internet, such as Wifi and Bluetooth connections, for transmitting and receiving commands and any other data; a sensor electrically connected to a plurality of sensors for perceiving an environment and collecting data from infrared, haptic, proximity and other types of sensors; the external host flash memory computer is specially used for uploading / downloading firmware, cloning and configuring; the nonvolatile memory is used for storing a control algorithm, a configuration file and other necessary data; the HDMI-based user interface is used for robot operation, training and setting; the internal star network based on USB C or Ethernet is used for bypassing the standard PCI bus interface BUS to carry out high-speed communication; an Ethernet switch enables a plurality of boards to access the Ethernet for internal communication within the star network as well as external Internet access.

1. Name of the product in this design: General Purpose Transmitter. 2. Application of this design: for gas and liquid measurement, residential water supply, and humidifier control. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key features: the front view.

To provide a printing system, an information processing apparatus, a control method, and a program that implement color adjustment function, which is a function unique to a manufacturer, in printing using general purpose printing software.SOLUTION: A host computer 101 includes a standard driver, and an extended application which extends functions of the standard driver for implementing color adjustment function unique to a manufacturer. The extended application is configured to: add a control to receive settings for the color adjustment function from a user, to a detailed setting screen generated by the standard driver; and convert, when the host computer 101 is connected to a printer 102 having a color adjustment module that uses the color adjustment function to perform color adjustment processing on print data, based on the settings for the color adjustment function received by the control, intermediate data generated by the standard driver into print data for which the color adjustment processing can be performed by the printer 102.SELECTED DRAWING: Figure 8

1. Name of the product in this design: General Purpose Pulse Power Supply. 2. Purpose of this design: To integrate supercapacitor modules with general-purpose power supplies to achieve energy storage and power conversion. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: 3D view 1.

The universal maintenance dock comprises a maintenance assembly and an aisle assembly, the maintenance assembly comprises a first supporting frame and a maintenance platform, the first supporting frame is provided with a first lifting mechanism, a plurality of first trundles are arranged at the bottom of the first supporting frame, and the maintenance platform is arranged at the top end of the first lifting mechanism; the aisle assembly comprises a second supporting frame and an aisle platform, a second lifting mechanism and a third lifting mechanism are arranged at the two ends of the second supporting frame respectively, a plurality of second trundles are arranged at the bottom of the second supporting frame, and the top end of the second lifting mechanism is rotationally connected to one end of the aisle platform; the top end of the third lifting mechanism is hinged to the other end of the aisle platform, the ends, close to each other, of the aisle platform and the maintenance platform are hinged to each other, and the aisle platform can be adjusted in a telescopic mode in the length direction. According to the universal maintenance dock, airplanes of different models can be maintained, and the practicability is better.

An apparatus utilized for security testing one or more electronic control units (ECUs) includes a memory unit configured to store one or more instructions, a controller configured to execute one or more instructions, a control network interface in communication with the controller and that is configured to communicate instructions received from one or more control networks, a breakout interface configured to send one or more instructions to the one or more ECUs, a automotive network interface configured to communicate with one or more automotive networks, a general purpose input-output (GPIO) breakout interface including a plurality of GPIO pins configured to send signals to control functionality of the apparatus, a power interface configured to supply variable power to the one or more ECUS, and one or more debug interfaces configured to allow communication between a debugger and the one or more ECUs as associated with security testing.

The utility model relates to the field of lithium ion battery preparation, and discloses an ion battery which comprises a shell, a battery pack body, a battery management system module and a plug assembly, the battery pack body and the battery management system module are packaged in the shell, a cavity position with an outward opening is arranged on the shell, and the plug assembly is arranged in the cavity position. A positive copper sheet and a negative copper sheet of the battery management system module are located on the side of the cavity position, the plug assembly is used for being connected with an external plug in an inserted mode so as to discharge outwards or charge the battery pack body, and the plug assembly is detachably installed in the cavity position. The front surfaces of a positive copper plate and a negative copper plate of the plug assembly are respectively fastened and attached to the back surfaces of a positive copper sheet and a negative copper sheet of the battery management system module, and an external plugging part of a plug of the plug assembly is positioned at the opening of the cavity position for external plugging. By applying the technical scheme, the universality of a battery product is improved.

To provide technique capable of evaluating an influence of a content more accurately and generally.SOLUTION: A first keyword extraction unit 61 extracts first keywords included in first content information on the basis of first keyword information stored in a first keyword DB 200. On the basis of second keyword information stored in a second keyword DB 300, the first keyboard extraction unit extracts a second keyword corresponding to each of the first keywords extracted by the first keyword extraction unit 61. A second keyword extraction unit 64 extracts the first and second keywords included in second content information. An influence calculation unit 65 calculates an influence of the second keyword in the second content on the basis of a predetermined rule. An influence presentation unit 66 transmits result information related to the influence of the second keyword calculated by the influence calculation unit 65 to a service providing terminal 4.SELECTED DRAWING: Figure 3

The invention provides a hybrid heterogeneous system and a signal processing method thereof, and relates to the field of satellite-borne intelligent load processing. The system comprises: a first hybrid hardware module comprising: a first programmable logic device unit; a first general purpose processor unit; a first neural network accelerator unit; a first switching network unit; wherein communication signals are transmitted between any two units of the first programmable logic device unit, the general processor unit and the first neural network accelerator unit by adopting a PCIe bus or a first switching network unit. The first programmable logic device unit, the first general processor unit and the first neural network accelerator unit are integrated, and communication signals can be transmitted between any two units through the PCIe bus or the first switching network unit. The problems that an existing processing system is low in processing speed, large in time delay, lack of application flexibility and insufficient in computing power can be solved.