379 results about "General purpose" patented technology

Disclosed is a method and tidying robot system that performs it. A robot of a tidying robot system receives a starting location, a target cleaning area, and obstructions in its path navigating the target cleaning area. It determines a tidying strategy including vacuuming and obstruction handling. It executes the tidying strategy, vacuuming the target cleaning area and moving and / or avoiding obstructions, which are tidyable and / or movable objects. Where the obstruction may be picked up, the robot determines and executes a pickup strategy. Where the obstruction may be relocated but not picked up, it pushes the obstruction to a different location. Where the obstruction cannot be relocated / picked up, it alters its path to avoid the obstruction. The robot determines if the dirt collector is full, and if so, navigates to a base station configured to charge the robot and empty the dirt collector. Otherwise, it continues to execute the tidying strategy.

The invention discloses an instruction execution acceleration method based on a GPGPU and a GPGPU architecture, and relates to the field of high-performance computation.The method comprises the steps that a thread execution task output by a host compiler is received, and the thread execution task is scheduled according to the current idle state of a computing unit; capturing instruction data output by the host compiler, and executing concurrent instruction decoding according to the corresponding instruction type to obtain a machine code corresponding to the instruction data; obtaining an operand corresponding to the instruction data, and generating a to-be-transmitted instruction based on the machine code corresponding to the instruction data and the operand after secondary verification; according to the calculation complexity, determining an optimal calculation unit, and sending the to-be-launched instruction to the optimal calculation unit; and receiving an execution result of the to-be-transmitted instruction, and returning the execution result to the terminal. The thread execution task is dynamically scheduled according to the idle state of the computing unit, so that computing resources can be fully utilized, and the operation efficiency is improved.

Precise nerve detection during surgery is crucial for safe operational outcomes, which largely depend on the surgeon's skills. Therefore, automatic real-time identification of anatomical structures is of great importance. However, image processing times must be kept as low as possible to be a viable solution for real-time visual identification. By using a general purpose graphics processing unit (GPGPU) implementation for birefringence mapping, the process can achieve rates of 43 frames per second (FPS); a 118×gain from a CPU implementation. Furthermore, by including a deep learning network, the complete framework can automatically detect nerves close to 12 FPS. By leveraging GPU for the processing task, the framework can run on compact devices with NVIDIA modules, such as Jetson Xavier AGX, while still achieving reasonably fast nerve identification and visualization.

The invention provides an indoor and outdoor universal nail-free sports wood floor. The indoor and outdoor universal nail-free sports wood floor is characterized by comprising floor modules, leveling hole plugging plates and elastic eccentric supports; the elastic eccentric supporter is arranged on the base layer and is connected with and supports the floor module and the leveling hole plugging plate; the device can be used as a permanent facility to be mounted in indoor and outdoor open places of a building, and is suitable for outdoor places such as concrete places with large height difference and large inclination angle, square marble places, roofs and the like through the rotation of the elastic eccentric shaft seat around a shaft within a certain range; compared with the prior art, the structure is simple, no nail is used for connection and fixation, rapid and accurate leveling can be achieved without a leveling cushion block, the material cost and the installation cost are low, the overall use and maintenance cost is low, and large-scale application and popularization are facilitated.

The invention relates to the technical field of GPGPU (General Purpose Graphics Processing Unit), and relates to an SIMT stack and thread scheduling optimization method and device for GPGPU (General Purpose Graphics Processing Unit) branch instructions, a medium and a GPGPU architecture. The method comprises the steps that in a GPGPU, an SIMT stack is optimized, an SM unit is expanded to be a double-instruction assembly line, and a main thread beam scheduler and an auxiliary thread beam scheduler are arranged. And in a non-branch state, half threads of each tube of the scheduler are executed in parallel by the assembly line. When a branch instruction is encountered, instruction addresses, thread masks and branch reunion points of the two branch paths are pressed into the SIMT stack. Judging conflicts according to the thread masks; if conflicts exist, performing serial execution; and if no conflict exists, executing on double pipelines in parallel. And when the branch is completed to a reunion point, the SIMT stack pops up an entry, and the execution is continued. The method has remarkable effects in the aspects of improving the thread resource utilization rate, improving the calculation efficiency, simplifying the branch control complexity, enhancing the GPGPU flexibility and the like.

The invention discloses a key thread bundle scheduling method and device, and relates to the technical field of GPGPU (General Purpose Graphics Processing Unit), a thread bundle which is executed in sequence and a thread bundle which is branched are scheduled at different frequencies, different scheduling schemes are appointed for the two types of thread bundles in the mode, the parallel performance of the sequence thread bundle is ensured not to be influenced to the greatest extent, and the scheduling efficiency is improved. And meanwhile, the operation of the branch thread bundles is accelerated, the problem that the operation time of the thread bundles is prolonged due to excessive thread branches is avoided, and the combining performance of the universal graphics processor is improved to a certain extent.

Embodiments of this application provide example computing chips and instruction processing method related to the field of integrated circuit technologies. One example computing chip uses a superscalar processor architecture, and includes an instruction processing unit and a plurality of registers that are separately coupled to the instruction processing unit. The plurality of registers include a general purpose register and a plurality of private registers that are separately coupled to the general purpose register. The general purpose register is configured to store an execution result of a microinstruction that is in a plurality of microinstructions of a computing task and that is executed before a jump instruction and whose execution result is referenced by a microinstruction that is executed after the jump instruction. Each private register in the plurality of private registers is configured to store an execution result of any microinstruction in the plurality of microinstructions.

The invention provides a parallel optimization method and system for a GPGPU (General Purpose Graphics Processing Unit) instruction execution stage, and the method comprises the steps: splitting an input instruction into a plurality of sub-instructions which can be independently scheduled based on an instruction type, operand dependency analysis and a hardware resource real-time state, and generating a dependency table to record the input and output association of the sub-instructions; acquiring real-time load data of the calculation unit, the storage unit and the communication unit, and distributing the sub-instructions to the calculation unit, the storage unit or the communication unit by adopting a priority dynamic adjustment algorithm and combining instruction key path analysis; according to the dependency relationship of the sub-instructions and the availability of hardware resources, the execution sequence of the sub-instructions is adjusted to maximize the degree of parallelism; and analyzing the dependency relationship among the sub-instructions in real time to maximize the degree of parallelism to dynamically adjust a parallel execution strategy so as to realize serial execution of dependent instructions and parallel execution of non-dependent instructions. According to the method, the complexity of instruction compiling is reduced, the efficiency of instruction compiling is improved, and meanwhile extra consumed time is reduced.

The invention discloses an inter-thread operand collection strategy and an application system, and relates to the technical field of cross-thread data sharing of a GPGPU (General Purpose Graphics Processing Unit). In order to solve the problems of read-write delay and cache occupation caused by synchronous operation of the GPGPU in a data sharing scene, the scheme adopted by the invention comprises a decoding unit, a transmitting unit and a write-back unit, and the three units cooperate with one another to form a complete cross-thread data read-write path. Wherein the decoding unit is responsible for decoding a self-defined instruction and remapping a thread index; the transmitting unit undertakes the tasks of instruction caching, data synchronization control and cross-thread data reading; and the write-back unit is responsible for writing an instruction execution result back to the storage space and updating the state of a related register. According to the method, the parallel performance of the GPGPU in a multi-thread parallel computing scene can be improved.

The invention discloses a GPGPU (General Purpose Graphics Processing Unit)-based singular value decomposition acceleration method and equipment, belongs to the technical field of computer technologies, and is used for solving the problems that when an SVD (Singular Value Decomposition) technology is applied to hardware, a relatively large calculation amount and a large amount of memory occupation can be caused, and different index strategies influence the parallel operation efficiency of the hardware, so that the hardware performance is poor. And the overall performance of hardware is reduced. The method comprises the steps of obtaining an index sequence of a to-be-decomposed matrix; generating a plurality of groups of index sequence pairs based on the index sequence; sending a kernel function kernel to the GPGPU, and traversing each group of index sequence pairs through each block in the kernel function kernel; decomposing matrix data corresponding to the first group of index sequences in the to-be-decomposed matrix through the queue in each block to obtain a first decomposed matrix; and decomposing matrix data corresponding to the second group of index sequences in the first decomposition matrix to obtain a second decomposition matrix, and so on until the last group of decomposition matrix is obtained, thereby obtaining a singular value decomposition result.

The invention discloses a path decision-making method for optimizing the punctual arrival probability in combination with a Decision Transform and a GPG (General Purpose Graphics). The method comprises the following steps: acquiring a vehicle initial path data set; constructing a vehicle path decision model based on a Decision Transform, and obtaining probability distribution of vehicle path node selection by using the vehicle initial path data set and the vehicle path decision model to generate a vehicle prediction path; and calculating a strategy gradient by taking the punctual arrival probability as an optimization target based on the vehicle predicted path and the GPG, carrying out back propagation training on the vehicle path decision model by utilizing the strategy gradient, and carrying out vehicle path decision by utilizing the vehicle path decision model. According to the method, the problem that spatial correlation modeling is insufficient in the prior art can be solved, the accuracy and stability of path decision making are improved, meanwhile, dependence on priori knowledge can be reduced in the optimization decision making process, and then the punctual arrival probability of optimization path decision making can be achieved.

A GPI device includes a communication port for receiving a GPI signal from a first device, one or more processors; and a memory comprising program instructions. The program instructions, when executed by the one or more processors, cause the GPI device to assign a command to the GPI signal when the GPI device receives the GPI signal from the first device and transmit the command to a second device. The transmission of the command may be triggered by the received GPI signal. The command may include a script, such as a python script. The command may also include triggering transmission of a live broadcast, switching between graphics during the live broadcast, or a combination thereof.

To improve utilization of a systolic array, each row of the array is provided with two or more general purpose row input buses. Each of the general purpose row input data buses can be operable to transfer either feature map (FMAP) input elements or weight values into the processing elements of the corresponding row of the array. The flexibility of the general purpose row input buses allows weights to be loaded in parallel into the array to speed up weight loading times to reduce the overall latency.

Aspects of the disclosed technology include techniques and mechanisms for using a custom scratchpad memory for partial dot product reductions. The custom scratchpad memory may be a special purpose memory that is dedicated to receiving and storing partial dot products determined by matrix multiplier units. Each partial dot product may correspond to tiles of a resultant matrix, where the resultant matrix is the product of matrix multiplication that can use a first matrix representing a user query as a left-hand side operand and a second matrix representing a trained model containing data that may be used to respond to the user query as a right-hand side operand. The custom scratchpad memory may append the tiles determined by the matrix multiplication, where the appended tiles may create the resultant matrix. Custom scratchpad memory may write the resultant matrix to general purpose memory, where it may be used to respond to the user query.

Some implementations relate to receiving input data; generating, using a low-rank representation of a machine-learned generative model, a generative output from the input data; determining, based on a machine-learned reward model, a corresponding reward from the generative output, and updating, based on the corresponding reward, one or more parameters of the low-rank representation of the machine-learned model. Further, some additional or alternative implementations relate to receiving input data associated with a client device; generating, using a general purpose agent, responsive content to the input data, wherein the general purpose agent is configured based on a machine-learned generative model and a low-rank representation of the machine-learned generative model; and causing the client device to render the responsive content.

The present invention provides an A-pillar bracket for vehicles with improved wiring assembly capable of being used for general purposes, by installing a pair of rotating pieces formed to rotate facing each other on two supports formed to face each other so that each rotating piece is rotatable in place, where each of the rotating pieces is configured to adjust a rotation angle twice by forcibly rotating with respect to the support, thereby stably supporting and fixing wiring even when the thickness of the wiring fixed and supported by the A-pillar bracket becomes thicker. In particular, the present invention provides an A-pillar bracket for vehicles with improved wiring assembly capable of more stably supporting and fixing wiring even when the thickness of the wiring changes by forming a pressing protrusion on at least one of two rotating pieces and configuring a portion wrapping the wiring in an arc shape.

The invention discloses a GPGPU thread block synchronization method and device based on a thread lock and a medium, and relates to the technical field of electric digital data processing. The method comprises the following steps: a thread block scheduling module allocates thread blocks for each stream multiprocessor and calculates a thread start ID (Identity) to maintain a corresponding thread lock table; analyzing whether a dependency relationship exists between the memory access request and a thread in the currently occupied thread block or not under the condition that the memory access requirement exists, and if yes, adding the memory access request with the dependency relationship to a lock queue; querying a thread lock state of a thread having a dependency relationship with the memory access request in a corresponding thread lock table so as to add the thread lock state to an entry state corresponding to the lock queue; and dequeuing the memory access request from the lock queue under the condition that the entry states of all the threads with the entries in the lock queue and the thread bundle having the dependency relationship are unlocked, and performing memory access according to the memory access request to realize synchronization of GPGPU thread blocks.

A method and system for providing an intermediary AI model that interfaces with a general purpose generative AI engine (e.g., a chatbot) that improves interface with the general-purpose AI in a domain-specific environment. The intermediary AI makes use of user specific information, user preferences, domain-specific concerns, trends, and makes use of a feedback loop to improve the operation thereof.

An anomalous scenario synthesizer apparatus includes a rotatable shaft configured to be rotationally driven about a rotation axis, a data acquisition system operably associated with the rotatable shaft and configured to measure attributes of the rotatable shaft, and a dynamic anomaly generator operably connected to the rotatable shaft. The dynamic anomaly generator is configured to generate at least one anomaly in the rotatable shaft while the rotatable shaft is rotating, and is configured to generate at least one dynamic label for each anomaly while the rotatable shaft is rotating. The dynamic label for each anomaly includes at least one descriptor corresponding to the anomaly that describes the anomaly such that a machine learning method may utilize the descriptor for machine learning.

The invention provides a computer system based on a multi-agent reinforcement learning network and a network optimization method, and relates to the technical field of deep reinforcement learning. The computer system based on the multi-agent reinforcement learning network comprises a strategy network module used for receiving local state information and capability vectors corresponding to target agents, processing the local state information and the capability vectors and outputting probability values of action information corresponding to the target agents, the local state information comprises observation information of at least two other agents except the target agent, and the observation information is sequentially input to the strategy network module in a parallel stacking mode; and the value network module is used for receiving the global state information or the local state information corresponding to the target agent, and obtaining the long-term value information corresponding to the target agent according to the global state information or the local state information, so as to optimize the strategy network module and the value network module. According to the invention, the universality of a network algorithm can be improved.

A GPI device includes a communication port for receiving a GPI signal from a first device, one or more processors; and a memory comprising program instructions. The program instructions, when executed by the one or more processors, cause the GPI device to assign a command to the GPI signal when the GPI device receives the GPI signal from the first device and transmit the command to a second device. The transmission of the command may be triggered by the received GPI signal. The command may include a script, such as a python script. The command may also include triggering transmission of a live broadcast, switching between graphics during the live broadcast, or a combination thereof.

A cleaning system and a method of cleaning are provided. The cleaning system comprises a liquid comprising 4-50 wt % glyceride wherein the glyceride is the condensation reaction product of at least 1.10 moles of a mixture of acids to no more than 2.1 moles of the mixture of acids per mole of glycerin. The mixture of acids comprises at least 0.275 to no more than 0.990 moles of a first acid comprising a branched acid with 16-20 aliphatic carbons; at least 0.250 to no more than 0.810 moles of a second acid comprising an alkyl acid with 9-11 carbons and at least 0.250 to no more than 0.810 moles of a third acid comprising an alkyl acid with 7-9 carbons. The third acid has a lower molecular weight than the second acid. The cleaning system also has 6-45 wt % surfactant, optionally up to 90 wt % cleaning agent and up to 90 wt % solvent. The liquid has a BYV of at least 50 dyn / cm2.

Systems and methods for continuous monitoring of the behavior of animals, such as small rodents, are provided. Monitoring can include video, audio, and other sensor modalities. In one embodiment, the system can include cameras, arena design, environmental sensors, and ultrasonic sensors. The system uniquely provides a continuous long-term monitoring system suitable for mouse behavioral study. Further provided is a neural network based tracker configured for use with video data acquired by the monitoring system. 3 different neural network architectures have been tested to determine their performance on genetically diverse mice under varying environmental conditions. It has been observed that that an encoder-decoder segmentation neural network achieves high accuracy and speed with minimal training data. This general purpose neural network tracker can be easily extended to other experimental paradigms and even to other animals through transfer learning, thus forming a robust, generalizable solution for bio-behavioral research.

Systems, methods and apparatuses provide a disaggregated network operating system in which control plane and data plane components of the network operating system are distributed across a network controller and network elements. An information model describes a network element and identifies packet processing plug-ins executable by general purpose processors of the network element. The network controller uses the model to generate a packet pipeline program for execution by a programmable packet pipeline of the network element, and generates a list of packet processing plug-ins for handling offload conditions. The network controller transmits the packet pipeline program and list of packet processing plug-ins to the network element. The network element installs the packet pipeline program to the programmable packet pipeline and downloads the listed packet processing plug-ins. When the pipeline detects an offload condition, the pipeline forwards the network packet to the packet processing plug-in associated with the offload condition.

The invention provides a general purpose computing unit and computing equipment. The general-purpose computing unit comprises a plurality of execution units, wherein each execution unit is used for executing an operation instruction by taking a thread bundle as a unit; and a thread local register for each execution unit, including a plurality of thread beam registers allocated for a plurality of thread beams run by the execution unit, the plurality of thread beam registers being non-overlapping, where the thread local register further includes a shared register shared by the plurality of thread beams.

Disclosed is a method and tidying robot system that performs it. A robot of a tidying robot system receives a starting location, a target cleaning area, and obstructions in its path navigating the target cleaning area. It determines a tidying strategy including vacuuming and obstruction handling. It executes the tidying strategy, vacuuming the target cleaning area and moving and / or avoiding obstructions, which are tidyable and / or movable objects. Where the obstruction may be picked up, the robot determines and executes a pickup strategy. Where the obstruction may be relocated but not picked up, it pushes the obstruction to a different location. Where the obstruction cannot be relocated / picked up, it alters its path to avoid the obstruction. The robot determines if the dirt collector is full, and if so, navigates to a base station configured to charge the robot and empty the dirt collector. Otherwise, it continues to execute the tidying strategy.

An electronic device is provided. The electronic device includes a communication circuitry, memory storing one or more computer programs, and one or more processors operatively connected to the communication circuitry and the memory, wherein the one or more computer programs include computer-executable instructions that, when executed by the one or more processors indivudally or collectively, cause the electronic device to establish at least one multimedia broadcast and multicast service (MBMS) subchannel with a mission critical push to talk (MCPTT) server, and, while the at least one MBMS subchannel has been established, sends a message related to switching to a unicast method, to the MCPTT server, if the reception delay time of a control message related to the MBMS subchannel received through a general purpose MBMS subchannel (GPMS) satisfies a specified first switching condition.

A GPI device includes a communication port for receiving a GPI signal from a first device, one or more processors; and a memory comprising program instructions. The program instructions, when executed by the one or more processors, cause the GPI device to assign a command to the GPI signal when the GPI device receives the GPI signal from the first device and transmit the command to a second device. The transmission of the command may be triggered by the received GPI signal. The command may include a script, such as a python script. The command may also include triggering transmission of a live broadcast, switching between graphics during the live broadcast, or a combination thereof.

The invention discloses a global memory allocation method and device for a GPGPU (General Purpose Graphics Processing Unit) and a medium, belongs to the technical field of GPGPU memory allocation, and is used for solving the technical problem that in the data transmission cooperative work process of an existing host and a GPGPU device, the real-time performance of a task is easily influenced, and a large device memory space is possibly occupied, so that the memory space is wasted. The method comprises the following steps: performing data block division processing on each piece of input data required by an input task to obtain input data blocks; performing operation processing of the device end on the first group of input data to obtain an operation result of the first group of input data; if the operation state of the device end is completed before the host end finishes sending the second group of input data, performing first operation completion control on the device end to obtain a first operation result of the second group of input data; and if the operation state of the device end is completed after the host end finishes sending the second group of input data, obtaining a post-operation result of the second group of input data.

A coordinated control system designed with a small form factor that can be located within a robot or an automated inline manufacturing system, comprising: an on board advanced distributed control hardware configured with artificial intelligence enabled processors incorporated within a System on Module (SOM) board, each SOM comprising four processors or nodes; interfaced with a cameras, motors, general purpose I / O through I2C expander, audio interface, Internet, wireless communication such as WiFi and Bluetooth to send and receive commands and any other data; electrically connected to a plurality of sensors for perceiving the environment and collecting data from infrared, tactile, proximity and other types of sensors; an external host flashing computer dedicated for uploading / downloading firmware, cloning and configuration setup; a non-volatile memory for storing control algorithms, configuration files and other essential data; a HDMI based user interface for robot operation, training and setup; USB C or Ethernet based internal star network for high-speed communication bypassing the standard PCI bus interface bus; an Ethernet switch board enabling multiple boards to access the Ethernet for both internal communication within the star network as well as external Internet access.