52 results about "Scratchpad memory" patented technology

A statically reconfigurable dataflow architecture processor (SRDAP) performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes L address pattern memory units (PMUs) comprising a memory arranged as a vector of L banks, and L corresponding data PMUs. Each data PMU receives a copy of the input image. In parallel: each address PMU writes an L-vector of addresses of input pixels to the vector of L banks and reads a single address of the written L-vector of addresses from a predetermined bank corresponding to a PMU number of the address PMU among the L address PMUs, and each data PMU receives the single address from the corresponding address PMU and uses it to read a single input pixel from the data PMU memory. A tree of pattern compute units coalesces the L single input pixels into an L-vector of input pixels.

A floating point arithmetic device with two floating point operands and its operation method are disclosed. The floating point arithmetic device includes an exponent subtraction circuit, an exponent calculation circuit, a mantissa calculation circuit, and a conversion circuit. The exponent subtraction circuit calculates the difference between the exponents of the two operands and generates a sign bit and an exponent difference. The exponent calculation circuit generates the post-operation exponent bits according to the larger one of the exponents of the two operands. The mantissa calculation circuit aligns the mantissa bits of the two operands and performs one of addition and subtraction on the aligned mantissa bits. To improve the calculation efficiency and reduce the power consumption, the floating point arithmetic device can complete the floating point addition or subtraction operation in one step (one clock cycle) without moving the intermediate floating point data between the registers and the functional circuit units as in the multi-step operation.

Techniques for static instruction decoupling for data movement and computer are described. In some examples, hardware support at least includes a plurality of instruction queues to store instructions, wherein each instruction queue of the plurality of instruction queues is dedicated to a separate thread; a local memory to store instructions and / or data for a first thread; a scratchpad memory, coupled to the local memory, to store instructions and / or data for a second thread; and execution resources, coupled to the scratchpad memory, to execute one or more mathematic and / or logical instructions for a third thread.

A chip, a design method thereof, and a fault analysis method thereof, wherein the chip, also known as an integrated circuit, includes a configuration register that is usually volatile, and / or at least one on-chip non-volatile memory m, which usually includes at least one reserved memory location that can be reserved to store the content of at least one of the configuration registers that is usually volatile; and / or a write unit that is configured to store a value indicating the content of at least one of the configuration registers that is usually volatile at least once in, for example, the at least one reserved memory location in the on-chip non-volatile memory.

Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.

The present application provides a test circuit and an electronic device for testing a memory circuit, which includes a controller, a pattern generating circuit, a comparison circuit and a register. The controller is used to generate a plurality of internal test signals and receive a test result. The pattern generating circuit writes a test data into a memory block of the memory circuit according to the internal test signals and reads the memory block to generate a read data. The comparison circuit compares the test data and the read data to generate the test result. The register is used to store the test result. The controller judges whether the memory circuit is normal according to the test result stored in the register.

The present disclosure provides a method for adaptive noise suppression of a data strobe signal and a memory element using the same. The method comprises the following steps of: judging whether a first data strobe signal and a second data strobe signal meet a first condition; in response to the first data strobe signal and the second data strobe signal satisfying the first condition, determining whether a mode register setpoint (MRSV) associated with a first on-die terminator and a second on-die terminator is greater than N; and in response to the MRSV not greater than N, respectively disconnecting a first resistor and a second resistor from a first input end and a second input end of a differential amplifier, and in response to the MRSV being greater than N, the first resistor and the second resistor are respectively coupled to the first input end and the second input end of the differential amplifier.

The embodiment of the present invention provides a semiconductor memory device and an operation method thereof that can know whether the reading of setting information is completed correctly during the power-on action. The semiconductor memory device and the operation method provided by the present invention read the fuse memory when it is detected that the power supply voltage reaches the power-on detection level, and determine whether the reading of the fuse memory is completed correctly. When it is determined that it is not completed correctly, the fuse memory is read again within the maximum reading number range, and the setting information read from the fuse memory is written to the CF register. Furthermore, the identification data for identifying whether the reading of the fuse memory is completed correctly is stored in the register.

The present invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency divider includes a plurality of registers, a counter, a control signal generator, and a clock gating circuit. With respect to the plurality of registers, at least a portion of the plurality of registers is set to have a value. The counter is configured to sequentially generate a plurality of count values, wherein the plurality of count values ​​respectively correspond to the at least a portion of the registers, and the plurality of count values ​​are repeatedly generated. The control signal generator is configured to generate a control signal based on the received count value and the corresponding register value. The clock gating circuit is configured to mask or unmask an input clock signal based on the control signal to generate an output clock signal.

The invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency eliminator comprises a plurality of temporary memories, a counter, a control signal generator and a clock pulse gating circuit. At least a portion of the plurality of registers is set to have a value with respect to the plurality of registers. The counter is used for sequentially generating a plurality of count values, the plurality of count values respectively correspond to the at least one part of the temporary register, and the plurality of count values are repeatedly generated. The control signal generator is used for generating a control signal according to the received count value and the value of the corresponding register. The clock gating circuit is used for referring to the control signal to shield or not shield an input clock signal so as to generate an output clock signal.

The present disclosure provides a vector processing circuit and a vector processing method. The vector processing circuit includes a vector register, a two-dimensional register, and an operation circuit. The vector register is configured to store first data. The two-dimensional register is configured to store second data. The operation circuit is configured to perform a first matrix multiplication operation on the first data and the second data. After performing the first matrix multiplication operation, the vector register is configured to store third data to replace the first data, and the operation circuit is configured to perform a second matrix multiplication operation on the third data and the second data. Thus, the data exchange and delay can be reduced.

The present invention discloses a joint test workgroup microcode update module, method and system. The joint test workgroup microcode update module includes a JTAG interface, a buffer and drive unit, a security and protection unit, a test access port controller, an instruction register, a data register and a microcode interface logic unit; external microcode data is loaded through the JTAG interface, and the buffer and drive unit performs signal enhancement processing on the output signal of the JTAG interface; the security and protection unit receives and verifies the security and correctness of the microcode data loaded through the JTAG interface, and controls the further transmission of the verified microcode data and intercepts the microcode data that fails the verification; the test access port controller is electrically connected to the instruction register and the data register respectively to control the transmission of data and instructions; and the microcode interface logic unit transmits the microcode data to the system interface unit. The present invention can safely and reliably update the external microcode to the processor system.

The invention discloses a floating-point arithmetic device with two floating-point number operands and an operation method of the floating-point arithmetic device. The floating-point arithmetic device comprises an index subtraction circuit, an index calculation circuit, a mantissa calculation circuit and a conversion circuit. The exponent subtraction circuit is used for calculating the difference between the exponents of the two operands to generate a sign bit and an exponent difference. The exponent calculation circuit generates a post-operation exponent bit according to a larger exponent in the exponents of the two operands. The mantissa calculation circuit aligns mantissa bits of the two operands, and performs one of addition and subtraction on the aligned mantissa bits. In order to improve the calculation efficiency and reduce the power consumption, the floating-point arithmetic device can complete floating-point addition or subtraction operation in one step (one clock cycle) without moving intermediate floating-point number data between a temporary memory and each functional circuit unit like multi-step operation.

A processor core (1) of the SIMT type and a related method of operation are disclosed. The processor core comprises frontend circuitry (10), a plurality of lanes (20a-f), a multi-banked and arbitration-free scratchpad memory (40), and an interconnect (50) to couple active ones of the plurality of lanes to different ones of the scratchpad memory banks. There are at least as many banks as lanes in the processor core. Each lane comprises a thread-private register file (21a-f) and address generation logic (22a-f) to independently calculate an effective address of an operand within the scratchpad memory. An execution pipeline of the processor core, associated with the thread-parallel execution of vector memory instructions, comprises at least the address generation logic of the different lanes, the interconnect, and the different banks as pipeline components. The processor core is implemented as a stack of dies (2a, 2b) including the frontend circuitry and the plurality of lanes on a first die (2a) and the scratchpad memory on a second die (2b).

Methods, systems, and apparatus, including computer-readable media, are described for a hardware circuit configured to implement a neural network. The circuit includes a first memory, respective first and second processor cores, and a shared memory. The first memory provides data for performing computations to generate an output for a neural network layer. Each of the first and second cores include a vector memory for storing vector values derived from the data provided by the first memory. The shared memory is disposed generally intermediate the first memory and at least one core and includes: i) a direct memory access (DMA) data path configured to route data between the shared memory and the respective vector memories of the first and second cores and ii) a load-store data path configured to route data between the shared memory and respective vector registers of the first and second cores.

The invention provides a field programmable memory array, a writing method and a reading method. The field programmable memory array comprises a single readable and writable memory array, an addressing circuit and an access circuit. The readable and writable memory array includes m memory cells in 2i rows and 2j columns to perform a digital circuit function, and has a plurality of digital inputs and a plurality of digital outputs. The addressing circuit is configured to receive an n-bit input vector and is coupled between the readable and writable memory array and the access circuit. The n-bit input vectors are selected from a register conversion layer logic table, and the logic table comprises a plurality of n-bit input vectors and a plurality of m-bit output vectors. The FPMA utilizes the character line / bit line multiplexer characteristics of the memory array to realize the operation of a plurality of binary inputs and any number of binary outputs. The FPMA has the advantages that the connection complexity is reduced, the number of repeated flip-flops is reduced, and the grain area in an integrated circuit chip is saved.

An apparatus and method for efficiently scheduling wavefronts for execution on an integrated circuit. In various implementations, a computing system includes a parallel data processing circuit with multiple, replicated compute circuits. Each compute circuit executes one or more wavefronts. Each compute circuit includes a cache configured to store temporary data that cannot fit in the vector general-purpose register file of the compute circuit. Each wavefront requests a corresponding amount of storage space in the cache for storing the temporary data. When the available data storage space in the cache is less than a data size requested by a wavefront waiting to be dispatched, a control circuit of the compute circuit reduces a dispatch rate of wavefronts. The control circuit also reduces an issue rate of instructions of one or more dispatched wavefronts to assigned execution circuits of the compute circuit.

The application discloses a memory management method, device, equipment and medium. The method comprises the following steps: obtaining pre-defined temporary register initialization parameters during initialization; applying memory space to an operating system once according to the temporary register initialization parameters, and obtaining initialized temporary registers; obtaining a first value corresponding to memory application of a target application program during running of the target application program; traversing all the initialized temporary registers, and calculating a difference value between a memory space value corresponding to at least one memory block in each temporary register and the first value; searching for an optimal temporary register in all the temporary registers according to the difference value; when the optimal temporary register is found, allocating at least one memory block in an unused state from the optimal temporary register to the target application program, and marking a state of each allocated memory block as a used state. The method can uniformly allocate and manage memory blocks by creating temporary registers in advance, reduce the number of times of directly calling system memory allocation, and improve memory use efficiency.

The utility model relates to a temporary memory main memory module special for a light-emitting server. The temporary memory main memory module comprises a printed circuit board, a plurality of dynamic random access memories, a temporary clock pulse driver and at least one light-emitting diode, the dynamic random access memories are arranged on the printed circuit board. The temporary clock pulse driver is arranged on the printed circuit board. The at least one light emitting diode is arranged on the printed circuit board. Therefore, the main memory module of the temporary memory special for the light-emitting server can emit light through the light-emitting diode in the state of stable current, highlights the aesthetic feeling, and meets the requirements of artificial intelligence creators, game developers and display type workstations or servers.

An inter-integrated digital audio standard (I2S) audio device and its misalignment recovery method are provided, including a first-in-first-out (FIFO) circuit and a shift register. The FIFO circuit has a memory, a FIFO synchronization logic circuit, and a FIFO misalignment flag. The FIFO synchronization logic circuit, in response to changes in the logic bits of the left and right clock signals, shifts data out of the memory or into the memory according to the data's position. In response to a misalignment in the FIFO circuit, the logic bit of the corresponding FIFO misalignment flag is set to the first logic bit. The shift register outputs data from the memory or shifts data into the memory according to changes in the logic bits of the bit clock signals. In response to the FIFO misalignment flag being set to the first logic bit, the I2S audio device is reset to recover the misalignment.

The present invention relates to a method, system, electronic device, and medium for improving CPU execution efficiency, comprising: obtaining an access request, the access request including a first access address of target data, the first access address representing the storage location of the target data in a temporary register; obtaining the target data from the temporary register according to the first access address, and if the target data is not obtained from the temporary register, determining a second access address corresponding to the target data according to the first access address, the second access address representing the storage location of the target data in a main memory; obtaining the target data from the main memory according to the second access address; and storing the target data in the temporary register according to the target storage address, the target storage address representing the storage address of the target data in the temporary register. The method solves the problem of low CPU execution efficiency when the current CPU fails to obtain data in the temporary register.

The application discloses a kind of based on RISC-V instruction set's graphic processor instruction processing method and device, comprising: the current instruction is decoded, and initial decoding result is obtained;According to the initial decoding result, it is judged whether the current instruction is register expansion instruction;If the current instruction is not the register expansion instruction, then according to the effective bit information of target temporary register, the instruction processing category is determined;Wherein, the instruction processing category includes RISC-V standard decoding category or splicing decoding category;For the splicing decoding category, target expansion data is read from the target temporary register;Wherein, the target expansion data is the expansion data corresponding to last register expansion instruction;The target expansion data and the initial decoding result are spliced and handled, and target decoding result is generated.The application can improve the instruction processing performance of graphic processor designed by using RISC-V instruction set.

A micro-control circuit, a control method and an operating system wherein the micro-control circuit comprises a memory, an image processing circuit, a first register, a second register, a control circuit and a display circuit. The memory comprises a first storage space and a second storage space. The image processing circuit writes first image data into the first storage space and writes second image data into the second storage space. The first register stores an initial address of one of the first storage space and the second storage space. The second register stores another initial address of the first storage space and another initial address of the second storage space. The control circuit exchanges the values of the first register and the second register according to a vertical synchronization signal. The display circuit reads the image data of the first storage space or the second storage space according to the numerical value of the first temporary memory.

The invention discloses an asynchronous first-in first-out memory verification method, device and equipment and a medium, and relates to the technical field of integrated circuit design and verification, and the method comprises the steps: analyzing a temporary memory transfer language code, detecting whether a statement is complete or not and whether bit width and depth parameters of a memory unit are consistent with design specifications or not, and obtaining a detection result; verifying the clock domain affiliation of the read-write pointer generation logic to obtain a first verification result; verifying the synchronization chain level, the Gray code coding and the clock domain isolation to obtain a second verification result; verifying the data integrity and the error processing mechanism through the test case to obtain a third verification result; determining a coverage rate heat map according to the coverage rate data, and verifying the completeness of the test case to obtain a fourth verification result; and generating a verification report according to the detection result, the first verification result, the second verification result, the third verification result, the fourth verification result and the coverage rate heat map to complete verification. And automatic verification of the asynchronous first-in first-out memory is realized.

Methods and systems, including computer programs encoded on a computer storage medium. In one aspect, a method includes the actions of receiving a request to perform convolutional computations for a neural network on a hardware circuit having a matrix computation unit, the request specifying the convolutional computation to be performed on a feature tensor and a filter and padding applied to the feature tensor prior to performing the convolutional computation; and generating instructions that when executed by the hardware circuit cause the hardware circuit to perform operations comprising: transferring feature tensor data from a main memory of the hardware circuit to a scratchpad memory of the hardware circuit; and repeatedly performing the following operations: identifying a current subset of the feature tensor; and determining whether a memory view into the scratchpad memory for the current subset is consistent with a memory view of the current subset in the main memory.

The application provides a binary search method and system. The method comprises the following steps: providing a storage device with M entries, each of which stores a value; providing index register registers including N registers, wherein the N registers divide the storage device into N-1, N or N+1 search areas; wherein M and N are integers and N

This invention discloses a static timing analysis method and a static timing analysis system. The static timing analysis method includes: obtaining a standard component library file describing multiple standard components; performing circuit structure analysis on the standard component library file to identify a target sequential component from the standard components, the target sequential component including logic gates, selection circuits, and register circuits; executing a logic test program to identify pin combinations with non-mutually controllable relationships, and treating the timing constraints related to these pin combinations in the standard component library file as redundant timing constraints to remove them from the standard component library file, thereby generating an optimized standard component library file; and performing static timing analysis on the target circuit design based on the optimized standard component library file.

The invention relates to a temporary memory main memory module special for a light-emitting server. The temporary memory main memory module comprises a printed circuit board, a plurality of dynamic random access memories, a temporary clock pulse driver and at least one light-emitting diode, the dynamic random access memories are arranged on the printed circuit board. The temporary clock pulse driver is arranged on the printed circuit board. The at least one light emitting diode is arranged on the printed circuit board. Therefore, the temporary memory main memory module special for the light-emitting server can emit light through the light-emitting diode under the state of stable current, the aesthetic feeling is highlighted, and the requirements of an artificial intelligence creator, a game developer and a display type work station or a server shell are met.

A control circuit is used for being coupled to a memory through a plurality of channels, and the plurality of channels comprise a first channel. The control circuit comprises a storage circuit and a processor. The storage circuit is used for storing a plurality of read voltage tables and index registers. The processor is coupled to the storage circuit and is used for executing a first reread test on the memory by using the plurality of read voltage tables in sequence through the first channel until the first reread test is successfully executed by using a target read voltage table in the plurality of read voltage tables when an error occurs in the read operation of the first channel. When the processor successfully executes the first reread test, the processor determines whether to update the index register according to the change history of the stored data in the index register. Therefore, the probability of retry reading can be reduced, and the reading efficiency can be improved.