272 results about "Scratchpad memory" patented technology

A method of graphics processing includes determining a non-depth conditional status and an occlusion status of a fragment. Such a method may be used in culling occluded fragments before expending resources such as processing cycles and memory bus usage. In one example, a scratchpad stores depth values of robust fragments and is used for occlusion testing. Graphics architectures, and methods that include use of representative Z values, are also disclosed.

The invention provides a separable array-based reconfigurable accelerator and a realization method thereof. The reconfigurable accelerator comprises a scratchpad memory cache area, separable calculation arrays, and a register cache area, wherein the scratchpad memory cache area is used for realizing reuse of data of convolution calculation and sparsity full connection calculation, the separable calculation arrays comprise multiple reconfigurable calculation units and fall into a convolution calculation array and a sparsity full connection calculation array, the register cache area is a storage area formed by multiple registers, and provides input data, weight data and corresponding output results for convolution calculation and sparsity full connection calculation, input data and weight data of convolution calculation are input into the convolution calculation array, the convolution calculation array outputs a convolution calculation result, input data and weight data of the sparsity full connection calculation are input into the sparsity full connection calculation array, and the sparsity full connection calculation array outputs a sparsity full connection calculation result. Characteristics of two neural networks are fused, so that the calculation resource of the chip and the memory bandwidth use ratio are improved.

The invention provides a vector calculating device comprises a memory cell, a register unit and a vector operation unit. Vectors are stored in the memory cell, addresses stored by the vectors are stored in the register unit, and the vector operation unit obtains a vector address in the register unit in dependence on a vector operation instruction, and then obtains a corresponding vector in the memory cell in dependence on the vector address, and carries out vector operation in dependence on the obtained vector to obtain a vector operation result. According to the invention, vector data participating in calculation is temporarily stored in a scratchpad memory, data in different widths can be supported flexibly and effectively during the vector operation process, and the execution performance of tasks including a lot of vector calculations is improved.

The invention provides a matrix calculating device comprising a memory cell, a register unit and a matrix operation unit. Matrixes are stored in the memory cell, addresses stored by the matrixes are stored in the register unit, and the matrix operation unit obtains a matrix address in the register unit in dependence on a matrix operation instruction, and then obtains a corresponding matrix in the memory cell in dependence on the matrix address, and carries out matrix operation in dependence on the obtained matrix to obtain a matrix operation result. According to the invention, matrix data participating in calculation is temporarily stored in a scratchpad memory, data in different widths can be supported flexibly and effectively during the matrix operation process, and the execution performance of tasks including a lot of matrix calculations is improved.

A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main register file. The local memory can emulate as an additional register file to the processor and can reside at a virtual address. The local memory can be further partitioned for prefetching data from a non-cacheable address to be stored/loaded into the main register file.

A system and method for logging and storing failure analysis information on disk drive so that the information is readily and reliably available to vendor customer service and other interested parties is provided. The information, in an illustrative embodiment, is stored on a nonvolatile (flash) random access memory (RAM), found generally in most types of disk drives for storage of updateable disk drive firmware. A known location of limited size is defined in the flash RAM, to form a scratchpad. This scratchpad is a blank area of known addresses, formed during the original firmware download onto the memory, and which is itself free of firmware code. This scratchpad is sufficient in size to write a series of failure codes in a non-erasable list as failures/errors (and user/administrator attempts to unfail the disk) are logged. The log of failures always travels with the drive, and can be read by the vendor to determine the general nature of the most recent failure(s) and whether these failures represent a problematic history for the drive.

The invention provides a sub-matrix operation device and method. The device includes a storage unit, a register unit and a sub-matrix operation unit. Sub-matrix data are stored in the storage unit. Sub-matrix information is stored in the register unit. The sub-matrix operation unit acquires the sub-matrix information in the register unit according to a sub-matrix operation instruction, acquires the corresponding sub-matrix data in the storage unit according to the sub-matrix information, and then carries out sub-matrix operations according to the acquired sub-matrix data to obtain a sub-matrix operation result. According to the device and method, the sub-matrix data involved in computation is temporarily stored on a high-speed scratchpad memory, the device can be enabled to more flexibly and effectively support data with different widths in sub-matrix operation processes, and the execution performance of a computation task including a large number of sub-matrices is improved.

Various embodiments of systems and methods to implement a voice scratchpad for deriving data from a voice communication are provided. The system may include a voice scratchpad module configured to detect an audio connection between an on-board vehicle computing device and a communications device, and present a selector on a voice scratchpad graphical user interface, which upon selection by a user causes the voice scratchpad module to process voice data received via the audio connection to obtain recognized speech data. The system may further include an annotation engine configured to annotate the recognized speech data to produce structured data in one of a plurality of predetermined formats. The voice scratchpad module may be configured to receive the structured data from the annotation engine, and display the structured data on voice scratchpad graphical user interface.

A highly predictable, low overhead and yet dynamic, memory allocation methodology for embedded systems with scratch-pad memory is presented. The dynamic memory allocation methodology for global and stack data (i) accounts for changing program requirements at runtime; (ii) has no software-caching tags; (iii) requires no run-time checks; (iv) has extremely low overheads; and (v) yields 100% predictable memory access times. The methodology provides that for data that is about to be accessed frequently is copied into the SRAM using compiler-inserted code at fixed and infrequent points in the program. Earlier data is evicted if necessary.

The invention relates to an apparatus and a method used for an operation of a big integer multiplication. The apparatus of the operation of the big integer multiplication consists of a temporary memory of a multiplicand, the temporary memory of a multiplier, a multiplication module, an addition module, the temporary memory of a carry value and a storage temporary memory of a multiplication result. The storage of the temporary memory of the multiplicand comprises m multiplicand data of multiplicand elements Ak; a k is a serial number of the multiplicand element Ak. The storage of the temporary memory of the multiplier comprises n multiplier data of multiplier elements Bj; a j is the serial number of the multiplier element Bj. In the multiplication module the multiplicand element Ak multiplied by the multiplier element Bj makes a product value AkBj. The addition module adds the product value AkBj, a multiplication result value Rk-1,j +1 of the lower right and the right carry value Ck-1, j to get the multiplication result value Rkjand the carry value Ckj. The storage temporary memory of the carry value stores the carry value Ck j and provides the carry value Ck-1, j on the right of the addition module. The temporary memory of the multiplication result stores the multiplication result value Rk j, and provides the multiplication result value Rk-1, j+1 on the lower right of the addition module.

The invention discloses a page presenting method and page presenting equipment. The equipment comprises an element logger, an element resolving and rendering device, an element resolving and rendering judger, a temporary element register and an element representing device. The method comprises the following steps that when contents represented on the current window of a browser change, the element resolving and rendering judger judges whether to resolve and render registered elements stored in the temporary element register; and if resolving and rendering are required, the element resolving and rendering device resolves and renders the registered elements stored in the temporary element register. Elements required to be represented in a delayed way are registered, and the registered elements required to be represented in the delayed way are resolved, rendered and represented in the delayed way, so that pictures in a page can be represented and processed in the delayed way, other page elements can be represented and processed in the delayed way, and the display speed of the page is increased effectively.

The invention discloses a design method of a high speed register with low power consumption and high capacity. On the one hand, the invention prevents the invalid visiting to the high speed register by beforehand obtaining the information whether the high speed register is hitting and reduce the dynamic power consumption; on the other hand, the invention divides the storing district in to a number of physical blocks and only visit 1/n of the total size under the hitting status of the high speed working-storage section, the dynamic power consumption is 1/n of the original situation. The invention saves the switching time of the dummy address to the physical address, reduces the extra hardware spending brought by the address switching and reduces the whole power consumption of the system byadopting the dummy address to search the high speed register. The invention can greatly reduce the power consumption of the high speed register and greatly elevate the whole capacity of the highly embedding type processor being utilized, which has the advantages of low hardware cost and simple design realization.

A system includes a smart table at which a wagering game is provided RFID-enabled chips and RFID sensors configured to detect the presence of RFID-enabled chips. The smart table includes a dealer scratchpad for detecting a value of RFID-enabled chips within a scratchpad area on the smart table. The smart table includes a ticket reader and a processor configured to scan, with the ticket reader, a voucher presented by a player, the voucher is redeemable for a voucher value, determine the voucher value of the voucher in response to the scanning, display, to a dealer of the wagering game at the smart table, a confirmation that the player is entitled to receive the voucher value, detect, from the RFID sensor, a chip value within the scratchpad area, compare the chip value to the voucher value, and display, to the dealer, a confirmation that the chip value matches the voucher value.

The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an interleaved forward-reverse addressing which greatly relieves the amount of memory required. This approach is in marked contrast to conventional turbo decoders which employ either a dual port main memory or a single port main memory in conjunction with a complex ping-ponged scratch memory. In the system of this invention, during each cycle accomplishes one read and one write operation in the scratch memories. If a particular location in memory, has been read, then that location is free. The next write cycle can use that location to store its data. Similarly a simplified beta RAM is implemented using a unique addressing scheme which also obviates the need for a complex ping-ponged beta RAM.

A quick algorithm preventing from irregular power cut off in flash memory and a control system is to mainly store logic BA and related interlock relationship mapping list information of PBA information in a PB paging of the memory protected by a set of ECC. When the host in operation, the controller logs in the mapping list information directly on a temporary memory of the said control device forits fetching, in which, the set up of mapping list is promptly and quickly without scanning program, and if the mapping list is wrong because of the irregular operation system then it will turn back to the last one to recover and ordinary interlock.