8 results about "Scratchpad memory" patented technology

A frequency adjustment device and a frequency adjustment method are disclosed. The device includes a microprocessor and a buffer. The microprocessor is configured to receive a memory access signal. The buffer is disposed in the microprocessor and configured to receive and output an input index signal and an output index signal based on the memory access signal, the input index signal and the output index signal. A frequency adjustment circuit is configured to receive and output a first current threshold value based on the input index signal and the output index signal. The frequency adjustment circuit is configured to output a threshold trimming signal to a time register based on a set threshold signal and the first current threshold value.

A processor core (1) of the SIMT type and a related method of operation are disclosed. The processor core comprises frontend circuitry (10), a plurality of lanes (20a-f), a multi-banked and arbitration-free scratchpad memory (40), and an interconnect (50) to couple active ones of the plurality of lanes to different ones of the scratchpad memory banks. There are at least as many banks as lanes in the processor core. Each lane comprises a thread-private register file (21a-f) and address generation logic (22a-f) to independently calculate an effective address of an operand within the scratchpad memory. An execution pipeline of the processor core, associated with the thread-parallel execution of vector memory instructions, comprises at least the address generation logic of the different lanes, the interconnect, and the different banks as pipeline components. The processor core is implemented as a stack of dies (2a, 2b) including the frontend circuitry and the plurality of lanes on a first die (2a) and the scratchpad memory on a second die (2b).

The application discloses a kind of based on RISC-V instruction set's graphic processor instruction processing method and device, comprising: the current instruction is decoded, and initial decoding result is obtained;According to the initial decoding result, it is judged whether the current instruction is register expansion instruction;If the current instruction is not the register expansion instruction, then according to the effective bit information of target temporary register, the instruction processing category is determined;Wherein, the instruction processing category includes RISC-V standard decoding category or splicing decoding category;For the splicing decoding category, target expansion data is read from the target temporary register;Wherein, the target expansion data is the expansion data corresponding to last register expansion instruction;The target expansion data and the initial decoding result are spliced and handled, and target decoding result is generated.The application can improve the instruction processing performance of graphic processor designed by using RISC-V instruction set.

This invention discloses a static timing analysis method and a static timing analysis system. The static timing analysis method includes: obtaining a standard component library file describing multiple standard components; performing circuit structure analysis on the standard component library file to identify a target sequential component from the standard components, the target sequential component including logic gates, selection circuits, and register circuits; executing a logic test program to identify pin combinations with non-mutually controllable relationships, and treating the timing constraints related to these pin combinations in the standard component library file as redundant timing constraints to remove them from the standard component library file, thereby generating an optimized standard component library file; and performing static timing analysis on the target circuit design based on the optimized standard component library file.

A computing system, preferably including a scratchpad, a plurality of computation units, and a register file, and optionally including a controller. The computing system, or any suitable elements thereof, can optionally be integrated into a processor unit, wherein one or more such processor units can optionally be integrated into a larger-scale computing system. Some or all elements of the larger-scale computing system can be collocated and / or codefined on a single semiconductor chip, can be located and / or defined on separate chips, and / or can be otherwise located and / or defined. A method of operation, preferably including performing computation unit I / O operations and / or performing scratchpad I / O operations. The method of operation is preferably performed using the computing system, but can additionally or alternatively be performed using any other suitable systems.

This application discloses a reference signal generation circuit and its reading method for time-domain readout, relating to the field of integrated circuit technology. The circuit includes: a majority of logic gates, several reference generation column circuits, and several data column circuits. Each reference generation column circuit is equipped with a corresponding first sensing amplifier; each data column circuit is equipped with a corresponding multi-column selector, a second sensing amplifier, and a data register. The reference signal generation circuit of this application can be directly applied to time-domain readout. Combined with the reading method of this application, it can accurately read time-domain signals even when the detectability margin of the difference signal in the voltage or current domain is continuously decreasing, thereby realizing memory readout signals and improving reliability.

The invention relates to a driving and access control system and method for virtualization communication of remote equipment, an extended CPLD (Complex Programmable Logic Device) of an extended circuit board transmits data to external equipment through an LVDS (Low Voltage Differential Signaling) and an external connection interface, so that the external equipment executes a corresponding instruction, and an extended register mapping table is stored in the extended CPLD; the expansion register mapping table stores information of control behaviors, data input and output and state monitoring of an external connection interface, the control CPLD provides signal conversion of LVDS and GPMC signals, and the control CPLD stores a plurality of control register mapping tables. Each control register mapping table corresponds to an expansion register mapping table for controlling an expansion circuit board correspondingly connected with the USB Type-C port, and performs data synchronization with the corresponding expansion register mapping table by using a data synchronization technology; the control device performs control behavior, data input and output and change of state monitoring on the control register mapping table to synchronize data to the corresponding extended register mapping table, so as to realize driving and access of the remote control external equipment, thereby achieving the technical effect of driving and access of the remote control external equipment.

On-package accelerators for integrating IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.