172results about "Details involving image processing hardware" patented technology

Approaches presented herein provide for the generation of synthesized data from input noise using a denoising diffusion network. A higher order differential equation solver can be used for the denoising process, with one or more higher-order terms being distilled into one or more separate efficient neural networks. A separate, efficient neural network can be called together with a primary denoising model at inference time without significant loss in sampling efficiency. The separate neural network can provide information about the curvature (or other higher-order term) of the differential equation, representing a denoising trajectory, that can be used by the primary diffusion network to denoise the image using fewer denoising iterations.

The invention relates to the technical field of visual sensing modules, and discloses a sensing-storage-calculation integrated bionic visual sensing module in-storage calculation method and system.The method comprises the steps that photo-induced electrons excited by incident photons are directly injected into memristor oxygen vacancy conductive filaments through a shared electrode interface, and photocurrent driving signals are obtained; in a forward SET mode, driving memristor oxygen vacancy conductive filaments to form cross array conductivity distribution, and calculating row line driving voltage of a memristor cross array; applying the current to each cross point of cross array conductance distribution in a reverse RESET mode to obtain a flowing current of each cross point; and converging and summing the flowing current of each cross point at a column line node to obtain a column line output current, performing capacitor charging integration on the column line output current, and converting the column line output current into an analog domain convolution operation voltage, thereby avoiding intermediate multiple analog-to-digital and digital-to-analog conversion loss. And end-to-end low-delay and low-power-consumption processing from photon sensing to feature calculation is realized.

The invention provides a polygon clipping processing method based on GPU acceleration, comprising the following steps: forming a minimum frame: reading the shape of a to-be-processed graph to form the minimum frame surrounding the to-be-processed graph, the minimum frame having a plurality of extreme points; the center of a first segmented grid is determined according to one of the extreme points, the segmented grid is a regular polygon, coordinates of all vertexes of the first segmented grid are obtained through calculation according to the center of the first segmented grid, other segmented grids are formed according to center coordinate deviation of the first segmented grid, and the center of the first segmented grid is a regular polygon; the minimum frame is completely covered by the segmentation grids; and kernel clipping: grouping the segmentation grids, performing parallel processing on each group of segmentation grids by using a GPU calculation unit so as to clip each group of segmentation grids edge by edge, and reserving vertexes of the segmentation grids in the to-be-processed graph and intersection points formed by the outer contour of the segmentation grids and the outer contour of the to-be-processed graph.

In a multi-GPU simulation environment, frame buffer management may be implemented by multiple GPUs (306, 402, 504, 600, 704) rendering respective frames of video, or by rendering respective portions of each frame of video (900 / 902; 1000 / 1002; 1100 / 1102). One of the GPUs controls HDMI frame output by virtue of receiving frame information from the other GPU(s) and reading out complete frames through a physically connected HDMI output port (1200). Or, the outputs of the GPUs can be multiplexed together (1302).

The invention provides a data migration method and device based on a computing pipeline, a processor and a related product. The data migration method based on the calculation pipeline comprises the following steps: receiving a data migration instruction of to-be-processed data; the data migration instruction is used for indicating a target data migration operation on the to-be-processed data; determining a target complexity classification corresponding to the target data migration operation based on a corresponding relationship between a preset data migration operation and the complexity classification; if the target complexity is classified as a preset complex operation type, converting the to-be-processed data and the data migration instruction into a general calculation task; the preset complex operation type comprises data conversion and data analysis in the data migration operation; and executing the general-purpose computing task through the general-purpose computing pipeline to obtain target data after the target data migration operation is completed. According to the method, the hardware and software complexity of the graphics processor for realizing data migration can be reduced.

Techniques are described for implementing selective activation and deactivation of a dynamically allocated subset of shader engines, such as based on application-based profile information and / or on an active system power configuration. Instructions for execution are received from an application associated with a first application profile.Based on the application profile, a quantity of activated shader engines in a plurality of shader engines is modified. The quantity of activated shader engines is further modified responsive to receiving additional instructions from a second application, and / or to receiving one or more indications of an altered active system power configuration.

Embodiments herein provide a method and system for a vicarious calibration of optical data from satellite sensors for urban scene flat fields. Identifying test sites automatically in the urban scene helps in vicarious calibration or on-board calibration of the hyperspectral / multispectral image. An internal average relative reflectance is calculated to get a relative reflectance of the image. Band ratios for various pixels is determined to assess flatness of the spectrum. Flat field candidates are identified from the various pixels having average band ratio nearing zero and a morphological technique is applied to determine a flat field. Finally, the image is calibrated vicariously based on the determined flat field as a test site. The on-board calibration of the remote sensing image may lead to a faster way to get the reflectance image of the scene, with the help of the calibration constants.

To provide an imaging processing system that improves utilization efficiency of an FOV part in an imaging area.SOLUTION: A system of the present invention displays medical imaging data, and includes one or more data inputs, one or more processors, and one or more displays. The one or more data inputs are configured to receive first image data generated by a first medical imaging device. The first image data includes a field-of-vision (FOV) part and a non-FOV part (Step 202). The one or more processors identify the non-FOV part of the first image data (Step 204). By removing at least part of the non-FOV part of the first image data, cropped first image data is generated (Step 206). The cropped first image data to be displayed in a first part of the display and additional information to be displayed in a second part of the display are transmitted (Step 208).SELECTED DRAWING: Figure 2

The application relates to a data processing method and device, integrated circuit and electronic equipment, and belongs to the technical field of image processing. The data processing method comprises the following steps: alternately storing a received to-be-processed data stream into a first memory and a second memory; and continuously reading data from the first memory and the second memory for preprocessing, wherein the data writing rate is greater than the data reading rate, and is not greater than twice the data reading rate. The data processing method can process a high-speed data stream by using a low-speed processing module, thereby saving hardware cost and enhancing the applicability of the scheme.

An image inspection apparatus includes an image reader that reads an original image formed on a recording material based on a print job and generates a read image, and a hardware processor that analyzes the read image and performs an image inspection, wherein the hardware processor: acquires the read image from the image reader, detects an edge from the read image, and excludes a region near the edge from a target of the image inspection; performs a predetermined filter process on the read image after the exclusion process to generate a first reference image; compares the read image after the exclusion process with the first reference image to generate a first comparison image; and binarizes the first comparison image using a predetermined threshold to detect points where a specific abnormality has occurred, and outputs a detection result.

A system for storing geometry data for use by a graphics processor when rendering a frame that represents a view of a scene using a ray tracing process. The system comprises a processing circuit that is configured to prepare a ray tracing acceleration data structure for use when rendering a frame that represents a view of a scene using a ray tracing process. Graphics primitives for an end point of the ray tracing acceleration data structure is sorted into groups of contiguous graphics primitives, and fewer instances of vertex data is stored for a graphics primitive that is shared by at least two graphics primitives of the group of contiguous graphics primitives than the number of graphics primitives in the group of contiguous graphics primitives that share the vertex.

The present disclosure provides a management method and an apparatus for graphics rendering resources, a related device and a rendering method. The management method for graphics rendering resources includes: determining, in response to a received management instruction generated in a running process of at least one rendering program, a hardware resource object for calling graphic rendering, based on the management instruction and an interface function conversion relationship and a driving conversion relationship in a rendering resource object of a rendering program corresponding to the management instruction; and managing, according to the determined hardware resource object and the management instruction, a hardware resource of the graphic rendering required by the management instruction, wherein the interface function conversion relationship includes a conversion relationship between a pre-set hardware resource interface function and a target interface function of a hardware resource required for calling graphic rendering; and the driving conversion relationship includes a conversion relationship between the pre-set hardware resource interface function and the hardware resource object. The above method can reduce difficulty and cost of graphics rendering hardware resource management in scenarios with a plurality of rendering programs.

A method for configuring a buffer and an image synthesis apparatus are provided. The image synthesis apparatus includes a memory, and the memory includes a plurality of line buffers. The method includes the following step: dividing, according to a plurality of depths of a plurality of target planes, each of a plurality of target line buffers into a plurality of sections for respectively storing row pixel data of the target planes. The sections correspond to the depths of the target planes, respectively.

In various examples, apparatuses, systems, and techniques for performing offline image signal processing of source image data to generate target image data. In at least one embodiment, data collection is performed using exposure and calibration settings of an image sensor to generate source image data, which is then processed by using offline image signal processing to generate target data.

Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.

Graphics processor (2) comprises a programmable execution unit (65) executing programs to perform graphics processing and a machine learning (ML) processing circuit (78) (e.g. neural processing accele

To provide an image inspection device, an image inspection method and an image inspection program which can further shorten a time required in processes ranging from generation of a reference image to image inspection in comparison with in a conventional technique.SOLUTION: An image inspection device 300 comprises an image formation part 330, a reference image generation part 380 and an image inspection part 350. The image formation part 330 forms an image on a recording medium on the basis of obtained image data. The reference image generation part 380 generates a reference image that is used for inspecting the image formed on the recording medium, on the basis of the obtained image data. The image inspection part 350 inspects the image formed on the recording medium, on the basis of the reference image. The image inspection device 300 performs generation of the reference image and formation of the image on the recording medium in parallel.SELECTED DRAWING: Figure 2

The present invention specifically relates to a system and method for reconstructing microscope images, such as phase contrast microscope images, using a convolutional neural network, such as a U-net convolutional neural network. The method according to the present invention comprises the steps of obtaining a training data set comprising a plurality of bright field microscope images and a plurality of phase contrast microscope images, training a neural network based on the data set to extract phase information in the form of an interference pattern from each of the plurality of bright field microscope images, and further using the trained neural network to reconstruct a phase contrast microscope image from a bright field microscope image. The system according to the present invention comprises a memory device, a processing device, a storage and retrieval device, and a display device. The memory device stores the data set, the processing device trains a neural network based on the data set, and further enables the reconstruction of a phase contrast image.

The present invention relates to a method of assisting in diagnosis of a target heart disease using a fundus image, the method including: obtaining a target fundus image which is obtained by imaging a fundus of a testee; on the basis of the target fundus image, obtaining heart disease diagnosis assistance information of the testee according to the target fundus image, via a heart disease diagnosis assistance neural network model which obtains diagnosis assistance information that is used for diagnosis of the target heart disease according to the fundus image; and outputting the heart disease diagnosis assistance information of the testee.

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of pixels associated with a first color space including a plurality of first color channels, at least one first color channel of the plurality of first color channels being a first compressed channel. The apparatus may also decompress the at least one first color channel of the plurality of first color channels, the at least one first color channel being decompressed from the first compressed channel to a first decompressed channel. Further, the apparatus may perform a color space conversion of the first color space associated with the plurality of pixels, such that the plurality of first color channels is converted to a plurality of second color channels, the plurality of second color channels being associated with a second color space for the plurality of pixels.

The present disclosure relates to graphics processing systems. In particular, it relates to a graphics processor that rasterizes input primitives to generate graphics fragments to be processed, and renders the graphics fragments to generate a first, higher resolution version of a render output. When processing of the render output is stopped before completion of the render output, the first resolution version of the render output is downsampled to a second, lower resolution, and the downsampled data elements at the second resolution and a set of difference values indicative of differences between data elements at the first resolution and the downsampled data elements at the second resolution are written out. When processing of the render output is resumed, these values can then be loaded and used to reconstruct the array of data elements at the first resolution for use in continuing processing of the render output.

A region-based depth test method and apparatus, a device, a storage medium, and a computer program product. The method includes: before executing a tile rasterization process, dividing a tile is divided to obtain a plurality of regions to be tested and region data corresponding to said regions, the region data including region information of said regions and graphic primitive information corresponding to said regions (S201); for each said region, generating a first depth range of said region on the basis of the region information of said region and the graphic primitive information corresponding to said region (S202); acquiring a second depth range of said region from a depth range cache (S203); and determining a depth test result of said region on the basis of the first depth range and the second depth range, the depth test result being used for indicating whether said region requires a pixel-level depth test (S204).

A processor receives a request to access one or more levels of a portion of a persistent texture (PRT) resource. The levels represent textures at different levels of detail (LODs) and the request includes normalized coordinates indicative of a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more persistent maps indicative of texels that are resident in the PRT resource. The processor converts the normalized coordinates to texel coordinates in the one or more persistent maps based on the offsets and accesses the one or more persistent maps based on the texel coordinates in response to the request to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.

During the rendering of an image, specific pixels in the image are identified where antialiasing would be helpful. Antialiasing is then performed on these identified pixels, where antialiasing is a technique used to add greater realism to a digital image by smoothing jagged edges. This reduces a cost of performing antialiasing by reducing a number of pixels within an image on which antialiasing is performed.

The application relates to a structured light 3D camera system and a measurement method based on FPGA heterogeneous computing, wherein the system comprises a projection module for projecting a structured light coding pattern sequence containing multiple frames of patterns; a collection module for collecting a structured light coding pattern sequence modulated by a target object and outputting the structured light coding pattern sequence in a preset format; and a processing chip module for generating a phase diagram of the target object by pipeline processing of the structured light coding pattern sequence through each hardware acceleration processing pipeline in an FPGA programmable logic unit and sending the phase diagram to an external host through Ethernet to perform three-dimensional modeling of the target object. Through the application, pipeline processing of the structured light coding pattern based on the FPGA hardware acceleration processing pipeline is realized, the time consumption of three-dimensional reconstruction is greatly reduced, edge computing on the camera system is realized, and the problem of how to improve the calculation real-time performance of three-dimensional reconstruction is solved.

Aspects of this technical solution can increase speed of processing and lower computational hardware complexity in motion detection, while maintaining integrity of motion detection across image frames. For example, in image-processing environments associated with autonomous or semi-autonomous navigation (e.g., driving, robotic navigation, etc.), a large volume of image data is to be rapidly and accurately processed to maintain reliable and up-to-date models of a physical environment. Thus, embodiments in accordance with this disclosure can provide high-speed and accurate motion detection of input frame data.

The invention discloses a self-adaptive QoS arbitration method and device for an image system, and belongs to the field of computer hardware and data communication. According to the method, a priority locking mechanism and a credit refreshing mechanism triggered by authorization switching are introduced, so that the bus utilization rate is improved, the arbitration logic overhead is reduced, and concurrent access management of multiple channels on shared memory resources is realized. According to the structural design, a channel transaction management module and a GST-WA core arbitration module are designed, high decoupling of read-write transactions and arbitration logic is achieved, and standardized processing is conducted on data streams with channels as units. Meanwhile, an arbiter combines credit depletion forced propulsion and a deadlock prevention mechanism to realize effective balance between QoS guarantee and long-term fairness of a high-weight channel.

This application provides an image processing method, an electronic device, and a storage medium, and relates to the field of image processing. The method includes: receiving a frame buffer resource creation command delivered by an application, where a frame buffer corresponding to the frame buffer resource creation command includes a color attachment; storing, in preset storage space, a frame buffer identifier of a frame buffer whose quantity of color attachments meets a preset quantity condition; receiving a rendering command delivered by the application, where the rendering command corresponds to a first frame buffer; and performing a rendering operation corresponding to the rendering command on a second frame buffer if a frame buffer identifier consistent with a frame buffer identifier of the first frame buffer exists in the preset storage space, where resolution of the second frame buffer is lower than resolution of the first frame buffer.

Techniques and systems are provided for processing image data using one or more neural networks. For example, a patch of raw image data can be obtained. The patch can include a subset of pixels of a frame of raw image data, and the frame can be captured using one or more image sensors. The patch of raw image data includes a single color component for each pixel of the subset of pixels. At least one neural network can be applied to the patch of raw image data to determine a plurality of color component values for one or more pixels of the subset of pixels. A patch of output image data can then be generated based on application of the at least one neural network to the patch of raw image data. The patch of output image data includes a subset of pixels of a frame of output image data, and also includes the plurality of color component values for one or more pixels of the subset of pixels of the frame of output image data. Application of the at least one neural network causes the patch of output image data to include fewer pixels than the patch of raw image data. Multiple patches from the frame can be processed by the at least one neural network in order to generate a final output image. In some cases, the patches from the frame can be overlapping so that the final output image contains a complete picture.

In a method for subpixel disparity calculation, image data for various images each representing a field of view of an input device is received by a processor, and the image data is applied to a machine learning model. The machine learning module uses the image data to compute an output representing calculated subpixel disparity between the various images. In an example of the method, the machine learning model is a neural network that produces accurate and reliable subpixel disparity estimation in real-time using synthetically generated data.