420results about "Details involving image processing hardware" patented technology

Apparatus and method for efficient storage of BVH nodes in blocks. For example, one embodiment of an apparatus comprises: bounding volume hierarchy (BVH) construction circuitry to construct a BVH based on primitives of a graphics scene; and block allocation hardware logic coupled to or integral to the BVH construction circuitry, the block allocation hardware logic to allocate a plurality of nodes of the BVH into a plurality of blocks for storage in a cache or memory subsystem, the block allocation hardware logic to maximize a number of blocks which include a leading parent node and one or more corresponding child nodes of the plurality of nodes.

A method or system for implementing a machine learning pipeline on a chipset comprising a plurality of hardware compute elements. The system accesses a hardware-agnostic functional description of the machine learning pipeline, wherein the description specifies a plurality of functional modules, including at least one machine learning model. Hardware specifications of the chipset are accessed to identify the available hardware compute elements. Based on the hardware specifications, the functional modules are synthesized into a plurality of interconnected executable components configured to execute on at least two different hardware compute elements. An implementation package is generated, comprising the executable components and metadata describing interconnections between them. The implementation package is then deployed to the chipset, where the executable components are executed by the identified hardware compute elements.

In a general aspect, enhancement of artificial intelligence algorithms using 3D data is described. In some aspects, input data of an object is stored in a storage engine of a system. The input data includes first-order primitives and second-order primitives. A plurality of features of the object is determined by operation of an analytics engine of the system, based on the first-order primitives and the second-order primitives. A tensor field is generated by operation of the analytics engine of the system. The tensor field includes an attribute set, which includes one or more attributes selected from the first-order primitives, the second-order primitives, or the plurality of features. The tensor field is processed by operation of the analytics engine of the system according to a series of artificial intelligence algorithms to generate output data representing the object.

The invention discloses a multi-view collaborative 3D Gaussian splash optimization method and system, and the method comprises the steps: constructing a multi-level heterogeneous video memory pool, and dynamically dividing a video memory in 3D Gaussian reconstruction into a view exclusive memory block and a global shared memory pool; a mixed rendering-gradient pipeline is designed, and hardware-level pipeline parallelism in 3D Gaussian reconstruction is realized through a double-buffer asynchronous switching mechanism based on a CUDA Warp-level parallel primitive fusion forward rendering and back propagation thread group; performing multi-view gradient joint optimization, screening an effective gradient path in 3D Gaussian reconstruction based on the visibility mask matrix, and performing projection error weighted fusion on a multi-view gradient tensor; and implementing a multi-modal densification decision, generating a 3D Gaussian candidate splitting position in 3D Gaussian reconstruction through Monte Carlo sampling, calculating a joint optimization objective function by combining a multi-view projection residual error and a gradient contribution factor, and finally realizing 3D Gaussian reconstruction. According to the invention, high-precision and low-delay large-scale scene real-time rendering and training can be realized.

Approaches presented herein provide for the generation of synthesized data from input noise using a denoising diffusion network. A higher order differential equation solver can be used for the denoising process, with one or more higher-order terms being distilled into one or more separate efficient neural networks. A separate, efficient neural network can be called together with a primary denoising model at inference time without significant loss in sampling efficiency. The separate neural network can provide information about the curvature (or other higher-order term) of the differential equation, representing a denoising trajectory, that can be used by the primary diffusion network to denoise the image using fewer denoising iterations.

To display a low-resolution image at higher resolution and furthermore to reduce an afterimage.SOLUTION: Resolution is made higher by super-resolution processing. In this case, the super-resolution processing is performed after frame interpolation processing is performed. Further in that case, the super-resolution processing can be performed using a plurality of processing systems. Therefore, super-resolution processing can be performed at high speed even when frame frequency is made higher. An afterimage can be reduced since frame rate doubling is performed by frame interpolation processing.SELECTED DRAWING: Figure 1

A system and a method for displaying super-resolution images generated from images of lower resolution, includes processor circuitry for a combination multi-core CPU and machine learning engine configured with an input for receiving the low resolution images, a feature extraction section to extract features from the low resolution images, non-linear feature mapping section, connected to the feature extraction section, generating feature maps using a self-calibrated block with pixel attention having a plurality of Depthwise Separable Convolution (DSC) layers, a late upsampling section combines at least one DSC layer and a skip connection that upsamples the feature maps to a predetermined dimension, and a video output for displaying approximate upsampled super-resolution images that corresponds to the low resolution images.

The invention provides a frame insertion processing method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a first texture and a second texture obtained through rendering before the first texture, the first texture and the second texture are UI-free textures, splicing the first texture and the second texture to obtain a spliced texture, and storing the spliced texture in a storage medium; a feature extraction network in a frame insertion model is adopted to perform multi-dimensional feature extraction on the spliced texture to obtain a target optical flow feature map and a target mask feature map, the feature extraction network is deployed in an NPU, and a frame insertion network in the frame insertion model is adopted to obtain frame insertion texture according to the target optical flow feature map and the target mask feature map, the frame insertion network is deployed in the GPU, and the frame insertion model is deployed in the GPU and the NPU, so that the hybrid programming of the GPU and the NPU is realized, the algorithm advantages of two kinds of hardware are fully played, and the processing efficiency of the frame insertion model is improved.

The invention provides a rendering system, a chip, equipment and a rendering method applied to the rendering system, and relates to the technical field of image rendering. The rendering system comprises a rendering pipeline manager, a middle buffer area, M geometric processing pipelines and N pixel processing pipelines, wherein a plurality of data segments divided from an input data stream of the rendering system are allocated to M geometric processing pipelines for processing, and primitive data obtained by processing each data segment is stored in a middle buffer area; the rendering pipeline manager is used for acquiring serial numbers and memory information of the data segments processed by the geometric processing pipeline; the rendering pipeline manager is further used for sending rendering instructions to the N pixel processing pipelines respectively, the rendering instructions comprise the serial numbers and the memory information of the k data segments, k is an integer larger than or equal to 1, and the serial numbers of the k data segments are continuous under the condition that k is larger than 1. According to the method, the image rendering efficiency is improved.

For direct multi-volume rendering, each voxel of a volume has a scalar value. A multi-ray generator generates a view multi-ray in the direction of a pixel of a projection image, wherein the pixel represents a 2D projection of all scene voxels intersecting with the view multi-ray behind the projection image. A volume ray marching processor processes each view ray, wherein, at each ray marching step, the scalar value of the corresponding voxel is mapped to a color value and a transparency value of said corresponding voxel. A projection image updater updates the value of the particular pixel in the projection image by combining the respective voxel color and transparency values of the individual view rays. Updating with the values of a particular voxel intersecting with a particular view ray is performed after the updating with all intersecting voxel values of voxels closer to the viewing point than the particular voxel.

Approaches presented herein provide for the generation of synthesized data from input noise using a denoising diffusion network. A higher order differential equation solver can be used for the denoising process, with one or more higher-order terms being distilled into one or more separate efficient neural networks. A separate, efficient neural network can be called together with a primary denoising model at inference time without significant loss in sampling efficiency. The separate neural network can provide information about the curvature (or other higher-order term) of the differential equation, representing a denoising trajectory, that can be used by the primary diffusion network to denoise the image using fewer denoising iterations.

Apparatuses and methods for block friendly ray traversal are disclosed. An apparatus and method for efficient storage of BVH nodes in a block. For example, one embodiment of an apparatus includes a bounding volume hierarchy (BVH) construction circuit to construct a BVH based on primitives of a graphical scene; and block allocation hardware logic coupled to or integral with the BVH fabric circuitry, the block allocation hardware logic to allocate a plurality of nodes of the BVH into a plurality of blocks for storage in a cache or memory subsystem, the block allocation hardware logic is to maximize a number of blocks comprising a leader parent node of a plurality of nodes and one or more corresponding child nodes.

A development platform for implementing a machine learning pipeline on a chip containing multiple hardware compute elements. The development platform includes a user interface, a library of software blocks, and a synthesis engine. The user interface facilitates a user to develop a functional description of the machine learning pipeline. The functional description specifies multiple functional modules, including a machine learning model. The synthesis engine synthesizes the pipeline of functional modules into multiple interconnected executable components of software blocks and generates an implementation package including the executable components and specifying interconnections between the executable components.

Illustrative embodiments of the present disclosure include a method, a device, and a product for a Graphics Processing Unit (GPU) cluster. The method includes: obtaining a graph of interconnections between GPUs in the GPU cluster; forming a parallel hierarchical architecture of the GPU cluster based on the graph of interconnections between GPUs; and mapping parallel tasks to the parallel hierarchical architecture to execute the parallel tasks. The method for a GPU cluster according to the present disclosure ensures that high-speed GPU-GPU connection is used for tasks with high communication requirements, thus improving the overall processing efficiency of the GPU cluster.

The invention relates to an image rendering method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the steps of receiving rendering information; the rendering information is generated when the graphic application sends a rendering request; analyzing the rendering information, and creating a graphic task; the graphic task comprises a plurality of cache objects; the cache object is used for storing image data in the rendering process; the cache object carries a virtual address; when the physical space is allocated to each cache object, mapping the virtual address of each cache object to a physical address to obtain a page table mapping relation; generating a to-be-written page table item based on the page table mapping relation of each cache object, and sending the to-be-written page table item to the GPU; and the GPU writes the page table mapping relation into the corresponding page table item according to the to-be-written page table item so as to establish an access path between the GPU and the physical address, and the GPU executes the graphic task based on the access path. By adopting the method, the mapping efficiency can be improved.

Disclosed are an information processing method and a terminal device. The method comprises: acquiring first information, wherein the first information is information to be processed by a terminal device; calling an operation instruction in a calculation apparatus to calculate the first information so as to obtain second information; and outputting the second information. By means of the embodiments in the present disclosure, a calculation apparatus of a terminal device can be used to call an operation instruction to process first information, so as to output second information of a target desired by a user, thereby improving the information processing efficiency.

The invention provides a graphics processor, a texture loading method, a texture processing unit, equipment and a medium, and relates to the technical field of image texture loading. The method comprises the following steps: uniformly distributing texture loading instructions to a texture processing unit for execution, wherein the texture loading instructions comprise texture cache loading instructions; analyzing and executing the texture loading instruction through the texture processing unit; wherein the texture state information of the texture loading instruction is obtained through hardware analysis of the texture processing unit, the texture loading instruction completes address calculation and data reading in an independent texture loading pipeline, and the texture loading pipeline is started in the texture processing unit. According to the technical scheme, the scheduling logic of the texture loading instruction can be simplified, the compatibility of dynamic resources is improved, meanwhile, the hardware utilization rate is increased, and the reliability and execution efficiency of texture data access are improved.

The invention relates to the technical field of visual sensing modules, and discloses a sensing-storage-calculation integrated bionic visual sensing module in-storage calculation method and system.The method comprises the steps that photo-induced electrons excited by incident photons are directly injected into memristor oxygen vacancy conductive filaments through a shared electrode interface, and photocurrent driving signals are obtained; in a forward SET mode, driving memristor oxygen vacancy conductive filaments to form cross array conductivity distribution, and calculating row line driving voltage of a memristor cross array; applying the current to each cross point of cross array conductance distribution in a reverse RESET mode to obtain a flowing current of each cross point; and converging and summing the flowing current of each cross point at a column line node to obtain a column line output current, performing capacitor charging integration on the column line output current, and converting the column line output current into an analog domain convolution operation voltage, thereby avoiding intermediate multiple analog-to-digital and digital-to-analog conversion loss. And end-to-end low-delay and low-power-consumption processing from photon sensing to feature calculation is realized.

Executing a machine learning model in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (‘GPU’) servers, including: receiving, by a graphical processing unit (‘GPU’) server, a dataset transformed by a storage system that is external to the GPU server; and executing, by the GPU server, one or more machine learning algorithms using the transformed dataset as input.

The invention provides a polygon clipping processing method based on GPU acceleration, comprising the following steps: forming a minimum frame: reading the shape of a to-be-processed graph to form the minimum frame surrounding the to-be-processed graph, the minimum frame having a plurality of extreme points; the center of a first segmented grid is determined according to one of the extreme points, the segmented grid is a regular polygon, coordinates of all vertexes of the first segmented grid are obtained through calculation according to the center of the first segmented grid, other segmented grids are formed according to center coordinate deviation of the first segmented grid, and the center of the first segmented grid is a regular polygon; the minimum frame is completely covered by the segmentation grids; and kernel clipping: grouping the segmentation grids, performing parallel processing on each group of segmentation grids by using a GPU calculation unit so as to clip each group of segmentation grids edge by edge, and reserving vertexes of the segmentation grids in the to-be-processed graph and intersection points formed by the outer contour of the segmentation grids and the outer contour of the to-be-processed graph.

A method for performing Tile to Raster (T2R) conversion includes: receiving tile input data including a stream of a plurality of tiles each having a tile height, a tile input width, a macroblock width (MBW), and data bits; segmenting the tile input data based on a total number of virtual square tiles; segmenting a Tile Buffer (TB) into one or more of the virtual square tiles based on the received tile input data; and performing a raster-scanning operation on each of the segmented tile input data and the segmented TB based on the total number of virtual square tiles to generate raster data.

In a multi-GPU simulation environment, frame buffer management may be implemented by multiple GPUs (306, 402, 504, 600, 704) rendering respective frames of video, or by rendering respective portions of each frame of video (900 / 902; 1000 / 1002; 1100 / 1102). One of the GPUs controls HDMI frame output by virtue of receiving frame information from the other GPU(s) and reading out complete frames through a physically connected HDMI output port (1200). Or, the outputs of the GPUs can be multiplexed together (1302).

The invention provides a frame insertion method and device, electronic equipment and a storage medium, and the method comprises the steps: responding to the determination of texture rendering of a user interface UI, switching a rendering buffer from a first buffer to a second buffer, rendering the UI in the second buffer according to a target rendering instruction, and obtaining a first texture, obtaining a second texture which is obtained by rendering in the first buffer area and does not comprise the UI, carrying out frame insertion processing according to the second texture to obtain a frame insertion texture, fusing the frame insertion texture and the first texture to obtain a target frame insertion texture, and carrying out UI texture separation in the rendering process to obtain a first texture of the UI and the second texture which does not comprise the UI. And frame insertion is performed based on the second texture, so that the influence of the UI texture on frame insertion is avoided, and the accuracy of a frame insertion result is improved.

The invention provides a data migration method and device based on a computing pipeline, a processor and a related product. The data migration method based on the calculation pipeline comprises the following steps: receiving a data migration instruction of to-be-processed data; the data migration instruction is used for indicating a target data migration operation on the to-be-processed data; determining a target complexity classification corresponding to the target data migration operation based on a corresponding relationship between a preset data migration operation and the complexity classification; if the target complexity is classified as a preset complex operation type, converting the to-be-processed data and the data migration instruction into a general calculation task; the preset complex operation type comprises data conversion and data analysis in the data migration operation; and executing the general-purpose computing task through the general-purpose computing pipeline to obtain target data after the target data migration operation is completed. According to the method, the hardware and software complexity of the graphics processor for realizing data migration can be reduced.

Techniques are described for implementing selective activation and deactivation of a dynamically allocated subset of shader engines, such as based on application-based profile information and / or on an active system power configuration. Instructions for execution are received from an application associated with a first application profile.Based on the application profile, a quantity of activated shader engines in a plurality of shader engines is modified. The quantity of activated shader engines is further modified responsive to receiving additional instructions from a second application, and / or to receiving one or more indications of an altered active system power configuration.

Embodiments herein provide a method and system for a vicarious calibration of optical data from satellite sensors for urban scene flat fields. Identifying test sites automatically in the urban scene helps in vicarious calibration or on-board calibration of the hyperspectral / multispectral image. An internal average relative reflectance is calculated to get a relative reflectance of the image. Band ratios for various pixels is determined to assess flatness of the spectrum. Flat field candidates are identified from the various pixels having average band ratio nearing zero and a morphological technique is applied to determine a flat field. Finally, the image is calibrated vicariously based on the determined flat field as a test site. The on-board calibration of the remote sensing image may lead to a faster way to get the reflectance image of the scene, with the help of the calibration constants.

A processing device and method for tiled rendering of an image for display are provided. The processing device includes a memory and a processor. The processor is configured to receive an image including one or more three-dimensional (3D) objects, divide the image into tiles, perform coarse-level tiling on the tiles of the image, and perform fine-level tiling on the tiles of the image. The processing device also includes the same fixed-function hardware used to perform the coarse-level tiling and the fine-level tiling. The processor is configured to determine visibility information for a first tile. The visibility information is divided into draw-call visibility information and triangle visibility information for each remaining tile of the image.

To provide an imaging processing system that improves utilization efficiency of an FOV part in an imaging area.SOLUTION: A system of the present invention displays medical imaging data, and includes one or more data inputs, one or more processors, and one or more displays. The one or more data inputs are configured to receive first image data generated by a first medical imaging device. The first image data includes a field-of-vision (FOV) part and a non-FOV part (Step 202). The one or more processors identify the non-FOV part of the first image data (Step 204). By removing at least part of the non-FOV part of the first image data, cropped first image data is generated (Step 206). The cropped first image data to be displayed in a first part of the display and additional information to be displayed in a second part of the display are transmitted (Step 208).SELECTED DRAWING: Figure 2