582results about "Details involving image processing hardware" patented technology

Apparatus and method for efficient storage of BVH nodes in blocks. For example, one embodiment of an apparatus comprises: bounding volume hierarchy (BVH) construction circuitry to construct a BVH based on primitives of a graphics scene; and block allocation hardware logic coupled to or integral to the BVH construction circuitry, the block allocation hardware logic to allocate a plurality of nodes of the BVH into a plurality of blocks for storage in a cache or memory subsystem, the block allocation hardware logic to maximize a number of blocks which include a leading parent node and one or more corresponding child nodes of the plurality of nodes.

A method or system for implementing a machine learning pipeline on a chipset comprising a plurality of hardware compute elements. The system accesses a hardware-agnostic functional description of the machine learning pipeline, wherein the description specifies a plurality of functional modules, including at least one machine learning model. Hardware specifications of the chipset are accessed to identify the available hardware compute elements. Based on the hardware specifications, the functional modules are synthesized into a plurality of interconnected executable components configured to execute on at least two different hardware compute elements. An implementation package is generated, comprising the executable components and metadata describing interconnections between them. The implementation package is then deployed to the chipset, where the executable components are executed by the identified hardware compute elements.

When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks for different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks are enforced.

A computer implemented method for defect recognition in an imaging dataset of a wafer in a charged particle beam system comprising an embedded system, the method comprising: i) obtaining an imaging dataset of a wafer; ii) obtaining model data for a model architecture of a machine learning model for defect recognition in the imaging dataset of the wafer, the model architecture being implemented in the embedded system; iii) transferring the model data to a programmable memory of the embedded system; and iv) applying the machine learning model to an imaging dataset of a wafer to recognize defects, comprising executing the embedded system implemented model architecture with the transferred model data.

In a general aspect, enhancement of artificial intelligence algorithms using 3D data is described. In some aspects, input data of an object is stored in a storage engine of a system. The input data includes first-order primitives and second-order primitives. A plurality of features of the object is determined by operation of an analytics engine of the system, based on the first-order primitives and the second-order primitives. A tensor field is generated by operation of the analytics engine of the system. The tensor field includes an attribute set, which includes one or more attributes selected from the first-order primitives, the second-order primitives, or the plurality of features. The tensor field is processed by operation of the analytics engine of the system according to a series of artificial intelligence algorithms to generate output data representing the object.

The invention discloses a multi-view collaborative 3D Gaussian splash optimization method and system, and the method comprises the steps: constructing a multi-level heterogeneous video memory pool, and dynamically dividing a video memory in 3D Gaussian reconstruction into a view exclusive memory block and a global shared memory pool; a mixed rendering-gradient pipeline is designed, and hardware-level pipeline parallelism in 3D Gaussian reconstruction is realized through a double-buffer asynchronous switching mechanism based on a CUDA Warp-level parallel primitive fusion forward rendering and back propagation thread group; performing multi-view gradient joint optimization, screening an effective gradient path in 3D Gaussian reconstruction based on the visibility mask matrix, and performing projection error weighted fusion on a multi-view gradient tensor; and implementing a multi-modal densification decision, generating a 3D Gaussian candidate splitting position in 3D Gaussian reconstruction through Monte Carlo sampling, calculating a joint optimization objective function by combining a multi-view projection residual error and a gradient contribution factor, and finally realizing 3D Gaussian reconstruction. According to the invention, high-precision and low-delay large-scale scene real-time rendering and training can be realized.

Techniques are disclosed relating to distributing geometry work in a graphics processor. In some embodiments, multiple geometry pipelines are configured to process, in parallel, multiple segments of a set of geometry work. In some embodiments, control circuitry is configured to split operations from the set of graphics work into the multiple segments. This may include parsing a control stream for the set of graphics work to determine an initial work estimate based on numbers of primitives in different draw calls and adjusting the initial work estimate based on a complexity determination for the draw call.

Approaches presented herein provide for the generation of synthesized data from input noise using a denoising diffusion network. A higher order differential equation solver can be used for the denoising process, with one or more higher-order terms being distilled into one or more separate efficient neural networks. A separate, efficient neural network can be called together with a primary denoising model at inference time without significant loss in sampling efficiency. The separate neural network can provide information about the curvature (or other higher-order term) of the differential equation, representing a denoising trajectory, that can be used by the primary diffusion network to denoise the image using fewer denoising iterations.

To display a low-resolution image at higher resolution and furthermore to reduce an afterimage.SOLUTION: Resolution is made higher by super-resolution processing. In this case, the super-resolution processing is performed after frame interpolation processing is performed. Further in that case, the super-resolution processing can be performed using a plurality of processing systems. Therefore, super-resolution processing can be performed at high speed even when frame frequency is made higher. An afterimage can be reduced since frame rate doubling is performed by frame interpolation processing.SELECTED DRAWING: Figure 1

A sliced graphics processing unit (GPU) architecture in a processor-based device is disclosed. In some aspects, a GPU based on a slicing GPU architecture includes a plurality of hardware slices. The GPU also includes command processor (CP) circuitry and a non-slice primitive controller (PCUS). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuitry determines a graphics workload and sends the graphics workload to the PCUS. The PCUS then divides the graphics workload into a plurality of sub-batches, and distributes each sub-batch to the PCS of the hardware slice for processing.

A system and a method for displaying super-resolution images generated from images of lower resolution, includes processor circuitry for a combination multi-core CPU and machine learning engine configured with an input for receiving the low resolution images, a feature extraction section to extract features from the low resolution images, non-linear feature mapping section, connected to the feature extraction section, generating feature maps using a self-calibrated block with pixel attention having a plurality of Depthwise Separable Convolution (DSC) layers, a late upsampling section combines at least one DSC layer and a skip connection that upsamples the feature maps to a predetermined dimension, and a video output for displaying approximate upsampled super-resolution images that corresponds to the low resolution images.

The invention provides a frame insertion processing method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a first texture and a second texture obtained through rendering before the first texture, the first texture and the second texture are UI-free textures, splicing the first texture and the second texture to obtain a spliced texture, and storing the spliced texture in a storage medium; a feature extraction network in a frame insertion model is adopted to perform multi-dimensional feature extraction on the spliced texture to obtain a target optical flow feature map and a target mask feature map, the feature extraction network is deployed in an NPU, and a frame insertion network in the frame insertion model is adopted to obtain frame insertion texture according to the target optical flow feature map and the target mask feature map, the frame insertion network is deployed in the GPU, and the frame insertion model is deployed in the GPU and the NPU, so that the hybrid programming of the GPU and the NPU is realized, the algorithm advantages of two kinds of hardware are fully played, and the processing efficiency of the frame insertion model is improved.

An image capture system provides automated prompts for aiding a user in capturing images for use in 3D model creation. While a user is preparing to capture an image, the system provides visual indications that indicate whether a quality-based condition is satisfied. Based on the visual indications, a user can determine whether an image, if captured, would likely be suitable for use in creating a 3D model. Determining if the quality-based condition is satisfied may include monitoring output generated by one or more sensors and comparing the output against a threshold value. Additionally, the system may analyze the visual content or metadata associated with an image to determine if the quality-based condition is satisfied and request user input to further identify certain image features that were identified by the system.

A processor includes a first processing pipeline, a second processing pipeline and a memory management that allocates memory regions from memory for the first processing pipeline to write the data of each of a first of a sequence of tasks, and deallocates each of the memory regions after the data therein has been processed by the second processing pipeline. A blocking circuit enables the second processing pipeline to start processing a second sequence of tasks while the memory management circuit is still deallocating some of the memory regions allocated to the data portions of the first of said sequence of tasks, the blocking circuit preventing identifiers of the data portions of the second task being passed to the memory management circuit until the memory management circuit indicates that it has completed deallocating the memory regions allocated to all the data portions of the first task.

The embodiment of the invention provides a screen cleaning method and device, electronic equipment and a readable medium, and relates to the technical field of display, in the method, vertex coordinates, width pixel values and height pixel values defined in a predefined screen cleaning area structural body and screen cleaning color values defined in a screen cleaning color structural body are pushed to a designated register of a GPU. And respectively reading the vertex coordinate, the width pixel value, the height pixel value and the clear screen color value from the specified register by a shader. And rendering all pixels in the display area indicated by the vertex coordinates, the width pixel value and the height pixel value according to the screen cleaning color value to realize screen cleaning. The vertex coordinate, the width pixel value, the height pixel value and the screen cleaning color value are directly pushed to the specified register, so that a shader can directly and conveniently obtain the vertex coordinate, the width pixel value, the height pixel value and the screen cleaning color value required by screen cleaning from the specified register. The screen cleaning efficiency can be improved, and efficient screen cleaning is achieved.

The invention provides a rendering system, a chip, equipment and a rendering method applied to the rendering system, and relates to the technical field of image rendering. The rendering system comprises a rendering pipeline manager, a middle buffer area, M geometric processing pipelines and N pixel processing pipelines, wherein a plurality of data segments divided from an input data stream of the rendering system are allocated to M geometric processing pipelines for processing, and primitive data obtained by processing each data segment is stored in a middle buffer area; the rendering pipeline manager is used for acquiring serial numbers and memory information of the data segments processed by the geometric processing pipeline; the rendering pipeline manager is further used for sending rendering instructions to the N pixel processing pipelines respectively, the rendering instructions comprise the serial numbers and the memory information of the k data segments, k is an integer larger than or equal to 1, and the serial numbers of the k data segments are continuous under the condition that k is larger than 1. According to the method, the image rendering efficiency is improved.

An Artificial Intelligence (AI) computational system for generating an embryo viability score from a single image of an embryo to aid selection of an embryo for implantation in an In-Vitro Fertilisation (IVF) procedure is described. The AI model uses a deep learning method applied to images in which the Zona Pellucida region in the image is identified using segmentation, and ground truth labels such as detection of a heartbeat at a six week ultrasound scan.

The invention discloses a video memory management method and system, a chip and electronic equipment, and belongs to the technical field of storage. The method comprises the following steps: acquiring respective heat information of a plurality of storage units included in a first chip through a first logic unit, wherein the heat information is used for indicating use conditions of the storage units; data in at least one target storage unit is compressed through a second logic unit, and the target storage unit is determined from the multiple storage units by the second chip based on the obtained heat information of the multiple storage units; wherein the first chip is different from the second chip. According to the method, the target storage unit can be determined from the multiple storage units based on the use condition of the storage units, and the data in the target storage unit is compressed, so that the storage space occupied by the data in the video memory is reduced, and the available storage capacity of the video memory is effectively expanded.

For direct multi-volume rendering, each voxel of a volume has a scalar value. A multi-ray generator generates a view multi-ray in the direction of a pixel of a projection image, wherein the pixel represents a 2D projection of all scene voxels intersecting with the view multi-ray behind the projection image. A volume ray marching processor processes each view ray, wherein, at each ray marching step, the scalar value of the corresponding voxel is mapped to a color value and a transparency value of said corresponding voxel. A projection image updater updates the value of the particular pixel in the projection image by combining the respective voxel color and transparency values of the individual view rays. Updating with the values of a particular voxel intersecting with a particular view ray is performed after the updating with all intersecting voxel values of voxels closer to the viewing point than the particular voxel.

The invention provides a chip system and a method for reading data, relates to the technical field of chips, and improves the performance of a graphics processor. According to the specific scheme, the chip system comprises a graphics processor and a memory manager, and the graphics processor is used for responding to a graphics rendering task and outputting a first reading instruction to the memory manager. And the memory manager is used for reading the first data from the memory based on the first virtual address and the partition mapping table in response to the first reading instruction. The memory manager is further used for outputting the first data to the graphics processor. The method is used for the process that the graphics processor reads the data in the memory.

Approaches presented herein provide for the generation of synthesized data from input noise using a denoising diffusion network. A higher order differential equation solver can be used for the denoising process, with one or more higher-order terms being distilled into one or more separate efficient neural networks. A separate, efficient neural network can be called together with a primary denoising model at inference time without significant loss in sampling efficiency. The separate neural network can provide information about the curvature (or other higher-order term) of the differential equation, representing a denoising trajectory, that can be used by the primary diffusion network to denoise the image using fewer denoising iterations.

Apparatuses and methods for block friendly ray traversal are disclosed. An apparatus and method for efficient storage of BVH nodes in a block. For example, one embodiment of an apparatus includes a bounding volume hierarchy (BVH) construction circuit to construct a BVH based on primitives of a graphical scene; and block allocation hardware logic coupled to or integral with the BVH fabric circuitry, the block allocation hardware logic to allocate a plurality of nodes of the BVH into a plurality of blocks for storage in a cache or memory subsystem, the block allocation hardware logic is to maximize a number of blocks comprising a leader parent node of a plurality of nodes and one or more corresponding child nodes.

A development platform for implementing a machine learning pipeline on a chip containing multiple hardware compute elements. The development platform includes a user interface, a library of software blocks, and a synthesis engine. The user interface facilitates a user to develop a functional description of the machine learning pipeline. The functional description specifies multiple functional modules, including a machine learning model. The synthesis engine synthesizes the pipeline of functional modules into multiple interconnected executable components of software blocks and generates an implementation package including the executable components and specifying interconnections between the executable components.

Illustrative embodiments of the present disclosure include a method, a device, and a product for a Graphics Processing Unit (GPU) cluster. The method includes: obtaining a graph of interconnections between GPUs in the GPU cluster; forming a parallel hierarchical architecture of the GPU cluster based on the graph of interconnections between GPUs; and mapping parallel tasks to the parallel hierarchical architecture to execute the parallel tasks. The method for a GPU cluster according to the present disclosure ensures that high-speed GPU-GPU connection is used for tasks with high communication requirements, thus improving the overall processing efficiency of the GPU cluster.

The invention relates to an image rendering method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the steps of receiving rendering information; the rendering information is generated when the graphic application sends a rendering request; analyzing the rendering information, and creating a graphic task; the graphic task comprises a plurality of cache objects; the cache object is used for storing image data in the rendering process; the cache object carries a virtual address; when the physical space is allocated to each cache object, mapping the virtual address of each cache object to a physical address to obtain a page table mapping relation; generating a to-be-written page table item based on the page table mapping relation of each cache object, and sending the to-be-written page table item to the GPU; and the GPU writes the page table mapping relation into the corresponding page table item according to the to-be-written page table item so as to establish an access path between the GPU and the physical address, and the GPU executes the graphic task based on the access path. By adopting the method, the mapping efficiency can be improved.

An image capture system provides automated prompts for aiding a user in capturing images for use in 3D model creation. While a user is preparing to capture an image, the system provides visual indications that indicate whether a quality-based condition is satisfied. Based on the visual indications, a user can determine whether an image, if captured, would likely be suitable for use in creating a 3D model. Determining if the quality-based condition is satisfied may include monitoring output generated by one or more sensors and comparing the output against a threshold value. Additionally, the system may analyze the visual content or metadata associated with an image to determine if the quality-based condition is satisfied and request user input to further identify certain image features that were identified by the system.

Disclosed are an information processing method and a terminal device. The method comprises: acquiring first information, wherein the first information is information to be processed by a terminal device; calling an operation instruction in a calculation apparatus to calculate the first information so as to obtain second information; and outputting the second information. By means of the embodiments in the present disclosure, a calculation apparatus of a terminal device can be used to call an operation instruction to process first information, so as to output second information of a target desired by a user, thereby improving the information processing efficiency.

The invention provides a graphics processor, a texture loading method, a texture processing unit, equipment and a medium, and relates to the technical field of image texture loading. The method comprises the following steps: uniformly distributing texture loading instructions to a texture processing unit for execution, wherein the texture loading instructions comprise texture cache loading instructions; analyzing and executing the texture loading instruction through the texture processing unit; wherein the texture state information of the texture loading instruction is obtained through hardware analysis of the texture processing unit, the texture loading instruction completes address calculation and data reading in an independent texture loading pipeline, and the texture loading pipeline is started in the texture processing unit. According to the technical scheme, the scheduling logic of the texture loading instruction can be simplified, the compatibility of dynamic resources is improved, meanwhile, the hardware utilization rate is increased, and the reliability and execution efficiency of texture data access are improved.

The invention relates to the technical field of visual sensing modules, and discloses a sensing-storage-calculation integrated bionic visual sensing module in-storage calculation method and system.The method comprises the steps that photo-induced electrons excited by incident photons are directly injected into memristor oxygen vacancy conductive filaments through a shared electrode interface, and photocurrent driving signals are obtained; in a forward SET mode, driving memristor oxygen vacancy conductive filaments to form cross array conductivity distribution, and calculating row line driving voltage of a memristor cross array; applying the current to each cross point of cross array conductance distribution in a reverse RESET mode to obtain a flowing current of each cross point; and converging and summing the flowing current of each cross point at a column line node to obtain a column line output current, performing capacitor charging integration on the column line output current, and converting the column line output current into an analog domain convolution operation voltage, thereby avoiding intermediate multiple analog-to-digital and digital-to-analog conversion loss. And end-to-end low-delay and low-power-consumption processing from photon sensing to feature calculation is realized.