1110 results about "Video memory" patented technology

An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh. In some embodiments, the circuitry may further include shift registers and one or more arithmetic logic units to provide a video memory.

A video memory manager manages and virtualizes memory so that an application or multiple applications can utilize both system memory and local video memory in processing graphics. The video memory manager allocates memory in either the system memory or the local video memory as appropriate. The video memory manager may also manage the system memory accessible to the graphics processing unit via an aperture of the graphics processing unit. The video memory manager may evict memory from the local video memory as appropriate, thereby freeing a portion of local video memory use by other applications. In this manner, a graphics processing unit and its local video memory may be more readily shared by multiple applications.

A system for filing applications with an institution from a plurality of remote sites, and for automatically processing said applications in response to each applicant's credit rating obtained from a credit reporting service comprising a series of self-service terminals remotely linked via a telephone line to a first computer at the institution and to a second computer at the credit reporting service headquarters. Each remote terminal comprises a video screen and a video memory which holds image-and-sound-generating information arranged to simulate the aspect and speech of an application loan officer on the video screen. The simulated loan officer is used to acquire loan request data from the applicant by guiding him through an interactive sequence of inquiries and answers. The system may be utilized as a trading network whereby stations are used by sellers and buyers to place and accept offers for securities, the central installation acting as a central computerized database where all transactions are processed and the various data items stored and automatically updated.

A personal computer motherboard has a main memory of phase-change-memory (PCM) chips in PCM memory modules. An operating system (OS) image is stored in the PCM memory modules and is retained during suspend since the PCM chips are non-volatile. The microprocessor can directly read the OS image retained in the PCM memory modules without copying an OS image from a hard disk to the main memory upon resume. Therefore a boot loader program in the boot ROM does not have to be fetched to the microprocessor for suspend/resume. The video memory can also be PCM, allowing the frame buffer to be retained during suspend/resume, yet be directly addressable by the microprocessor. The display is quickly activated since the frame buffer does not have to be re-constructed after suspend/resume. PCM cells use amorphous and crystalline states of a variable resistor to store data.

A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

A binocular endoscope operation visual system mainly comprises a binocular endoscope, an image server and an endoscope stereo display unit. Two ways of clear abdominal cavity image video signals are obtained by the binocular endoscope, two ways of video streams enter a memory of an image processing server or a video memory by a two-way image capture card, and a left-way image and a right-way image which are processed are respectively displayed in a left displayer and a right displayer. By a flat mirror, the contents of the left displayer and the right displayer respectively enter the left eye and the right eye of an observer, thereby the stereo effect is realized. The binocular endoscope operation visual system is suitable for the circumstance of a medical surgical endoscope operation, can completely satisfy the stereoscopic vision requirement of a laparoscope operation of a minimally invasive operation robot, realizes the binocular stereoscopic vision real-time display in the laparoscope operation, has reliable performance, simple structure and high commercialization level, and adapts the germfree circumstances of the operation.

Methods and systems are provided for cryptographically protecting secure content in connection with a graphics subsystem of a computing device. Techniques are implemented to encrypt the contents of video memory so that unauthorized software cannot gain meaningful access to it, thereby maintaining confidentiality. Moreover, a mechanism for tamper detection is provided so that there is awareness when data has been altered in some fashion, thereby maintaining integrity. In various embodiments, the contents of overlay surfaces and/or command buffers are encrypted, and/or the GPU is able to operate on encrypted content while preventing its availability to untrusted parties, devices or software.

A parallel data processing method based on multiple graphic processing units (GPUs) is provided, including: creating, in a central processing unit (CPU), a plurality of worker threads for controlling a plurality of worker groups respectively, the worker groups including one or more GPUs; binding each worker thread to a corresponding GPU; loading a plurality of batches of training data from a nonvolatile memory to GPU video memories in the plurality of worker groups; and controlling the plurality of GPUs to perform data processing in parallel through the worker threads. The method can enhance efficiency of multi-GPU parallel data processing. In addition, a parallel data processing apparatus is further provided.

A video camera and recording device integrated with a real or toy weapon to provide video recording of the assault and aiming process of the weapon holder in operational training, actual combat, hunting, sports and gaming scenarios. A video camera is boresighted with the weapon, and a video memory stores the recorded dynamic scenario, and a trigger sensor which continually senses and records the triggering actions imposed by the weapon holder. The trigger sensor is attached to the actual trigger of the weapon thus enabling normal operation of the weapon. The video camera, may be mounted internally within the bore of the weapon, such that the external form of the weapon is not altered, thus achieving closer operation to real life situations. The recorded trigger data is utilized upon playback of the recorded video, enabling quick review and scoring of the recorded aiming process for training and gaming.

A video sub-system features reduced power consumption by integrating a video memory onto the same chip as the video memory controller. The video memory is preferably a small DRAM sufficiently large to store all pixel data for lower resolutions, but insufficient for higher resolutions. At higher resolutions, an external DRAM supplements the internal DRAM. The amount of external DRAM needed depends upon the resolution to be supported. The internal DRAM has a wide data bus and thus high bandwidth, since no external I/O pins are needed. The external DRAM is narrow to minimize pincount and power consumption. Since the external DRAM is slower and lower in bandwidth, pixel data from both internal and external DRAMs are interleaved together for each horizontal scan line. Thus the lower bandwidth of the external DRAM is masked by the high bandwidth of the wide internal DRAM. Either the internal or the external DRAM, or both, are automatically tested with a pseudo-random number generator that writes pseudo-random numbers to the DRAM while simultaneously supplying pixel data to the graphics data path for display. A checksum of the pixel data output from the graphics data path is generated for the first screen of pixels or frame, while on the second frame the pseudo-random number generator is disabled and the DRAM supplies the same pixel data that was written to it by the pseudo-random number generator during the first frame. The checksums for the first and second frames should match if the DRAM is free of faults.

Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map.

A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

The invention discloses a neural network construction method and device and an image processing method and device in the field of computer vision in the artificial intelligence field. The neural network construction method comprises the following steps: determining a search space and a plurality of construction units; stacking the plurality of construction units to obtain a search network, with the search network being a neural network for searching a neural network structure; and optimizing a network structure of a construction unit in the search network in the search space, wherein in the optimization process, the search space is gradually reduced, the number of the construction units is gradually increased, and due to the reduction of the search space and the increase of the number of the construction units, the video memory consumption generated in the optimization process is within a preset range; and establishing the target neural network according to the optimized construction unit. Under the condition that video memory resources are certain, the neural network meeting application requirements well can be constructed.

The present invention provides a system and method for realizing split-screen display. The display screen is logically divided into N display areas. The system includes: a display controller, video memory and N display drivers, wherein the video memory contains N Each display driver corresponds to a display area respectively, and each display area corresponds to a display area respectively, and the N is an integer more than 2; when the display driver is called by an upper-level application program (APP), obtain the described The data of the APP is written or updated to the corresponding video memory area; the video memory area buffers the data to be displayed in the corresponding display area; the display controller reads the data of each video memory area and transmits it to the corresponding display area of ​​each video memory area . The present invention realizes split-screen display on the same display screen, without customizing the display screen, and ensures the independence of each display area.

The invention provides a method for sliding an interface of a touch screen and a terminal. The method comprises the following steps of: when entering an interface supporting sliding, drafting the data of the current interface in a memory, and drafting the data of the interface supporting the sliding in a buffer zone applied for in advance except the data of the current interface; and after a message of touching movement in the current interface is received, if judging that the effective distance of the touching movement of a touching article reaches a preset value, copying a screen of data corresponding to the preset value from the buffer zone in the memory, and refreshing the current interface in real time. In the method, a mode of directly operating the memory to refresh the screen whenthe interface contents are updated along with the sliding is adopted, so that the sliding speed and efficiency of the interface are effectively improved.