33 results about "Instruction scheduling" patented technology

The application discloses a kind of air-cooled refrigerator CAN bus multi-node instruction scheduling method and system, it is related to refrigerator control technical field, it is solved in the air-cooled refrigerator multi-node CAN bus control scene, when sudden heat load of freezing chamber, emergency refrigeration switching instruction is easily crowded by ordinary periodic message and leads to the problem of execution lag, first build cabinet temperature acquisition result, message category and periodic occupation relationship, then according to temperature deviation, temperature rise rate, door opening disturbance and forecast overrun result generate cabinet emergency degree, and form emergency refrigeration instruction set and ordinary message degradation set, then according to basic cycle division synchronous reference window, emergency exclusive window, key feedback window and ordinary arbitration window, make emergency refrigeration instruction priority transmission and priority confirmation, finally according to key message response delay, cabinet recovery state and ordinary message backlog situation iteration correction next round of scheduling parameters, to improve the timeliness and stability of multi-node collaborative control under sudden load scenario.

This disclosure presents a scheduling optimization processor, instruction scheduling method, apparatus, medium, and product. The scheduling optimization processor includes multiple arithmetic pipelines and a physical register file. Each arithmetic pipeline is connected to at least two write-back caches. The number of instruction types with different execution latencies supported by the arithmetic pipeline is n. The write-back cache contains several cache partitions, with the number of cache partitions being n-1. According to the enqueue order of the cache partitions, the arithmetic pipeline writes the execution results of instructions into the idle write-back cache. In each clock cycle, the write-back cache writes the valid execution results from the last-level cache partition into the physical register file. This processor can achieve ordered buffering and parallel write-back of multiple instruction execution results by configuring multiple write-back caches for a single arithmetic pipeline and adopting a cache partition structure that matches the execution latency. This eliminates write conflicts in the physical register file at the hardware level, significantly improving processor issue efficiency and operating performance.

This invention discloses a staged multi-policy instruction scheduling method and system for VLIW architecture. The method includes: basic step S1. Receiving the symbolic assembly structure (SAS); S2. Configuring three types of scheduling vision interfaces and registering corresponding scheduling policies, including a global vision interface, a loop vision interface, and a linear vision interface; S3. Executing loop vision scheduling, traversing all loop blocks, and concurrently calling the loop vision interface to generate candidate scheduling schemes; S4. Executing linear vision scheduling, after all loop blocks have been scheduled, traversing the remaining unscheduled basic blocks, and concurrently calling the linear vision interface to generate candidate schemes; S5. Performing competitive selection and register allocation on the candidate scheduling schemes generated in each stage; S6. Outputting the optimized SAS. This invention can efficiently adapt to various VLIW processor architectures, improving instruction-level parallelism and code execution efficiency.

This disclosure provides a computing unit, instruction execution method, processor, device, medium, and program, relating to the field of computer technology, specifically information processing, deep learning, artificial intelligence, and chip technology. The computing unit is integrated within a processor and includes multiple computing modules connected via a network. The computing unit is used to: receive control signals and vector data generated by decoding a target instruction; select a target computing module from among the computing modules based on the control signals, and determine the data flow direction of the vector data in the target computing module based on the network connection; and sequentially execute the fused instruction calculation operation of the target instruction through each target computing module according to the control signals and the data flow direction of the vector data. Embodiments of this disclosure can improve the performance of instruction scheduling within the computing unit, thereby improving the overall computing performance of the computing unit.

Embodiments relate to atomic memory operations with floating point values. An example processor comprises: a control register to store rounding mode and denormal mode control bits to indicate a rounding mode and denormal value processing mode; fetch circuitry to fetch a remote atomic operation (RAO) floating point (FP) instruction comprising a memory location to store at least one FP result value; decode circuitry to decode the instruction and scheduling circuitry to offload the instruction to an execution engine external to the logical processor or to schedule the decoded instruction for local execution, wherein an indication of the rounding mode and denormal value processing mode is communicated to the execution engine, the indication to be communicated by a transfer of one or more of the rounding mode control bits and denormal mode control bits to a storage coupled to the execution engine, or to be communicated in the message.

A system and method for power and latency reduction when processing thread execution code in a multithreaded architecture is disclosed. The method includes receiving a plurality of threads, each thread including a plurality of instructions for execution on one of a plurality of cores of processing circuitry; detecting a plurality of subsequent independent instructions in a first thread of the plurality of threads; and inserting an instruction hint into an instruction, the instruction hint, when executed, configuring an instruction scheduler of the processing circuitry to serially execute the plurality of subsequent independent instructions.

The application discloses a processor, a processing method and related equipment, wherein the processor comprises a processor core, the processor core comprises an instruction scheduling unit, a graph computing flow unit connected with the instruction scheduling unit and at least one general-purpose computing unit; wherein the instruction scheduling unit is configured to distribute general-purpose computing instructions in decoded to-be-executed instructions to the at least one general-purpose computing unit and distribute graph computing control instructions in the decoded to-be-executed instructions to the graph computing unit, the general-purpose computing instructions are used to instruct to execute general-purpose computing tasks, and the graph computing control instructions are used to instruct to execute graph computing tasks; the at least one general-purpose computing unit is configured to execute the general-purpose computing instructions; and the graph computing flow unit is configured to execute the graph computing control instructions. By using the application, the processing efficiency of the processor can be improved.

This patent discloses a scheduling control method and system for assembly lines based on continuous state evolution, applicable to complex assembly lines under multi-process and multi-resource constraints. The method first continuously models the execution conditions of assembly processes, forming a state expression that reflects the executability of the processes. Based on this, a scheduling focus is constructed according to the current main constraints of the production line, guiding the overall direction of scheduling decisions. Simultaneously, the assembly quality state is introduced into the scheduling state system in the form of reliability decay, allowing quality factors to participate in state evolution during the scheduling process. During scheduling operation, the system forms an ordered execution sequence and generates scheduling instructions. After the scheduling instructions are issued to the execution layer, their execution feedback drives the continuous updating of relevant states, thus forming a closed-loop scheduling control process. Through the above methods, adaptive adjustment of scheduling decisions is achieved, improving the operational stability and scheduling efficiency of the assembly line under complex constraints.

This invention discloses a device management and communication method and system for a domestically developed operating system in a satellite weak network environment. The method includes: after a system cold start or reset, performing initialization operations, loading a pre-compiled object model by the cloud platform, and transmitting the object model data to the device; the device collects data and monitors temperature changes in real time; when the temperature change exceeds a preset threshold, the collected data is simplified and encoded based on the object model, and the encoded data is transmitted to the cloud platform; when the cloud platform needs to perform instruction scheduling, it transmits the instruction and a globally unique token to the device, which verifies the token and executes the instruction after successful verification; the device transmits the result of the instruction execution as a response data to the cloud platform, and the cloud platform parses the response data to obtain the instruction execution result. This invention can improve communication efficiency in a satellite weak network environment and enhance the reliability and controllability of device management and communication.

This invention discloses a method for collaborative operation control between a quadruped robot arm and target equipment in cable tunnels, belonging to the field of intelligent control technology. The method includes: after the quadruped robot enters the work area, it executes preset tasks through its robotic arm and collects motion accuracy, interaction force, and temporal operation data, which are then normalized and labeled to form a dataset; statistical and temporal features of the dataset are extracted and concatenated into a task feature sequence according to the task execution order; this sequence is input into a task prediction model, and when the robot executes the final stage of the current task group, the model outputs the prediction result for the initial stage of the next task group. Based on the prediction results, collaborative control instructions for motion accuracy and interaction force are generated, and instruction scheduling is performed through a cache queue combined with a deviation threshold mechanism to ensure that instructions are injected and executed in an orderly manner when the system is stable. This invention achieves advanced prediction and smooth control of task execution, improving the continuity, adaptability, and reliability of robot operations.

Systems and methods are described for scheduling instructions corresponding to a computer program. A neural instruction scheduler operates by iterating over all the basic blocks (BBs) in the directed acyclic graph (DAG). The nodes of the DAG, which represent instructions in the form of compiler IR, are tokenized such that tokens retrieve embeddings from an embedding space. These embeddings are aggregated into a single vector that represents the instructions in a latent semantic space. The embeddings are fed into a value estimator which predicts performance metrics associated with scheduling each valid instruction and compares them against one another to determine which instruction to pick next. The process of picking the next instruction can begin using the same approach. This process is autoregressively repeated for all valid instructions. Candidate instruction schedule(s) with identified ordering of instructions are output and an instruction schedule is selected to schedule each basic block.

The present disclosure relates to the technical field of processors. Provided are a processor structure based on odd-even scheduling and allocation, and a chip and an electronic device. In the processor structure based on odd-even scheduling and allocation provided in the present disclosure, a free physical register file is divided into an odd part and an even part in a renaming phase, and whether an odd physical register or an even physical register is allocated for the current renaming operation is determined according to an instruction type. The embodiments provided by the present disclosure can reduce by half the number of write ports of a register file, and can effectively perform the allocation and instruction scheduling of physical registers in combination with a register allocation balancing algorithm.

The application discloses a kind of based on the instruction scheduling optimization method of Bisheng compiler of Peng platform, storage medium, equipment and computer program product, comprising: obtaining the source program to be scheduled by Bisheng compiler on Peng platform, whether source program is legal using context-independent grammar judgment;The power consumption required for scheduling illegal source program is calculated and sorted, and the sub-functions in the illegal source program are rearranged by dependency graph construction algorithm in turn to the illegal source program sorted from small to large;Illegal source program in sub-function is modified by log analysis method in turn to the illegal source program sorted from large to small;Illegal source program is handled using the above two methods from two ends to middle, and then whether the source program is legal after processing is judged;If still illegal, exchange two kinds of methods to handle illegal source program, judge whether the source program is legal again, if legal, carry out instruction scheduling by Bisheng compiler;Otherwise, mark the illegal source program, and alarm.

The application relates to the technical field of industrial automation control, and particularly provides a multi-device cooperative control method for a press, which comprises the following steps: decomposing a process task into multiple subtasks to be executed in sequence; establishing a unified time reference, dividing an action window for each subtask based on the action window of the press subtask, and defining a time-space forbidden area according to the action window; obtaining a communication delay parameter of a first robot and a second robot, and differentiating to calculate instruction issuing time of each device, wherein the advance amount of the second robot issuing time is greater than that of the first robot; issuing the instruction according to the instruction issuing time, and judging whether there is a behavior of violating the time-space forbidden area according to real-time feedback of the device and the current time reference, and if yes, triggering a safety response. Through the unified time reference, differentiating instruction scheduling and time-space forbidden area monitoring, high-precision cooperative control of heterogeneous devices is realized, and production safety and beat stability are improved.

This application relates to a hardware-based microscaling method, system, computer device, computer-readable storage medium, and computer program product. The method includes: receiving a microscaling instruction sent by an instruction scheduling unit, the microscaling instruction carrying configuration information, including the address information of the original data block, target quantization format information, and global memory address information of the target data block; parsing the configuration information from the microscaling instruction; using the hardware circuit structure built into the microscaling module to implement operations such as obtaining the original data block from the address information of the original data block, scaling and quantizing the original data block based on the target quantization format information, and associating the scaled and quantized target data block and the scaling factor into global memory based on the global memory address information. This method can free up the computing power of vector cores and improve the computational efficiency of artificial intelligence chips.

A method, apparatus and medium related to data processing are involved. The method proposed herein includes: obtaining, with a plurality of shaders, a plurality of portions of first data respectively; storing the plurality of portions of first data into a plurality of on-chip storage units associated with the plurality of shaders respectively; in response to completion of the storing of the first data, adjusting the plurality of shaders to a first mode, the first mode indicating that the plurality of shaders are divided into a first shader and at least one second shader, and instruction scheduling of the at least one second shader is paused; in response to a first instruction initiated by the first shader, loading second data into a common storage unit; in response to a second instruction initiated by the first shader, broadcasting, with an on-chip network, the second data in the common storage unit to the plurality of shaders; and performing, with the plurality of shaders, a matrix multiplication operation based on the second data and corresponding portions of the first data stored in the plurality of on-chip storage units.

This invention proposes a multi-level optimization execution method and system for a smart contract virtual machine based on the Go language. By constructing a three-level collaborative optimization architecture, it significantly improves execution efficiency and resource utilization. The intermediate code optimization layer integrates automatic vectorization technology with a dynamic profile-guided optimization recompilation mechanism driven by production environment configuration, breaking through the performance bottleneck of the core algorithm. The memory management optimization layer expands the underlying memory pool of the Go language and introduces an application-layer automated pooling mechanism, effectively reducing memory pressure and connection overhead. The instruction scheduling optimization layer combines dynamic time slice adjustment for computationally intensive tasks at the single-core level with optimistic locking concurrent execution technology for multi-core multi-version concurrency control, achieving efficient task collaboration. Through static compilation optimization, dynamic resource adaptation, and a full-process collaborative mechanism, a dynamic balance between high performance and low latency is achieved in scenarios such as encrypted computing and multi-core concurrency, providing a high-performance and highly scalable execution solution for the Go language smart contract virtual machine.

The application relates to the computer technical field, in particular to a register-allocated instruction scheduling method and device, a computer device and a storage medium. The method comprises the following steps: obtaining a machine instruction sequence to which a physical register has been allocated; determining scheduling dependency information and scheduling characteristic information of each instruction corresponding to the machine instruction sequence; constructing a global instruction scheduling model according to the scheduling dependency information and the scheduling characteristic information; the global instruction scheduling model comprises scheduling constraint information determined according to the scheduling characteristic information; solving the global instruction scheduling model to obtain target transmission periods corresponding to the instructions, with the scheduling constraint information being a solving condition, the transmission clock period of each instruction being a solving variable, and the earliest clock period in which all the instructions are executed completely being a solving target; and allocating and scheduling the instructions in a register-allocated instruction scheduling stage based on the target transmission periods. The application provides an instruction scheduling method with better scheduling effect.

This invention discloses a method, apparatus, and device for extracting contract information based on multi-level prompt word instructions. The method includes: acquiring the digital signal of the contract document to be processed; identifying business type tags through layout analysis and semantic clustering; then, using an instruction scheduling engine, calling and reconstructing multi-level instruction modules from a preset instruction library based on the tags to assemble a complete multi-level instruction stream; finally, injecting the complete multi-level instruction stream into an intelligent processing module, driving the intelligent processing module to complete the contract information extraction according to the instruction stream constraints, and outputting standardized structured data after verification and auditing. The multi-level instruction module is a three-layer architecture consisting of a decoupled system meta-instruction layer, an atomic rule configuration layer, and a semantic reasoning audit layer. These layers are independent of each other, and lower-level modules cannot modify the upper-level constraint rules. This invention solves the problems of instruction bloat, subject ambiguity, black-box unauditability, and weak generalization ability.

This invention relates to an instruction-level performance analysis method, system, and storage medium for DSA (Digital Subtraction Animation). The instruction-level performance analysis method includes the following steps: encoding and recording tracking events during the instruction execution process of DSA to obtain tracking data for the entire instruction lifecycle; allocating storage resources and managing bus bandwidth for the tracking data to reduce storage usage and bus bandwidth consumption; and co-optimizing instruction scheduling and tracking acquisition based on hardware execution unit configuration to ensure that the tracking event encoding and recording, tracking data storage, and bandwidth management processes do not interfere with normal system operation. This invention significantly improves the storage / bandwidth friendliness and real-time processing capabilities of the tracking system.

The present specification relates to the technical field of integrated circuits, and particularly relates to a multi-core system atomic instruction scheduling method, system and device, the method comprising: determining an atomic instruction near-end execution reliability index according to the number of times of successful near-end execution of the atomic instruction in a historical period; scheduling an execution position of the atomic instruction in a hierarchical cache according to the hit condition of to-be-processed data in the hierarchical cache, the data exclusive state of the to-be-processed data and the atomic instruction near-end execution reliability index, to obtain a scheduling execution result; and updating the atomic instruction near-end execution reliability index according to the scheduling execution result. The application can perceive the competition degree of access to a critical section in a multi-core scenario, dynamically adjust atomic instruction near-end execution and remote execution according to the system atomic instruction execution state, and improve the atomic instruction execution efficiency.

This invention provides a data storage device and its operation instruction scheduling method. The data storage device includes a controller and non-volatile memory. The controller includes a register, which includes a power consumption index list. The non-volatile memory is used to store multiple instructions. The controller executes the multiple instructions to implement the operation instruction scheduling method, which includes: determining that a first operation instruction to be executed is a power-consuming operation instruction; determining that a first field of the first part of the power consumption index list stores the first operation instruction such that a first valid bit corresponding to the first field is enabled; executing the first operation instruction on the non-volatile memory based on the first valid bit; and clearing the first field and the first valid bit when receiving an operation instruction completion signal for the first operation instruction.

The invention discloses an instruction execution device and method, a chip, a board card and equipment, and belongs to the field of chips. The device comprises a first scheduling assembly, a second scheduling assembly and an execution assembly, the output end of the first scheduling assembly is connected with the input end of the execution assembly, and the output end of the second scheduling assembly is connected with the input end of the execution assembly; the first scheduling component is responsible for scheduling an instruction sequence for a first thread, the second scheduling component is responsible for scheduling a branch instruction sequence for a second thread, the execution component comprises at least two execution channels, and the at least two execution channels are in one-to-one correspondence with the threads; the first scheduling component is used for scheduling a first branch instruction in the instruction sequence to the execution component; the second scheduling component is used for scheduling a second branch instruction in the instruction sequence to the execution component; and the execution component is used for executing the first branch instruction and the second branch instruction in parallel through at least two execution channels. By adopting the scheme provided by the embodiment of the invention, the utilization rate of the processor can be improved.

The embodiment of the present specification provides a resource event processing method and device, wherein the resource event processing method comprises: performing resource parameter switching detection of a resource platform on each user according to a resource pre-configuration event; if the switching detection is passed, querying a user state based on a target scheduling instruction in a scheduling instruction sequence constructed to each user, and scheduling the target scheduling instruction to a resource processing system for resource configuration response processing based on the user state, so as to realize scheduling judgment of instruction scheduling of each user from multiple stages by combining resource parameter switching detection and user state.

The disclosure provides a load store circuit, a processor and an electronic device, and relates to the technical field of computers.The load store circuit comprises an instruction scheduling module, an address generation module, a memory access execution module, a data adjustment module and a buffer module, wherein: the instruction scheduling module is configured to receive a memory access instruction corresponding to a current thread to be executed, and analyze instruction control data corresponding to the memory access instruction; the data adjustment module is configured to determine an access target corresponding to the memory access instruction according to general address data, adjust the instruction control data based on the access target, and obtain control optimization data; the address generation module is configured to generate a target access address corresponding to the memory access instruction by using the control optimization data and the general address data; the memory access execution module is configured to execute a memory access operation on the access target according to the target access address; and the general address buffer in the buffer module is configured to store the general address data.The scheme enables the memory access instruction based on the general address to be completed independently on the hardware side.

This invention discloses a multi-node instruction scheduling method and system for a CAN bus in an air-cooled refrigerator, relating to the field of refrigerator control technology. It solves the problem that in multi-node CAN bus control scenarios of air-cooled refrigerators, when a sudden heat load occurs in the freezer compartment, emergency cooling switching instructions are easily overwhelmed by ordinary periodic messages, leading to execution delays. The method first constructs the relationship between the compartment temperature acquisition results, message types, and periodic occupancy. Then, based on temperature deviation, temperature rise rate, door opening disturbance, and predicted over-limit results, it generates the compartment urgency level, forming an emergency cooling instruction set and an ordinary message degradation set. Next, it divides the window into a synchronization reference window, an emergency exclusive window, a critical feedback window, and an ordinary arbitration window according to the basic period, ensuring that emergency cooling instructions are sent and acknowledged first. Finally, iteratively corrects the scheduling parameters for the next round based on the critical message response delay, the compartment recovery status, and the backlog of ordinary messages, thereby improving the timeliness and stability of multi-node collaborative control under sudden load scenarios.