137 results about "Instruction scheduling" patented technology

The invention provides a data processor and method, electronic equipment and a storage medium, the data processor comprises an instruction scheduler and a copy engine, the instruction scheduler comprises a first tensor access register, and the first tensor access register is used for storing sub-tensor description information transmitted externally; the replication engine comprises a first queue structure, a second tensor access register and an instruction decoder, the second tensor access register is used for storing sub-tensor description information received from the first queue structure, and the instruction decoder is used for analyzing an instruction received from the first queue structure and generating a control signal to drive data handling; wherein the instruction scheduler is configured to dynamically detect a change parameter item of the sub-tensor description information, and write the change parameter item into the first queue structure, so that the copy engine incrementally updates the sub-tensor description information in the second tensor access register based on the change parameter item, therefore, the data transmission redundancy can be reduced, and the data transmission efficiency is improved. And the instruction processing efficiency is improved.

The invention discloses a multi-nozzle collaborative printing method, and particularly relates to the technical field of printing path planning. According to the method, a three-dimensional space mesh model is constructed by collecting structural feature information of a target printing area; calculating collaborative coverage parameters of the sub-regions according to the space coverage capability and the region curvature characteristics of the nozzle; constructing a priority map based on nozzle performance and task suitability, and performing task matching by adopting a minimum cross entropy objective function to generate an initial path allocation scheme; constructing a jet printing path conflict graph, extracting conflict feature points, performing local path reconstruction by using a graph convolutional neural network, and generating an optimized jet printing path; and finally, the multiple nozzles are driven to cooperatively execute a jet printing task through time synchronization and instruction scheduling. According to the invention, the conflict rate and waiting time of the nozzles can be obviously reduced, the path planning efficiency and the jet printing precision are improved, and the method has good engineering applicability.

The invention discloses a task scheduling method, a task scheduling device, electronic equipment and a readable storage medium, and relates to the technical field of task scheduling, the method comprises the steps that a first copy instruction is scheduled through an instruction scheduling unit, and the first copy instruction is used for instructing a single copy engine to carry a target tensor; receiving the first copy instruction through the task splitting unit, splitting the target tensor indicated by the first copy instruction into a plurality of sub-tensors, generating a plurality of second copy instructions, and correspondingly scheduling the plurality of second copy instructions to the plurality of copy engines, all the copying engines complete tensor carrying of the target tensor together; wherein the second copying instruction is used for indicating the single copying engine to carry one sub-tensor obtained by splitting the target tensor. The method and the device have the effects of effectively improving the load balance between the replication engines and improving the parallel efficiency and the throughput at the same time.

The invention relates to the technical field of computers, and discloses an equipment protocol adaptive analysis and instruction scheduling method for an intelligent central control system, and the method comprises the steps: obtaining an original communication data flow of heterogeneous equipment, and extracting a protocol feature fingerprint to recognize a protocol type; calling a corresponding pluggable protocol parser to generate a standardized instruction object; analyzing instruction semantics and dynamically calculating priorities in combination with a system load; and performing non-blocking scheduling and execution monitoring on the instruction based on a resource token bucket mechanism. The system comprises a data acquisition module, a protocol identification module, a self-adaptive analysis module, a semantic analysis module, a priority calculation module, an instruction sorting module, a token management module, a scheduling execution module, an execution monitoring module and a response generation module. According to the method, through protocol self-learning, dynamic priority quantification and multi-dimensional resource isolation scheduling, the response certainty, expansibility and operation stability of the system in a high-concurrency scene are remarkably improved.

The invention discloses a digital in-memory computing accelerator, an instruction set architecture and a data processing method thereof, and belongs to the technical field of in-memory computing. The digital memory computing accelerator comprises a chip-level module, a core-level module and a unit-level module, the chip-level module is used for acquiring a target calculation task, splitting the target calculation task into a plurality of core-level calculation tasks according to a load distribution strategy and distributing the core-level calculation tasks to the core-level module; the core-level module comprises a control unit, a calculation unit and a cache unit, and the control unit comprises an instruction fetching module, a decoding module and an instruction scheduler; an instruction fetching module reads a to-be-executed instruction corresponding to the core-level calculation task, a decoding module decodes the to-be-executed instruction to generate a control signal and sends the control signal to a calculation unit, and the to-be-executed instruction is an instruction of a calculation instruction set architecture in a digital memory; the calculation unit executes corresponding calculation operation according to the control signal; the cache unit caches intermediate data generated by executing the corresponding calculation operation.

The invention provides a loading storage circuit and a graphics processor, and relates to the technical field of graphics processing. The loading storage circuit comprises an instruction scheduling module, an address generation module and a data service module, and is provided with a buffer area module which comprises an operand buffer area and an effective data buffer area and is used for caching information required by address calculation and data access; the instruction scheduling module is used for collecting a data access instruction and outputting instruction information; the address generation module calculates a target access address according to the instruction information and the operand; and the data service module executes corresponding data loading or storage operation on the target cache unit. According to the scheme, the operands and the valid data are pre-cached, so that overflow and stagnation caused by inconsistent processing rhythms among modules can be avoided, and the parallel processing capability of an assembly line is improved; through the independent address calculation and data access process, the stability of the access time sequence and the data processing efficiency can be improved.

The present disclosure provides a store instruction scheduling method and apparatus, a device, and a storage medium. The solution comprises: acquiring a plurality of target cache entries; setting a status bit register and a countdown register for each target cache entry; within any clock cycle, decrementing the countdown of the register by one, and changing the status bit set for a target cache entry into which a store instruction is written; determining whether the number of occupied target cache entries is greater than or equal to a first threshold, determining whether the countdown of the countdown register is zero, and determining whether the status bit of the status bit register set for each target cache entry is equal to a second threshold, so as to obtain a second determination result, and on the basis of the second determination result, changing the status bit and resetting the countdown; and when the set status bit is equal to the second threshold, writing the store instruction cached in each target cache entry into a cache memory. Thus, there is no need to continuously occupy a cache port and bandwidth.

The invention relates to a multi-path power supply parallel automatic test system and a test method. The multi-path power supply parallel automatic test system comprises a main control module, an instruction scheduling module, a test instrument group and a plurality of test fixtures, each test fixture is used as an independent test channel with self-defined configuration; a request signal input end of the main control module is connected with a request signal output end of the independent test channel, a test signal input end of the main control module is connected with a test signal output end of the test instrument group, and a control signal output end of the main control module is connected with a control signal input end of the instruction scheduling module; the signal output end of the instruction scheduling module is connected with the signal input end of the test instrument group, and the test instrument group is used for executing corresponding test operation on the to-be-tested power supply according to the control signal; the testing efficiency is remarkably improved, manual operation is reduced, and the basic capability of automatic parallel testing of multiple power supplies is achieved.

The invention provides a general purpose computing unit and an instruction scheduling method for the general purpose computing unit. The general-purpose computing unit comprises a plurality of execution units, wherein each execution unit is used for executing an operation instruction by taking a thread bundle as a unit; and an instruction scheduler for determining a priority of the plurality of operation instructions based on whether the multiplexing flag exists, and scheduling each operation instruction to one of the plurality of execution units based on the priority; wherein each execution unit comprises one or more reuse registers, each reuse register is used for registering an operand of a previous operation instruction and a label, and the label is used for indicating an address and a thread bundle of the operand; and the instruction decoding unit is used for decoding the received operation instruction to determine the reading position of the operand of the operation instruction. The instruction is preferentially scheduled by adding a reuse mark to the whole operation instruction, so that the hit rate of the operand is improved, and excessive instruction bit fields do not need to be occupied.

The invention provides a power resource dynamic scheduling and security tracing system and method based on edge computing and block chain fusion, and the system employs a hierarchical collaborative architecture, and comprises an edge computing layer, a block chain layer and a cross-layer security module. The edge layer collects photovoltaic output and load demand data, and predicts short-term output and load through LSTM. The ACEGA algorithm is combined with the micro-service priority and the edge node resource state to generate a scheduling instruction; and the scheduling instruction hash value is subjected to uplink evidence storage, the energy storage device is triggered to charge and discharge after verification of the smart contract, and meanwhile, a green power consumption voucher is recorded. According to the invention, power resource dynamic scheduling optimization, data credibility evidence storage and security protection are realized, the problems of distributed new energy consumption, energy storage resource configuration and power transaction tracing are solved, and the defects of low edge computing scheduling efficiency, high data security risk and insufficient cross-technology collaboration in the prior art are overcome.

The invention provides a hardware resource scheduling method and a hardware scheduler used in a graphics processing unit. The hardware resource scheduling method used in the graphics processing unit comprises the following steps: for any hardware computing unit in the graphics processing unit, acquiring task or instruction queue state information indicating whether a task or instruction queue of the hardware computing unit is in an idle state or a full state from the hardware computing unit; receiving, from a driver system of the graphics processing unit, priority ranking information indicating a priority ranking between respective hardware computing units inside the graphics processing unit; and based on the task or instruction queue state information and the priority ranking information of the hardware computing unit, judging whether the task or instruction to be scheduled to the hardware computing unit is scheduled to the hardware computing unit, and if so, scheduling the task or instruction to be scheduled to the hardware computing unit to the hardware computing unit.

The embodiment of the invention discloses a micro-grid two-stage robust optimization scheduling method and device, equipment and a medium, and the method comprises the steps: building a mixed integer linear programming model for a target micro-grid according to the equipment information of the target micro-grid by taking the minimization of the total operation cost of the target micro-grid as a first target function; solving the mixed integer linear programming model to obtain a first scheduling scheme; minimizing the adjustment cost in the target scene as a second target function, and constructing a robust optimization scheduling model for the target micro-grid, the adjustment cost including the adjustment abandoning cost and the load reduction cost in the target scene; based on the first scheduling scheme, solving the robust optimization scheduling model by using a preset target algorithm to determine a target scheduling scheme; and sending a control instruction to the micro-grid according to the target scheduling scheme, and scheduling the target micro-grid to operate. According to the scheme, operation of the micro-grid under significant uncertainty can be managed, and multi-device collaborative robust optimization scheduling of the micro-grid is realized.

The application discloses a kind of air-cooled refrigerator CAN bus multi-node instruction scheduling method and system, it is related to refrigerator control technical field, it is solved in the air-cooled refrigerator multi-node CAN bus control scene, when sudden heat load of freezing chamber, emergency refrigeration switching instruction is easily crowded by ordinary periodic message and leads to the problem of execution lag, first build cabinet temperature acquisition result, message category and periodic occupation relationship, then according to temperature deviation, temperature rise rate, door opening disturbance and forecast overrun result generate cabinet emergency degree, and form emergency refrigeration instruction set and ordinary message degradation set, then according to basic cycle division synchronous reference window, emergency exclusive window, key feedback window and ordinary arbitration window, make emergency refrigeration instruction priority transmission and priority confirmation, finally according to key message response delay, cabinet recovery state and ordinary message backlog situation iteration correction next round of scheduling parameters, to improve the timeliness and stability of multi-node collaborative control under sudden load scenario.

This disclosure presents a scheduling optimization processor, instruction scheduling method, apparatus, medium, and product. The scheduling optimization processor includes multiple arithmetic pipelines and a physical register file. Each arithmetic pipeline is connected to at least two write-back caches. The number of instruction types with different execution latencies supported by the arithmetic pipeline is n. The write-back cache contains several cache partitions, with the number of cache partitions being n-1. According to the enqueue order of the cache partitions, the arithmetic pipeline writes the execution results of instructions into the idle write-back cache. In each clock cycle, the write-back cache writes the valid execution results from the last-level cache partition into the physical register file. This processor can achieve ordered buffering and parallel write-back of multiple instruction execution results by configuring multiple write-back caches for a single arithmetic pipeline and adopting a cache partition structure that matches the execution latency. This eliminates write conflicts in the physical register file at the hardware level, significantly improving processor issue efficiency and operating performance.

The invention discloses a scheduling-driven high-level comprehensive array division method, which comprises the following steps of: creating an associated access instruction set for arrays in algorithm design, and analyzing an address calculation expression of each access instruction; on the basis of the control data flow diagram designed by the algorithm, instruction scheduling is executed according to an instruction topological sequence and circuit performance requirements, for an array access instruction, a schedulable interval of the array access instruction is calculated, control steps in the interval are traversed, and incremental address conflicts introduced by each scheduling mode are determined; aiming at each scheduling mode of the array access instruction, a minimum overhead array division scheme capable of solving all address conflicts is searched, and the overhead of the division scheme comprehensively considers the number of storage modules after division, address control logic complexity and time delay; the address conflicts comprise the incremental address conflicts and the stock address conflicts. The method has the advantages that compared with an existing array division scheme, calculation scheduling and array division are organically combined, the cost of array division is reduced, and the scheduling performance is improved.

The invention provides a temperature and humidity price tag application control instruction scheduling method and system, and the method comprises the steps: extracting the deployment position information of a task, the environment response characteristics of a commodity type, the temperature and humidity trend, standardizing the multi-dimensional characteristics, and carrying out the dynamic clustering, thereby achieving the optimal task grouping under environment consistency and resource constraint; according to the method, the task execution priority in the cluster is determined in combination with a distributed state machine, a control instruction is generated and issued according to a collaboration result, clustering parameters are adaptively adjusted through a feedback closed-loop mechanism, and the execution efficiency of batch electronic price tag updating, the environment response adaptive capacity and the edge resource utilization rate are improved.

The present application provides a latency processing unit that may include the following: a plurality of multiply-accumulate (MAC) trees configured to perform a matrix product operation on at least one of a plurality of partitions implementing an artificial intelligence (AI) model; the streaming memory access module is configured to establish connection between each of the plurality of MAC trees and a high-bandwidth memory in which the at least one partition is stored through a plurality of channels; a vector execution engine configured to perform an additional operation on operation results of the plurality of MAC trees; the local storage unit is configured to store an operation result and an activation value of the vector execution engine; and the instruction scheduling unit is configured to schedule the operation processes of the plurality of MAC trees and the vector execution engines.

This invention discloses a staged multi-policy instruction scheduling method and system for VLIW architecture. The method includes: basic step S1. Receiving the symbolic assembly structure (SAS); S2. Configuring three types of scheduling vision interfaces and registering corresponding scheduling policies, including a global vision interface, a loop vision interface, and a linear vision interface; S3. Executing loop vision scheduling, traversing all loop blocks, and concurrently calling the loop vision interface to generate candidate scheduling schemes; S4. Executing linear vision scheduling, after all loop blocks have been scheduled, traversing the remaining unscheduled basic blocks, and concurrently calling the linear vision interface to generate candidate schemes; S5. Performing competitive selection and register allocation on the candidate scheduling schemes generated in each stage; S6. Outputting the optimized SAS. This invention can efficiently adapt to various VLIW processor architectures, improving instruction-level parallelism and code execution efficiency.

Performing criticality-based instruction scheduling in processor devices is disclosed herein. In some aspects, a processor device executes a compiler that generates an initial schedule comprising a plurality of instructions. The compiler constructs a directed graph based on the initial schedule, with each directed graph node corresponding to an instruction of the plurality of instructions, and each directed edge of the directed graph indicating an instruction dependency. The compiler calculates criticality metrics for each directed graph node, and generates a max heap data structure based on the criticality metrics. The compiler determines an optimized schedule comprising the plurality of instructions by iteratively identifying a root node of the max heap data structure as a node having a highest criticality metric, scheduling an instruction corresponding to the root node, and removing the root node from the max heap data structure. The processor device then executes the instructions according to the optimized schedule.

A graphics processor, an instruction scheduling method, a terminal device and a medium, the graphics processor comprising: a scheduling module, an instruction cache module, a memory access dynamic scheduling module, a unified description cache module, a read-write module and a texture module, wherein: the memory access dynamic scheduling module is adapted to receive a first instruction transmitted by the scheduling module, obtain corresponding first description register information based on the first instruction; after determining that the first instruction supports dynamic scheduling based on the first description register information, determine whether to schedule the first instruction to the read-write module or the texture module based on the load state of the read-write module and the load state of the texture module; and the unified description cache module is adapted to feed back the first description register information to the memory access dynamic scheduling module based on the type of the first instruction. The above scheme can balance the load of the texture module and the read-write module, and improve the execution efficiency of the memory access instruction.

The invention relates to an instruction scheduling method and apparatus, a semiconductor device and a medium. The method comprises the steps of storing a plurality of received service instructions of a service process; distributing a corresponding time slice for each service instruction of the stored service process; and under the condition that the received control instruction indicates that the service process needs to be started, sending the service instruction in the corresponding time slice. According to the method, the efficient execution of the instruction can be realized, the uncertainty caused by communication with the service process in the instruction execution process is eliminated, and the communication reliability is high; and a specific hardware architecture does not need to be adapted, so that the compatibility is good.

This disclosure provides a computing unit, instruction execution method, processor, device, medium, and program, relating to the field of computer technology, specifically information processing, deep learning, artificial intelligence, and chip technology. The computing unit is integrated within a processor and includes multiple computing modules connected via a network. The computing unit is used to: receive control signals and vector data generated by decoding a target instruction; select a target computing module from among the computing modules based on the control signals, and determine the data flow direction of the vector data in the target computing module based on the network connection; and sequentially execute the fused instruction calculation operation of the target instruction through each target computing module according to the control signals and the data flow direction of the vector data. Embodiments of this disclosure can improve the performance of instruction scheduling within the computing unit, thereby improving the overall computing performance of the computing unit.

The invention relates to a resource scheduling method and device based on a large electric power model and computer equipment. The resource scheduling method comprises the following steps: constructing a hardware capability matrix and a model demand matrix based on storage structure characteristics and electric power large model parameters; constructing a matching degree evaluation function according to the hardware capability matrix and the model demand matrix, and determining a matching degree evaluation result; determining a pruning strategy according to a matching degree evaluation result; determining model parameter storage capacity according to a pruning strategy and hardware storage granularity; pruning and compressing the large electric power model according to the model parameter storage capacity to obtain a target compression model; performing computational graph decomposition on the target compression model to obtain a plurality of sub-graphs; according to the hardware capability matrix, a calculation unit is correspondingly distributed to each sub-graph, and a hardware instruction scheduling sequence is generated; and performing resource scheduling based on the hardware instruction scheduling sequence. The use energy consumption of the large electric power model can be effectively reduced, the computing resource utilization rate is improved, and the large electric power model can be cooperatively matched with different hardware platforms.

The invention discloses a disease-related content automatic typesetting and background manuscript storage system and method, belongs to the field of digital content processing, and solves the problems that in the prior art, efficiency is low, formats are not uniform, metadata matching is prone to error, and a publishing link is split. The system comprises an instruction scheduling module, a disease-driven content generation module, a semantic typesetting engine module, a metadata assembly module and an API transmission manuscript storage module which are coordinated in sequence. The method comprises five steps of instruction receiving, content generation, typesetting conversion, metadata assembly and background manuscript storage, and cross-platform accurate typesetting and material automatic matching are realized through style mapping, a null line standardization algorithm and a disease mapping matrix. According to the method, time consumed by single processing is shortened to be within 10 seconds, typesetting standardization and zero content error are ensured, multi-disease and multi-background batch processing and timed manuscript storage are supported, and the distribution efficiency and quality of disease science popularization content are remarkably improved.

Embodiments of the present application provide a data transmission scheduling method and apparatus, a communication device, and a storage medium. The method can include transmitting a first scheduling instruction to a User Equipment (UE) in a N-th time domain unit, where the first scheduling instruction schedules the UE to transmit uplink data in a (N+K)-th time domain unit, and the N and the K are both natural numbers, and transmitting, between the N-th time domain unit and the (N+K)-th time domain unit, at least one second scheduling instruction to the UE, where the second scheduling instruction schedules the UE to transmit uplink data.

A graphics processor, an instruction execution method, a terminal device, and a medium, the graphics processor comprising: an instruction cache coupled to a constant data cache, identifying a first instruction in response to a received instruction queue including the first instruction, and executing a target instruction in response to an identification result that the first instruction is a target instruction; sending a constant data request to a constant data cache, and transmitting a first instruction to a scheduler; the target instruction comprises a target register, a source register, a constant data cache view and a constant data cache view parameter; and the constant data cache is suitable for outputting the target constant data indicated by the first instruction to the actuator after receiving the constant data request. The scheduler is suitable for scheduling the first instruction to the actuator after receiving the first instruction; and the executor is suitable for executing the first instruction and sending an execution result to the target register. Therefore, the instruction execution efficiency of the graphics processor is improved.

The invention discloses a regional power load prediction and scheduling service platform and method based on cloud edge collaboration, and relates to the technical field of big data processing. The regional power load prediction and scheduling service platform and method based on cloud edge collaboration comprises the steps of S1, collecting equipment operation data and instruction scheduling data of regional power for preprocessing operation, and compressing and storing the data to construct a regional power scheduling management database; s2, analyzing the synchronization state between the cloud and the edge node by analyzing the event time difference and the equipment state deviation; s3, evaluating the conflict degree between the cloud and the edge node by analyzing the equipment state, the load difference, the synchronous pressure and the response characteristics; and S4, according to the equipment state change, the frequency fluctuation and the conflict detection analysis result, performing oscillation risk quantitative evaluation. The problem of insufficient load adjustment stability caused by asynchronous data states, easy conflict of scheduling instructions and equipment oscillation in power load prediction in communication interruption and recovery scenes is solved.

The invention discloses a VR system multi-modal feedback synchronous driving method based on time sequence calibration, and relates to the technical field of multi-modal feedback synchroniss.The method comprises the steps that when a user interaction event is detected, the event is captured, and an initial timestamp is recorded; based on the timestamp, task scheduling and resource pre-allocation are carried out through a quantum heuristic scheduling algorithm; predicting a dynamic delay compensation value of each mode by using a neural symbol AI model; calculating the accurate triggering time fed back by each mode according to the compensation value; executing high-priority parallel instruction scheduling at the calculated time point; the driving hardware outputs feedback and collects actual execution time to optimize subsequent scheduling, synchronous driving is achieved in an operating system kernel layer, dynamic delay prediction and compensation are combined, the problem of timing sequence misalignment caused by hardware heterogeneous delay and software scheduling uncertainty of multi-mode feedback is solved, synchronous control of microsecond-level precision is achieved, and the service life of the system is prolonged. And the immersion and robustness of the VR system are improved.