229 results about "Instruction scheduling" patented technology

The embodiment of the invention provides an instruction processing method and a processor, and the method comprises the steps: obtaining a to-be-executed instruction, and determining a conflict type of the to-be-executed instruction; distributing a physical register for the to-be-executed instruction based on the conflict type; determining a dependency conflict condition and a resource conflict condition of the to-be-executed instruction, and determining an execution sequence of the to-be-executed instruction based on the dependency conflict condition and the resource conflict condition; determining a target execution unit based on the execution sequence, and sending the instruction to be executed to the target execution unit; and controlling the target execution unit to execute the to-be-executed instruction, and writing the to-be-executed instruction into the physical register when the to-be-executed instruction is executed, so that efficient out-of-order execution is realized through refined conflict detection, resource allocation and instruction scheduling, and the performance of the RISC-V processor can be remarkably improved. And the adaptability to complex applications is enhanced.

According to the instruction processing system, method and device provided by the invention, the instructions can be efficiently and smoothly distributed and run through the at least one processing module of the processor, and different instruction distribution logics are adopted based on different types of business processing instructions through two-stage instruction distribution, so that the service processing efficiency is improved. The business processing instructions are stored in the target storage area and then scheduled to the instruction execution module, so that quick distribution and hardware support of different types of business processing instructions are realized, the instruction distribution efficiency is greatly improved, complex calculation tasks can be flexibly and efficiently processed, instruction scheduling can be performed according to the priorities of the business processing instructions, and the service processing efficiency is improved. The key business operation is ensured to be responded and processed in time, and the overall performance and the operation efficiency of the database processor are effectively improved. The technical effect of flexibly and efficiently processing the database acceleration task is achieved.

The invention provides a robot control instruction analysis method and system fusing continuous instructions, and relates to the technical field of electric digital data processing, and the method comprises the steps: carrying out the quantitative evaluation of the instruction execution quality and resource consumption according to prediction data, and generating a quality score and a consumption estimation; constructing a multi-objective optimization framework based on the quality score and the consumption estimation, and determining a candidate path set; switching cost and execution time are calculated according to the candidate path set, and optimized path schemes meeting constraint conditions are screened; the instruction execution priority and the resource allocation proportion are adjusted in combination with the real-time environment data, and a scheduling strategy is generated. According to the method, environment changes and task quality are monitored in real time, instruction priorities and resource allocation are dynamically adjusted, when execution efficiency is lower than a threshold value, online updating of a prediction model is triggered, model parameters are finely adjusted to adapt to new conditions, and through continuous optimization and monitoring, the execution efficiency and task quality of an instruction sequence can be improved, and the execution efficiency is improved. And intelligent instruction scheduling and resource allocation are realized.

The present application discloses a compute-in-memory chip, an instruction scheduling method, and a related apparatus. The compute-in-memory chip comprises an instruction memory, an instruction scheduler, and at least one compute-in-memory memory; each compute-in-memory memory comprises at least one storage array; the instruction memory is used for acquiring a first tensor instruction to be executed; and the instruction scheduler is used for scheduling, on the basis of the association relationship between the first tensor instruction and a second tensor instruction and the state of a target storage array needing to be operated for executing the first tensor instruction, the first tensor instruction to the compute-in-memory memory to which the target storage array belongs so that the compute-in-memory memory executes the first tensor instruction. According to embodiments of the present application, diversified compute-in-memory computing can be supported, efficient out-of-order execution scheduling of a tensor instruction set is achieved on the basis of the compute-in-memory chip, and the requirements of compute-in-memory technology for high concurrency and high throughput rate are met.

The invention provides a vector core module of an artificial intelligence chip and an operation method of the vector core module, which are used for improving the efficiency of the vector core module in an application situation that a vector core is a host and a tensor core module is a slave. The vector core module comprises a vector core instruction execution pipeline, a tensor core instruction processing pipeline and an instruction scheduling unit. An instruction scheduling unit performs instruction classification to distinguish vector core instructions and tensor core instructions from a thread bundle. In response to the thread bundle including a vector core instruction, the instruction scheduling unit sends the vector core instruction to a vector core instruction execution pipeline. The vector core instruction execution pipeline executes the vector core instruction and stores an execution result in the memory module. In response to the thread bundle including a tensor core instruction, the instruction scheduling unit sends the tensor core instruction to a tensor core instruction processing pipeline. The tensor core instruction processing pipeline processes the tensor core instruction and sends a processing result to the tensor core module.

The invention discloses an instruction scheduling method, device and system, a product and a medium, and relates to the technical field of processor design. The invention provides an instruction scheduling method aiming at the problem that the dynamic change in the instruction transmitting time cannot be accurately scheduled by the existing out-of-order scheduling strategy. The historical delay information of each instruction is stored through the delay cache, and when the instruction execution delay corresponding to the instruction is dynamic delay, the dynamic delay is predicted through the historical delay information stored in the delay cache, so that instruction scheduling is performed. According to the method, the dynamic delay of which the delay time cannot be predetermined is included in the consideration range of instruction scheduling based on the dynamic delay prediction mechanism. On the basis of the method, for dynamic change scenes in instruction transmission time such as memory access delay and cache miss, the optimal instruction transmission opportunity can be accurately predicted, so that the effect of instruction scheduling on performance improvement of a processor is further improved.

The invention discloses an instruction scheduling device and method, a processor, electronic equipment and a storage medium. The instruction scheduling device comprises a running processor core, the processor core schedules a plurality of thread bundles, the plurality of thread bundles comprise a first thread bundle and a second thread bundle, the device comprises an arbitration unit and an instruction sharing unit, the arbitration unit is configured to obtain an instruction fetching request provided by the first thread bundle and provide the instruction fetching request to the instruction sharing unit, and the instruction sharing unit is configured to share the instruction with the first thread bundle. The instruction fetching request comprises current instruction fetching information; the instruction sharing unit is configured to determine whether other thread bundles except the first thread bundle in the plurality of thread bundles comprise current instruction data matched with the current instruction fetching information in response to the instruction fetching request; and in response to the second thread bundle including the current instruction data, obtaining the current instruction data from the second thread bundle, and providing the current instruction data to the first thread bundle. According to the instruction scheduling device, the instruction fetching bandwidth can be reduced, the bandwidth pressure can be relieved, and the thread beam instruction obtaining speed can be increased.

The invention provides a network processor and a related instruction scheduling method, relates to the technical field of chips, and can improve the execution efficiency of instructions. The network processor comprises a scheduler, a plurality of scheduling control modules and a plurality of cache queues. The plurality of scheduling control modules are used for obtaining a first number of instructions from each cache queue in the plurality of non-empty cache queues, generating a scheduling request based on first indication information of the first number of instructions in each non-empty cache queue so as to obtain a plurality of scheduling requests, and sending the plurality of scheduling requests to the scheduler, the scheduler is used for responding to a plurality of scheduling requests and sending at least one scheduling response signal to the at least one scheduling control module, and the at least one scheduling control module is further used for responding to the at least one scheduling response signal and generating to-be-executed instruction words based on a first number of instructions in a target cache queue and a target scheduling mode.

The invention provides a data processor and method, electronic equipment and a storage medium, the data processor comprises an instruction scheduler and a copy engine, the instruction scheduler comprises a first tensor access register, and the first tensor access register is used for storing sub-tensor description information transmitted externally; the replication engine comprises a first queue structure, a second tensor access register and an instruction decoder, the second tensor access register is used for storing sub-tensor description information received from the first queue structure, and the instruction decoder is used for analyzing an instruction received from the first queue structure and generating a control signal to drive data handling; wherein the instruction scheduler is configured to dynamically detect a change parameter item of the sub-tensor description information, and write the change parameter item into the first queue structure, so that the copy engine incrementally updates the sub-tensor description information in the second tensor access register based on the change parameter item, therefore, the data transmission redundancy can be reduced, and the data transmission efficiency is improved. And the instruction processing efficiency is improved.

The invention discloses a multi-nozzle collaborative printing method, and particularly relates to the technical field of printing path planning. According to the method, a three-dimensional space mesh model is constructed by collecting structural feature information of a target printing area; calculating collaborative coverage parameters of the sub-regions according to the space coverage capability and the region curvature characteristics of the nozzle; constructing a priority map based on nozzle performance and task suitability, and performing task matching by adopting a minimum cross entropy objective function to generate an initial path allocation scheme; constructing a jet printing path conflict graph, extracting conflict feature points, performing local path reconstruction by using a graph convolutional neural network, and generating an optimized jet printing path; and finally, the multiple nozzles are driven to cooperatively execute a jet printing task through time synchronization and instruction scheduling. According to the invention, the conflict rate and waiting time of the nozzles can be obviously reduced, the path planning efficiency and the jet printing precision are improved, and the method has good engineering applicability.

The invention discloses a compiler optimization method and device and a storage medium, and belongs to the technical field of computers. The method comprises the steps of obtaining a vector length corresponding to an access operation in a compiling language; the vector length is related to the number of elements included in the memory address to be accessed; under the condition that the vector length is not the power of the preset numerical value and the vector length is greater than a preset threshold value, splitting the access operation according to the vector length to obtain a plurality of sub-access operations; and according to the plurality of sub-access operations, optimizing repeated operations in the compilation language to obtain a compilation optimization result. By standardizing the access operation in the intermediate language of the compiler and splitting the access operation into a plurality of sub-access operations, the repeated sub-access operations in the intermediate language can be eliminated; moreover, in the instruction scheduling process after register allocation, based on the instructions corresponding to the multiple sub-access operations, access conflicts specific to hardware can be eliminated, and the accuracy of compiler optimization results is improved.

The invention discloses a task scheduling method, a task scheduling device, electronic equipment and a readable storage medium, and relates to the technical field of task scheduling, the method comprises the steps that a first copy instruction is scheduled through an instruction scheduling unit, and the first copy instruction is used for instructing a single copy engine to carry a target tensor; receiving the first copy instruction through the task splitting unit, splitting the target tensor indicated by the first copy instruction into a plurality of sub-tensors, generating a plurality of second copy instructions, and correspondingly scheduling the plurality of second copy instructions to the plurality of copy engines, all the copying engines complete tensor carrying of the target tensor together; wherein the second copying instruction is used for indicating the single copying engine to carry one sub-tensor obtained by splitting the target tensor. The method and the device have the effects of effectively improving the load balance between the replication engines and improving the parallel efficiency and the throughput at the same time.

The invention relates to the technical field of computers, and discloses an equipment protocol adaptive analysis and instruction scheduling method for an intelligent central control system, and the method comprises the steps: obtaining an original communication data flow of heterogeneous equipment, and extracting a protocol feature fingerprint to recognize a protocol type; calling a corresponding pluggable protocol parser to generate a standardized instruction object; analyzing instruction semantics and dynamically calculating priorities in combination with a system load; and performing non-blocking scheduling and execution monitoring on the instruction based on a resource token bucket mechanism. The system comprises a data acquisition module, a protocol identification module, a self-adaptive analysis module, a semantic analysis module, a priority calculation module, an instruction sorting module, a token management module, a scheduling execution module, an execution monitoring module and a response generation module. According to the method, through protocol self-learning, dynamic priority quantification and multi-dimensional resource isolation scheduling, the response certainty, expansibility and operation stability of the system in a high-concurrency scene are remarkably improved.

The invention discloses a digital in-memory computing accelerator, an instruction set architecture and a data processing method thereof, and belongs to the technical field of in-memory computing. The digital memory computing accelerator comprises a chip-level module, a core-level module and a unit-level module, the chip-level module is used for acquiring a target calculation task, splitting the target calculation task into a plurality of core-level calculation tasks according to a load distribution strategy and distributing the core-level calculation tasks to the core-level module; the core-level module comprises a control unit, a calculation unit and a cache unit, and the control unit comprises an instruction fetching module, a decoding module and an instruction scheduler; an instruction fetching module reads a to-be-executed instruction corresponding to the core-level calculation task, a decoding module decodes the to-be-executed instruction to generate a control signal and sends the control signal to a calculation unit, and the to-be-executed instruction is an instruction of a calculation instruction set architecture in a digital memory; the calculation unit executes corresponding calculation operation according to the control signal; the cache unit caches intermediate data generated by executing the corresponding calculation operation.

The invention provides a loading storage circuit and a graphics processor, and relates to the technical field of graphics processing. The loading storage circuit comprises an instruction scheduling module, an address generation module and a data service module, and is provided with a buffer area module which comprises an operand buffer area and an effective data buffer area and is used for caching information required by address calculation and data access; the instruction scheduling module is used for collecting a data access instruction and outputting instruction information; the address generation module calculates a target access address according to the instruction information and the operand; and the data service module executes corresponding data loading or storage operation on the target cache unit. According to the scheme, the operands and the valid data are pre-cached, so that overflow and stagnation caused by inconsistent processing rhythms among modules can be avoided, and the parallel processing capability of an assembly line is improved; through the independent address calculation and data access process, the stability of the access time sequence and the data processing efficiency can be improved.

The present disclosure provides a store instruction scheduling method and apparatus, a device, and a storage medium. The solution comprises: acquiring a plurality of target cache entries; setting a status bit register and a countdown register for each target cache entry; within any clock cycle, decrementing the countdown of the register by one, and changing the status bit set for a target cache entry into which a store instruction is written; determining whether the number of occupied target cache entries is greater than or equal to a first threshold, determining whether the countdown of the countdown register is zero, and determining whether the status bit of the status bit register set for each target cache entry is equal to a second threshold, so as to obtain a second determination result, and on the basis of the second determination result, changing the status bit and resetting the countdown; and when the set status bit is equal to the second threshold, writing the store instruction cached in each target cache entry into a cache memory. Thus, there is no need to continuously occupy a cache port and bandwidth.

The invention discloses an instruction scheduling method and system for a cold chain warehouse to control multiple devices, and belongs to the field of cold chain warehouse control, and the method comprises the steps: collecting environment data and device state data in the cold chain warehouse, carrying out the preprocessing of the data, and sending the data to a cloud; the cloud constructs an equipment database in a time sequence according to the timestamps in the message format, and processes data in the equipment database through a cold chain storage cooperative control model; sorting all the generated task requests according to a predefined priority, generating a task queue of a scheduling core, and generating an atomic operation instruction for specific equipment through a rolling time domain optimization algorithm; and sending the operation instruction message to the edge gateway, and sending the native command to the master control of the corresponding equipment through a communication module of the edge gateway. According to the invention, intelligent monitoring and scheduling of the equipment state are realized, and regulation and control can be carried out in time according to environmental changes.

The invention relates to a multi-path power supply parallel automatic test system and a test method. The multi-path power supply parallel automatic test system comprises a main control module, an instruction scheduling module, a test instrument group and a plurality of test fixtures, each test fixture is used as an independent test channel with self-defined configuration; a request signal input end of the main control module is connected with a request signal output end of the independent test channel, a test signal input end of the main control module is connected with a test signal output end of the test instrument group, and a control signal output end of the main control module is connected with a control signal input end of the instruction scheduling module; the signal output end of the instruction scheduling module is connected with the signal input end of the test instrument group, and the test instrument group is used for executing corresponding test operation on the to-be-tested power supply according to the control signal; the testing efficiency is remarkably improved, manual operation is reduced, and the basic capability of automatic parallel testing of multiple power supplies is achieved.

The invention relates to the technical field of processor hardware design, and discloses an ultra-wide RISC-V long vector processor, which comprises a 64-bit scalar RISC-V core and a plurality of vector clusters, wherein each vector cluster comprises an instruction dispatcher and an instruction scheduler, the instruction dispatcher receives vector instructions sent from the scalar core and distributes the instructions to idle processing channels, and the instruction scheduler controls the execution sequence of the instructions in time; each channel is connected with the mask unit, the sliding unit and the vector read-write unit through the full-interconnection crossbar switch, and the full-interconnection crossbar switch and the mask unit carry out conditional execution on elements in a vector instruction based on the mask register. According to the method, the long vector can be quickly and efficiently calculated, the expandability problem of a full interconnection structure is solved by adopting a special layered pipeline interconnection structure, and then long vector support can be carried out on an extended vector processor architecture.

Apparatuses, methods, systems, chip containing products, and computer readable media are disclosed. An apparatus comprises dispatch circuitry to receive instructions, and to identify linear chains of instructions each comprising a first instruction and one or more further instructions, which are temporarily ineligible for execution due to a dependence on an immediately preceding instruction. The apparatus further comprises offline storage circuitry. The dispatch circuitry is configured, for each of the linear chains: to dispatch the sequentially first instruction to the issue circuitry and to retain the one or more further instructions in the offline storage circuitry until a chain trigger signal is received, the chain trigger signal indicating that a previously dispatched instruction, on which a sequentially next instruction depends, has satisfied a predefined issuing condition. In response to receipt of the chain trigger signal, the dispatch circuitry is configured to dispatch the sequentially next instruction to the issue circuitry.

The invention provides vector computing equipment, which comprises an instruction scheduling unit, an instruction decoding unit connected with the instruction scheduling unit, and a plurality of vector kernel execution modules connected with the instruction decoding unit, wherein the plurality of vector core execution modules are connected in series, only one first vector core execution module is connected with the instruction decoding unit, and the instruction scheduling unit is configured to schedule a single-instruction multi-thread instruction and send the SIMT instruction to the instruction decoding unit. And the instruction decoding unit is configured to decode the SIMT instruction to determine an operand address of an operand of the SIMT instruction, and instruct the plurality of vector core execution modules to execute vector operations of the SIMT instruction on the operand in a plurality of clock cycles, respectively.

The invention discloses a virtual power plant distributed power generation instruction distribution method and system for a power distribution network, and the method comprises the steps: firstly carrying out the linearization of a power distribution network AC power flow model, carrying out the modeling of the line active power and node voltage in the power distribution network, and representing the node voltage and the line active power as the mapping of the node power variation; setting constraint conditions including a power balance constraint, a node voltage constraint, a line capacity constraint, an adjustable unit power adjustment upper and lower limit constraint and a climbing rate constraint of each adjustable unit, and constructing a power generation instruction scheduling optimization model taking the highest frequency modulation performance and the lowest carbon emission as double optimization targets; and finally, solving the power generation instruction scheduling optimization model in each control period by adopting a Nesterov momentum acceleration-based distributed algorithm to realize rapid and accurate solving of the instruction, and setting a communication condition to reduce the communication pressure during distributed information exchange and improve the convergence speed of the model. The method is high in convergence speed and high in precision.

The invention provides an instruction-level parallel scheduling method and device in a deep learning compiler, and the method comprises the steps: decomposing a calculation graph of a deep learning task, decomposing a task represented by each calculation graph node on the calculation graph into a hardware calculation instruction according to a current task decomposition scheme, and obtaining an instruction set of the calculation graph; according to the data flow dependency relationship between the nodes on the calculation graph, obtaining a dependency relationship graph between the instructions in the instruction set; dividing the hardware calculation instructions in the instruction set into each sub-core in the processor; according to the dependency graph, determining a directed acyclic graph containing the dependency among the hardware calculation instructions on the sub-cores in the processor, and according to an emission model of the processor and the reciprocal throughput rate of the hardware calculation instructions, determining the execution sequence of the hardware calculation instructions divided to the sub-cores on the sub-cores, and the processor executes the instruction scheduling to obtain an execution result of the deep learning task.

The invention discloses an instruction scheduling system and method and electronic equipment, and relates to the technical field of computers, a dispatch module writes a to-be-scheduled instruction and a renamed register index combination into a dispatch queue, and a dependency check module constructs a dependency linked list according to the dispatch queue so as to determine an instruction execution sequence and send the instruction according to the instruction execution sequence; according to the method, the sending sequence and the execution sequence of the instruction with RAW dependency are ensured to be matched, so that the technical problems of low RAW dependency processing efficiency, long instruction waiting time and waste of pipeline instruction storage resources in the instruction scheduling of the superscale out-of-order processor can be solved, and the execution delay of the instruction is reduced.

The invention provides a pseudo out-of-order instruction scheduling method based on branch jump, belongs to the technical field of processors, is applied to a dispatching and transmitting unit in a superscalar processor, and comprises the following steps: if a currently received instruction is a branch instruction, dispatching the current branch instruction to a branch instruction transmitting queue; judging whether the current branch instruction needs to be speculated and awakened or not; if it is determined that the current branch instruction needs to be speculated and awakened, whether the oldest branch instruction in the branch instruction transmitting queue can be awakened in the two clock periods or not is judged; and if it is determined that the oldest branch instruction in the branch instruction transmitting queue cannot be awakened in the two clock periods, suspending the operation of transmitting other instructions, after the oldest branch instruction, in the branch instruction transmitting queue and the non-branch instruction transmitting queue to the execution unit. Through conditional pause of the branch instruction, the cost of branch prediction errors caused by out-of-order execution is avoided, and the power consumption of a processor is remarkably reduced.

The invention discloses a multifunctional bionic robot intelligent task planning and control method and system, and the method comprises the following steps: S1, collecting and preprocessing multi-source heterogeneous sensing data, and constructing a multi-modal event flow; s2, inputting the multi-modal event stream into an event perception Transform model, and generating a semantic event vector sequence; s3, performing tasks based on the semantic event vector sequence, and constructing a structured task request graph; s4, constructing an optimization controller graph based on the idle execution module and the structured task request graph; s5, inputting the structured task request graph and the optimization controller graph into a distributed evolution graph control module to generate an optimal scheduling mapping relation; s6, generating a control instruction sequence based on the optimal scheduling mapping relation, distributing the control instruction sequence to an idle execution module, and executing action instruction scheduling and control parameter configuration operation; and S7, updating the multi-mode event flow, and repeatedly executing the steps S2 to S6. According to the invention, autonomous task understanding, efficient scheduling and closed-loop control of the bionic robot in a complex task scene are realized.

The invention belongs to the technical field of semiconductors, and particularly relates to a two-channel memory addressing and bus system based on 3D stacking, which comprises at least one intelligent memory processing unit, and the intelligent memory processing unit comprises a DRAM (Dynamic Random Access Memory) storage layer and a logic calculation layer of 3D stacking; a memory in the intelligent memory processing unit is divided into two independent memory channels, each memory channel comprises a plurality of calculation engine groups, each calculation engine group comprises a plurality of calculation engine blocks, and each calculation engine block is correspondingly connected with one DRAM storage unit, one instruction scheduling engine and one memory controller. The dual-channel design is suitable for high-bandwidth and low-delay application scenes such as high-performance calculation, real-time data analysis and image processing.

The invention provides a general purpose computing unit and an instruction scheduling method for the general purpose computing unit. The general-purpose computing unit comprises a plurality of execution units, wherein each execution unit is used for executing an operation instruction by taking a thread bundle as a unit; and an instruction scheduler for determining a priority of the plurality of operation instructions based on whether the multiplexing flag exists, and scheduling each operation instruction to one of the plurality of execution units based on the priority; wherein each execution unit comprises one or more reuse registers, each reuse register is used for registering an operand of a previous operation instruction and a label, and the label is used for indicating an address and a thread bundle of the operand; and the instruction decoding unit is used for decoding the received operation instruction to determine the reading position of the operand of the operation instruction. The instruction is preferentially scheduled by adding a reuse mark to the whole operation instruction, so that the hit rate of the operand is improved, and excessive instruction bit fields do not need to be occupied.

The invention provides a side channel leakage protection method and device of a micro-system structure. The method comprises the following steps: measuring the actual execution duration and the actual consumed energy of the current encryption and decryption operation; obtaining an instruction scheduling word of the next encryption and decryption operation based on the actual execution duration and the actual consumed energy; and adjusting execution of each instruction in the next encryption and decryption operation based on the instruction scheduling word. According to the method and the device provided by the invention, the actual execution duration and the actual consumed energy of the current encryption and decryption operation are measured; obtaining an instruction scheduling word of the next encryption and decryption operation based on the actual execution duration and the actual consumed energy; based on the instruction scheduling word, execution of each instruction in the next encryption and decryption operation is adjusted, time, energy and electromagnetic side channel leakage generated by the password dedicated processor is balanced, side channel-based information leakage is avoided, the sensitive information leakage risk in the information transmission process is reduced, and then the data transmission safety is improved.

The invention relates to a serial port instruction intelligent processing method and device based on multi-frame cache and a storage medium. The method comprises the steps that a system is initialized; starting serial port interruption to receive a serial port AT instruction; the received instruction is analyzed; after analysis is completed, the AT instructions are further classified; after instructions are classified and stored in corresponding queues, the system adopts a priority scheduling algorithm to determine which instruction is processed preferentially; and the system executes corresponding operation according to the specific content of the instruction. According to the method, a multi-level cache pool technology is adopted, a virtual cache queue is constructed on a software layer, the equivalent cache capacity is expanded, and the situation that a hardware buffer overflows or instructions are lost due to insufficient process processing capacity is avoided; a priority instruction scheduling algorithm is introduced, instruction grades are dynamically divided, key instructions are ensured to be processed preferentially, and the problem that a traditional single-frame mode cannot respond in time when the MCU is in a high load state is solved; and meanwhile, enhanced frame identification of the protocol is realized, and the problem of insufficient error correction capability of a traditional mode is solved.