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Method and apparatus for efficient scheduling for asymmetrical execution units

a technology of execution unit and execution unit, applied in the field of microprocessor architecture, can solve the problems of limited conventional architecture, instructions execution units that cannot support both types of instructions, so as to optimize dispatch throughput, maintain competitive latency, and more efficient scheduling

Active Publication Date: 2014-12-18
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a method and device that can execute different types of instructions, such as both A and E-types, and prioritize older instructions over newer ones to optimize execution. It also uses parallel circuitry to maintain competitive latency in performing scheduling procedures. The technical effect is improved efficiency in executing instructions and optimizing resource allocation.

Problems solved by technology

Conventional architectures that support two types of instructions, however, do not have execution units that can support both types of instructions.
Conventional architectures are limited because they do not successfully accomplish all the aforementioned objectives.
This allows execution to be conducted in parallel for better latency, but if there are not enough instruction blocks for the specific execution unit types, it will result in unused execution unit ports and less overall dispatch throughput.
Another problem with this scheme is that it is age optimized only within the individual category (A or E) and not optimized for overall age prioritization.
As a result, conventional architectures are limited and not designed to accomplish all the aforementioned desired objectives of the scheduler.

Method used

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  • Method and apparatus for efficient scheduling for asymmetrical execution units
  • Method and apparatus for efficient scheduling for asymmetrical execution units
  • Method and apparatus for efficient scheduling for asymmetrical execution units

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Embodiment Construction

[0023]Reference will now be made in detail to the various embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While described in conjunction with these embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.

NOTATIO...

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Abstract

A method for performing instruction scheduling in an out-of-order microprocessor pipeline is disclosed. The method comprises selecting a first set of instructions to dispatch from a scheduler to an execution module, wherein the execution module comprises two types of execution units. The first type of execution unit executes both a first and a second type of instruction and the second type of execution unit executes only the second type. Next, the method comprises selecting a second set of instructions to dispatch, which is a subset of the first set and comprises only instructions of the second type. Next, the method comprises determining a third set of instructions, which comprises instructions not selected as part of the second set. Finally, the method comprises dispatching the second set for execution using the second type of execution unit and dispatching the third set for execution using the first type of execution unit.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a conversion of and claims priority to and the benefit of Provisional Patent Application No. 61 / 799,062, entitled “METHOD AND APPARATUS FOR EFFICIENT SCHEDULING FOR ASYMMETRICAL EXECUTION UNITS,” having a filing Date of Mar. 15, 2013, which is herein incorporated by reference in its entirety.FIELD OF THE INVENTION[0002]Embodiments according to the present invention generally relate to microprocessor architecture and more particularly to the architecture for out-of-order microprocessors.BACKGROUND OF THE INVENTION[0003]In an Out-Of-Order (“OOO”) microprocessor, instructions are allowed to issue and execute out of their program order. The scheduler of an OOO microprocessor selects and dispatches ready instructions out of order into execution units. Certain microprocessor architectures have two types of instructions, A and E. Examples of A-type instruction are integer operations such as add and subtract while examples of ...

Claims

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Application Information

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IPC IPC(8): G06F9/48G06F9/38
CPCG06F9/3875G06F9/4881G06F9/3836G06F9/3856G06F9/3867
Inventor CHAN, NELSON N.
Owner INTEL CORP
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