22048 results about "Throughput" patented technology

The present invention relates to optical confinements, methods of preparing and methods of using them for analyzing molecules and / or monitoring chemical reactions. The apparatus and methods embodied in the present invention are particularly useful for high-throughput and low-cost single-molecular analysis.

Epitaxial layers are selectively formed in semiconductor windows by a cyclical process of repeated blanket deposition and selective etching. The blanket deposition phases leave non-epitaxial material over insulating regions, such as field oxide, and the selective etch phases preferentially remove non-epitaxial material while deposited epitaxial material builds up cycle-by-cycle. Quality of the epitaxial material improves relative to selective processes where no deposition occurs on insulators. Use of a germanium catalyst during the etch phases of the process aid etch rates and facilitate economical maintenance of isothermal and / or isobaric conditions throughout the cycles. Throughput and quality are improved by use of trisilane, formation of amorphous material over the insulating regions and minimizing the thickness ratio of amorphous:epitaxial material in each deposition phase.

This invention relates in part to soybean event pDAB8264.44.06.1 and includes a novel expression cassettes and transgenic inserts comprising multiple traits conferring resistance to glyphosate, aryloxyalkanoate, and glufosinate herbicides. This invention also relates in part to methods of controlling resistant weeds, plant breeding and herbicide tolerant plants. In some embodiments, the event sequence can be “stacked” with other traits, including, for example, other herbicide tolerance gene(s) and / or insect-inhibitory proteins. This invention further relates in part to endpoint TaqMan PCR assays for the detection of Event pDAB8264.44.06.1 in soybeans and related plant material. Some embodiments can perform high throughput zygosity analysis of plant material and other embodiments can be used to uniquely identify the zygosity of and breed soybean lines comprising the event of the subject invention. Kits and conditions useful in conducting these assays are also provided.

A wafer-processing apparatus includes: eight or ten reactors with identical capacity for processing wafers on the same plane, constituting four or five discrete units, each unit having two reactors arranged side by side with their fronts aligned in a line; a wafer-handling chamber including two wafer-handling robot arms each having at least two end-effectors; a load lock chamber; and a sequencer for performing, using the two wafer-handling robot arms, steps of unloading / loading processed / unprocessed wafers from / to any one of the units, and steps of unloading / loading processed / unprocessed wafers from / to all the other respective units in sequence while the wafers are in the one of the units.

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

A substrate processing apparatus is provided. The apparatus includes a plurality of fluid suppliers 61, 61, 63 for supplying different processing fluids. In processing a wafer W, the substrate processing apparatus moves the fluid suppliers 61, 62, 63 along the peripheral part of the wafer W relatively. The fluid suppliers 61, 62, 63 are arranged in a direction extending from the circumference of the wafer W to its inside. With the arrangement, the apparatus is capable of stable processing of the wafer W in spite of rotating the wafer W at a low speed. Further, it is possible to improve a throughput of the apparatus in resist processing.