40results about "Computation using non-denominational number representation" patented technology

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The invention relates to the field of integrated circuit design, and discloses a processor preamble and mantissa continuous bit parallel counting device and method. The device comprises a 32-bit bit sequence flipping module, a 32-bit bit negation module, eight 4-bit leading zero detection modules, four 8-bit leading zero processing modules, two 16-bit leading zero processing modules, a 32-bit leading zero processing module and a 32-bit result output module. According to the invention, parallel counting can be carried out on leading zeros, leading 1, mantissa zeros or mantissa 1 of various data with different precisions in a single processor clock period, so that the required time sequence path length is greatly shortened, the higher processor clock frequency is realized, the multiplexing of a hardware circuit is realized, and the cost is reduced. The circuit greatly reduces the use of transistor resources, reduces the area of a chip, reduces the cost and power consumption of the chip, improves the operation efficiency, universality and adaptability of the processor, and is suitable for being applied to application scenes such as a high-performance digital signal processor and a CPU (Central Processing Unit).

In methods and systems for estimating a gradient, a time-dependent unitary U and its derivative are computed with respect to a free parameter θi within a time interval for a pulse program for a quantum system, θi characterizing at least one of the pulse's shape, amplitude, phase, start time, and end time. The linear equation system ∂θ<sub2>i< / sub2>U=U*iΩ is solved for the effective generator Ω that is an element of the dynamical Lie algebra generated by the evolution under the time-dependent unitary U. Ω is decomposed into a sum of operators Pk, and the gradient of the circuit expectation value of the quantum system is computed with respect to θi for each operator Pk using a parameter-shift method. In a method for constructing a pulse program, a candidate pulse is added if its evolution generator commutes with all generators of all dynamical Lie algebras during the same time interval.

The invention provides a data processing method and device, electronic equipment, a storage medium and a program product, and the method comprises the steps: obtaining texture data corresponding to a target operation instruction under the condition that the target operation instruction is received; under the condition that the texture data is floating point type data, generating first operation data according to mantissa bit data of the texture data, and generating second operation data according to index bit data and sign bit data of the texture data; performing operation processing on the first operation data and the weight parameter by utilizing a normalization operation unit corresponding to the normalization data to obtain a first operation result, combining the second operation data and the first operation result to obtain to-be-adjusted operation data, and performing data format conversion on the to-be-adjusted operation data to obtain a second operation result; and determining a target operation result of the target operation instruction according to the second operation result. According to the embodiment of the invention, waste of computing resources can be avoided, and the occupancy rate of the circuit area is reduced.

A system and method which allows the basic checkpoint-reverse-mode AD strategy (of recursively decomposing the computation to reduce storage requirements of reverse-mode AD) to be applied to arbitrary programs: not just programs consisting of loops, but programs with arbitrarily complex control flow. The method comprises (a) transforming the program into a formalism that allows convenient manipulation by formal tools, and (b) introducing a set of operators to allow computations to be decomposed by running them for a given period of time then pausing them, while treating the paused program as a value subject to manipulation.

An artificial neural unit for signal processing is presented. The artificial neuron unit comprises: a fiber-based optical processing unit having first and second light input ports and first and second light output ports, and being configured and operable to controllably apply optical processing to incoherent input light signals and produce weighted first and second combined light signals; and an electro-optical processing unit configured and operable to process said weighted first and second combined light signals and produce a total weighted output of the artificial neuron unit, by successively performing the following: applying a predetermined mathematical function to said weighted first and second combined light signals corresponding to positive and negative weighting and producing a resulting signal; and applying a non-linear processing to the resulting signal to translate said resulting signal into an optical output signal representing said total weighted output of the artificial neuron unit.

The present invention provides a signal processing system for transmitting an analog signal from a probe to a remote processing unit. The system includes a first ASIC at the probe, the first ASIC being adapted to receive an analog probe signal. The first ASIC includes an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit stream. The system also includes a second ASIC at the remote processing unit, the second ASIC being adapted to receive the binary bit stream. The asynchronous may also include a time gain function circuit, the first ASIC may also include a multiplexer, and the second ASIC may also include a time to digital converter. The time to digital converter may be a pipelined time to digital converter.

A method for binary distance transform includes identifying a first binary vector and a second binary vector, the first binary vector and the second binary vector both having a binary dimension m, the binary dimension m indicating a number of bits. The method also includes determining a first distance between the first binary vector and the second binary vector, the first distance including a count of differing bits between the first binary vector and the second binary vector. The method also includes transforming the first distance to a second distance. The method also includes executing, by one or more processors, a machine-readable instruction in view of the second distance.

Introduced here is a technique to detect and / or correct errors in computation. The ability to correct errors in computation can increase the speed of the processor, reduce the power consumption of the processor, and reduce the distance between the transistors within the processor because the errors thus generated can be detected and corrected. In one embodiment, an error correcting module, running either in software or in hardware, can detect an error in matrix multiplication, by calculating an expected sum of all elements in the resulting matrix, and an actual sum of all elements in the resulting matrix. When there is a difference between the expected sum and the resulting sum, the error correcting module detects an error. In another embodiment, in addition to detecting the error, the error correcting module can determine the location and the magnitude of the error, thus correcting the erroneous computation.

A method of adaptive neural image compression with a hyperprior model by meta-learning is performed by at least one processor and includes generating a statistic feature, based on an input image and a hyperparameter, and generating a first shared feature and an estimated adaptive encoding parameter, encoding the input image to obtain a signal encoded image, based on the generated first shared feature and the generated estimated adaptive encoding parameter, generating a second shared feature and an estimated adaptive hyper encoding parameter, generating a hyper feature, based on the signal encoded image, the generated second shared feature, and the generated estimated adaptive hyper encoding parameter, and compressing the obtained signal encoded image, the generated statistic feature, and the generated hyper feature.

A method and device for adaptive neural image compression, and a computer device, the method comprising: generating statistical features based on an input image and hyperparameters; generating first shared features and estimated adaptive coding parameters; encoding the input image based on the generated first shared features and the generated estimated adaptive coding parameters to obtain a signal coded image; generating second shared features and estimated adaptive hyper-coding parameters; generating hyper-features based on the signal coded image, the generated second shared features and the generated estimated adaptive hyper-coding parameters; and compressing the obtained signal coded image, the generated statistical features and the generated hyper-features.

The invention relates to a transcendental function calculation device based on a lookup table and a self-reconfiguration self-evolution AI chip, and the device comprises a lookup table address generation module which is configured to receive configuration parameters and input data in a first fixed-point format, convert the input data into intermediate data in a second fixed-point format based on the configuration parameters, and send the intermediate data to the lookup table address generation module; processing the intermediate data into a lookup table address; wherein the data bit width of the second fixed-point format is smaller than the data bit width of the first fixed-point format; the lookup table module comprises a programmable memory; the programmable memory is used for storing a loadable lookup table data set, and the lookup table data set is a function value set after the transcendental function of the current configuration is quantized; the lookup table module is configured to respond to a lookup table address, read corresponding lookup table data from the programmable memory and output the lookup table data as a function value; by updating configuration parameters and lookup table data, the device can be reconfigured to calculate different transcendental functions, so that high precision, low delay, high flexibility and low hardware overhead can be considered at the same time.

The invention describes a computing unit for weighting networks, such as those used in artificial intelligence and for applications like the detection and synchronization of radio signals. By replacing large multiplier arrays with population counters and flexibly utilizing multiplication—both as a primary function for scaling population numbers and as a modified population counter itself—as well as through flexible masking operations, it is possible to drastically reduce the computational effort, and thus the die area and required electrical power, for calculating the output values ​​of artificial neural networks. The invention can be implemented as a special instruction or coprocessor in a conventional microcontroller, thereby enabling the use of artificial intelligence, particularly in lightweight and portable products, without requiring a connection to an external data center.

A logic cell for a programmable logic integrated circuit having K function inputs, where K is the maximum number of functions that the logic cell can compute for K inputs, and where the logic cell can be configured to implement one bit of a counter in parallel with K-1 any independent functions of the K inputs.

A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.

Embodiments of the present disclosure provide an artificial intelligence (AI)-driven system and methods for modeling the response / behavior of physical objects within a digital environment. In some implementations, digital models of physical objects are processed using a domain decomposition method (DDM) model configured to solve a boundary value problem by splitting the digital model into a plurality of subdomains. Each subdomain can then be individually solved (e.g., using a deep learning model) to predict horizontal and vertical displacements or the whole displacement field, which in turn can be used to predict boundary conditions for the respective subdomain. From the respective boundary conditions, a displacement field over the entire domain and / or a stress field can be predicted.

Disclosed is a method for generating an NPU command, comprising the steps of: generating a p-th partial network having the same structure as a structure of a first network defined by a first group of layers included in a predefined neural network; determining, in a first memory included in another computing device, a p-th read address, which is a location of an address where a p-th partial input activation, which is data to be inputted to an uppermost layer of the p-th partial network, is stored; determining, in the first memory, a p-th write address, which is a location of an address where a p-th partial output activation, which is data outputted by a lowest layer of the p-th partial network, should be stored; and generating an NPU command on the basis of the p-th read address and the p-th write address.

An artificial neural unit for signal processing is presented. The artificial neuron unit comprises: an optical fiber-based optical processing unit having a first optical input port and a second optical input port and a first optical output port and a second optical output port, the optical processor is arranged and operable to controllably apply optical processing to the incoherent input optical signal and produce weighted first and second combined optical signals; and an electro-optical processing unit, and an electro-optical processing unit configured and operable to process the weighted first combined optical signal and the second combined optical signal and to produce a total weighted output of the artificial neuron unit by continuously performing: applying a predetermined mathematical function to the weighted first combined optical signal and the second combined optical signal, to correspond to the positive weighting and the negative weighting and generate a result signal; and applying a non-linear process to the resultant signal to transform the resultant signal into an optical output signal representative of the total weighted output of the artificial neuronal unit.

This invention relates to the field of integrated circuit design and discloses a parallel counting device and method for consecutive leading and mantissa bits in a processor. The device includes a 32-bit bit order reversal module, a 32-bit bit inversion module, eight 4-bit leading zero detection modules, four 8-bit leading zero processing modules, two 16-bit leading zero processing modules, a 32-bit leading zero processing module, and a 32-bit result output module. This invention enables parallel counting of leading zeros, leading ones, mantissa zeros, or mantissa ones for various data with different precisions within a single processor clock cycle. This significantly shortens the required timing path length, allowing for higher processor clock frequencies. It also enables hardware circuit reuse, greatly reducing transistor resource usage, chip area, chip cost, and power consumption. This improves the processor's operational efficiency, versatility, and adaptability, making it suitable for applications in high-performance digital signal processors and CPUs.

A hardware processing device is provided comprising (i) multiple MAC units arranged to operate in a secure mode, performing at least one addition of a first value and a second value, wherein the first value is represented by a number of shares (proportions, representatives) and the second value is represented by the same number of shares; and at least one multiplication of the first value and the second value based on their shares and a random number; (ii) a multiplexer for switching between the secure mode and a normal mode, wherein the multiple MAC units are arranged to operate in normal mode on the first value and the second value instead of the shares of the first value and the shares of the second value.

A method for generating two large prime numbers by additive division without a trusted trader in a communication system with a number n participants, comprising the following steps: a. For each attempt, party P chooses i random numbers p i and q i : (pi, qi) = {(r × ϱ) − 1, ifi ≡ 1 r × ϱ, ifi ≡ 1 b. ϱ is the product of the first T prime numbers, where T is defined as: T = max { t ∈ ℕ , ρ ∈ ℙ | log 2 ( ∏ i = 1 t ρ ) ≤ k × γ} c. For each trial, each party chooses a new random rational number Y between 0 and 1 and selects r ∈ R [ 2 k − 1 − log 2 ϱ ,2 k − log 2 ϱ − 1 ] . d. To obtain a value N, all parties use an n-out-of-n additive secret-sharing scheme to determine p. i and q i as p i ,x = p i (x) and qi,x = q i (x) to share jointly, which allows them to calculate N without disclosing p or q: N = ∑ i = 1 n ( ∑ i = 1 npj , i × ∑ i = 1 nqj , i ) e. Each party performs a biprimality test to confirm that N is the product of two prime numbers, repeating the steps from step (a) in the event of a negative test result.

A system and method which allows the basic checkpoint-reverse-mode AD strategy (of recursively decomposing the computation to reduce storage requirements of reverse-mode AD) to be applied to arbitrary programs: not just programs consisting of loops, but programs with arbitrarily complex control flow. The method comprises (a) transforming the program into a formalism that allows convenient manipulation by formal tools, and (b) introducing a set of operators to allow computations to be decomposed by running them for a given period of time then pausing them, while treating the paused program as a value subject to manipulation.

An integrated circuit includes a plurality of current-mode computation (CMC) branches, each including a plurality of CMC cells and a branch summation line. An individual CMC cell includes at least one computation transistor that produces a CMC output current that is a function of a channel current of the computation transistor. A branch summation line receives CMC cell output currents produced by a plurality of CMC cells, and produces a branch output current that is a current-mode summation of all received CMC cell output currents. A layer-one current summation circuit receives the branch output current produced by at least one branch summation line, and produces a layer-one current summation circuit output current that is a function of the received branch output currents. The layer-one current summation circuit may be field-programmable. In operation, the integrated circuit can perform transistor tensor operations by programming one or more layer-one current summation circuits to combine all branch output currents received by those layer-one current summation circuits. Using embodiments of the present invention, millions, billions, trillions or more of the CMC cells can be field-programmed to execute computations in parallel to support transistor tensor operations.

A method of generating an NPU composite, the method comprising the steps of: generating a pth partial network having the same structure as a first network structure defined by a first set of layers included in a predefined neural network; determining, in a first memory included in another computing device, a p-th read address, which is a location where an address is stored as a p-th portion input activation value of data to be input to the most upstream layer of the p-th portion network; determining, in the first memory, a p-th write address, which is a position at which an address of a p-th portion output activation value, which is data output as a most downstream layer of the p-th portion network, should be stored; and generating an NPU instruction [p] based on the pth read address and the pth write address.

A processor including an instruction decoder configured to provide at least floating-point instruction control signals, a floating-point computational data path, a floating-point custom instruction control logic block coupled to the floating-point computational data path, a control and status register coupled to the floating-point computational data path, and the floating-point custom instruction control logic block, a first multiplexor configured to provide either floating-point instruction control signals or custom instruction control signals to the floating-point computational data path based on the state of a select control signal, and a second multiplexor configured to provide either floating-point operands or custom operands to the floating-point computational data path based on the state of the select control signal. The floating-point custom instruction control logic block asserts the select signal while directing the floating-point computational data path to assist it with the execution of a custom instruction. The custom instruction may be a floating-point exponential function.

An autonomous harvesting machine for orchard operating environments is described. The autonomous harvesting machine uses machine vision techniques to identify and triangulate features in the operating environment using a stream of monocular images. For instance, the harvesting machine identifies and localizes a shake point of a tree by projecting virtual rays from the pose of the identification system to the identified emergence point feature. To harvest the fruit of trees in the orchard, the harvesting machine shakes the tree at the identified shake point. Additionally, the harvesting machine autonomously navigates through the orchard using a combination high resolution spatial information based on localized features and low resolution spatial information from accessed satellite images.