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10362 results about "Byte" patented technology

The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable unit of memory in many computer architectures.

Multi-dimensional data protection and mirroring method for micro level data

The invention discloses a data validation, mirroring and error/erasure correction method for the dispersal and protection of one and two-dimensional data at the micro level for computer, communication and storage systems. Each of 256 possible 8-bit data bytes are mirrored with a unique 8-bit ECC byte. The ECC enables 8-bit burst and 4-bit random error detection plus 2-bit random error correction for each encoded data byte. With the data byte and ECC byte configured into a 4 bit×4 bit codeword array and dispersed in either row, column or both dimensions the method can perform dual 4-bit row and column erasure recovery. It is shown that for each codeword there are 12 possible combinations of row and column elements called couplets capable of mirroring the data byte. These byte level micro-mirrors outperform conventional mirroring in that each byte and its ECC mirror can self-detect and self-correct random errors and can recover all dual erasure combinations over four elements. Encoding at the byte quanta level maximizes application flexibility. Also disclosed are fast encode, decode and reconstruction methods via boolean logic, processor instructions and software table look-up with the intent to run at line and application speeds. The new error control method can augment ARQ algorithms and bring resiliency to system fabrics including routers and links previously limited to the recovery of transient errors. Image storage and storage over arrays of static devices can benefit from the two-dimensional capabilities. Applications with critical data integrity requirements can utilize the method for end-to-end protection and validation. An extra ECC byte per codeword extends both the resiliency and dimensionality.
Owner:HALFORD ROBERT

Multiple network protocol encoder/decoder and data processor

A multiple network protocol encoder/decoder comprising a network protocol layer, data handler, O.S. State machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine which decodes network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler which consists of data state machines that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML). Each data state machine reacts accordingly to the pertinent data, and any data that are required by more than one data state machine is provided to each state machine concurrently, and any data required more than once by a specific data state machine, are placed in a specific memory location with a pointer designating such data (thereby ensuring minimal memory usage). Resulting display data are immediately passed to a display controller. Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds header information and forwards the resulting network packet via a transport level mechanism.
Owner:NVIDIA CORP

Controller for Non-Volatile Memories and Methods of Operating the Memory Controller

A non-volatile memory system (3) is proposed consisting of a first non-volatile flash memory (5) having a plurality of blocks, each block having a plurality of pages, each block being erasable and each page being programmable, and a second non-volatile random access memory (23) having a plurality of randomly accessible bytes. The second non-volatile memory (23) stores data for mapping logical blocks to physical blocks and status information of logical blocks. Each logical block has an associated physical page pointer stored in the second non-volatile memory (23) that identifies the next free physical page of the mapped physical block to be written. The page pointer is incremented after every page write to the physical block, allowing all physical pages to be fully utilized for page writes. Furthermore, a method of writing and reading data is disclosed whereby the most recently written physical page associated with a logical address is identifiable by the memory system without programming flags into superseded pages, or recording time stamp values in any physical page or block of the first non-volatile memory (5). Furthermore, a method is provided for a logical block to be mapped to two physical blocks instead of one to provide additional space for page writes, resulting in reduction in page copy operations, thereby increasing the performance of the system.
Owner:CHANG CHEE KENG

Mechanisms for avoiding problems associated with network address protocol translation

Disclosed are methods and apparatus for avoiding problems caused by converting between two different protocols, such as IPv4 and IPv6. These problems may include, but are not limited to, fragmentation of packets, dropping of packets, and retransmission of packets. Avoiding these problems will reduce the incidence of transmission delays, bandwidth degradation, and additional processing in the packet's transmission path due to such problems. In general terms, the present invention provides mechanisms for modifying a protocol parameter, such as a TCP or UDP parameter, to avoid problems associated with protocol translation, such as fragmentation. In one implementation, the protocol parameter limits the size of a particular portion of the a packet transmitted by a sending computer node or device. For example, a packet size indicator is communicated to the sending computer node so that the sending computer node sends packets limited by the packet size indicator to thereby avoid associated with the size of such packets. In specific TCP embodiments, the size indicator specifies a window size and/or a maximum segment size. For example, if packets transmitted by a sending node to a receiving node are converted from IPv4 to IPv6 and the window size indicated to the sending node (e.g., by the receiving node) is 512 bytes, the window size is adjusted to 500 bytes before reaching the sending node. The adjustment amount may be based on an estimated size increase resulting from converting from IPv4 to IPv6. In this example, the window size is decreased by 12 bytes since a conversion from IPv4 to IPv6 where one 4 byte IPv4 address is changed to a 16 byte Ipv6 address has an associated size difference of 12 bytes. In a specific embodiment, actual changes in packet size may tracked and the adjusted size indicator may be dynamically based on such tracked changes. In other embodiments, the changes in packet size are predicted, and the adjusted size is preemptively changed as needed.
Owner:CISCO TECH INC
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