729 results about "Logical address" patented technology

The invention discloses a semiconductor device communication system and method based on an SECS / GEM protocol. The system comprises an SECS / GEM protocol processing module, a PLC communication module and a service logic processing module. The protocol processing module realizes message coding and decoding and state management through an HSMS / GEM layered architecture, and supports equipment capability dynamic negotiation; the PLC communication module adopts a factory mode to adapt to a multi-manufacturer controller to realize online mapping of a physical register and a logic address; and the business logic module dynamically loads the command processor based on a reflection mechanism, and realizes multi-condition event triggering through a rule engine. The method comprises the processes of system initialization, message priority scheduling, composite alarm processing and exception recovery, and the equipment integration efficiency and the communication reliability are remarkably improved. The method solves the problems of rigid parameter mapping, single event processing and poor equipment compatibility of a traditional scheme, and can be widely applied to equipment automation control of scenes such as semiconductor wafer manufacturing and packaging testing.

The invention belongs to the field of memory control, and provides a mapping table management method and a storage device.The method comprises the steps that a write-in instruction from a host system is received; judging an access mode of the write-in instruction according to an access feature of a logic address corresponding to the write-in instruction; if the access mode of the write-in instruction is judged to be a continuous access mode, updating a mapping relation from a logic address to a physical address corresponding to the write-in instruction to a main mapping table; and if it is judged that the access mode of the write-in instruction is a random access mode, recording and managing a mapping relation from a logic address to a physical address corresponding to the write-in instruction through a temporary mapping table arranged in a buffer memory, and delaying updating of a main mapping table. Therefore, the random write-in performance of the storage device is improved, and the service life is prolonged.

The invention relates to the technical field of storage control, in particular to a memory control method, which comprises the following steps: acquiring a target logic address in response to a reading request from a host system; determining a data access mode associated with the target logic address in real time based on the historical access information, wherein the data access mode at least comprises a continuous mode, a random mode and a hotspot mode; according to the determined data access mode, triggering a data prefetching strategy and a flash translation layer query strategy matched with the access mode; obtaining target data from a memory module based on a data prefetching strategy and a flash translation layer query strategy; and scheduling the cache resources and the input / output bandwidth according to a predetermined resource management strategy, and returning the target data to the host system. The prefetching accuracy and the cache utilization rate are improved.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention relates to the technical field of network operation and maintenance and communication monitoring, and discloses a machine room fault node identification method and system based on network topology, and the method comprises the steps: obtaining real-time network topology data and link transmission indexes, and constructing a weighted directed graph and an evolution sequence; performing time sequence projection on the historical data according to the sequence to obtain a node state vector; calculating a deviation value, and if the deviation value exceeds the limit, extracting deviation characteristics and searching to obtain a potential abnormal region; dominant indexes are obtained through clustering and grouping, propagation influences are evaluated, and a priority sequence is determined; an initial fault source is positioned, a congestion link is tracked, and a service influence range is mapped through a logic address; extracting link safety risk characteristics, calculating a correction coefficient, adjusting an abnormal threshold value, and evaluating a positioning difficulty level; and finally, similar cases are retrieved to generate a repair instruction, model parameters are fed back and adjusted, and optimized stable configuration is obtained. According to the method, accurate recognition and closed-loop optimization of machine room faults can be realized.

The invention discloses a fault recovery method of a storage pool, computer equipment, a storage medium and a product, and relates to the technical field of computers, and the method comprises the following steps: preferentially identifying and scanning a metadata area after the storage pool is offline, screening persistent effective metadata before offline, and storing the effective metadata in a database; metadata reconstruction is taken as a core to preferentially complete integration and restoration of a mapping relation between a logic address and a physical address instead of waiting for synchronous reconstruction of business data, so that the dilemma of long-time logic unavailability of a storage pool caused by synchronous processing of the metadata and the business data in a traditional restoration scheme is effectively broken through; according to the method, the target mapping relation table is quickly generated through conflict resolution and deletion completion processing, so that the interruption duration of the storage pool from offline to online can be remarkably shortened while the mapping accuracy is guaranteed, and the service access delay caused by unready metadata can be avoided.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

A host system can include a memory and a processing device, operatively coupled with the memory. The processing device is configured to perform operations including sending, to a memory device, data to be stored in the memory device, wherein the memory device comprises a plurality of dynamic capacity devices, wherein the plurality of dynamic capacity devices comprises a plurality of memory sections; receiving, from the memory device, a response including tag information, wherein the tag information comprises a set of tags in an order, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of the data; mapping the tags to logical addresses of the data; and accessing the data by aggregating, in the order of the set of tags, a plurality of device physical address (DPA) ranges, wherein each DPA range of the plurality of DPA ranges is associated with a respective tag of the tags.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention provides a key value cache scheduling method and device, a data processing method and device, a server and a medium. Relates to the technical field of data processing. The key value cache scheduling method is applied to a cache manager in a server for deploying a large model, and is used for uniformly scheduling cache resources when a heterogeneous accelerator executes large model reasoning. The method comprises the steps of obtaining a first request sent by a heterogeneous accelerator based on to-be-reasoned data, and determining the number of required cache blocks; selecting a plurality of target cache blocks from a preset memory cache region according to the cache block occupation state; and aggregating the logic addresses to generate a key value cache address and sending the key value cache address to the heterogeneous accelerator for accessing the key value data. According to the method, through a multi-level cache division and state awareness scheduling mechanism, the cache resource utilization rate and the cross-platform compatibility are effectively improved, the problems that an existing method is low in resource allocation efficiency and poor in compatibility are solved, and the large model reasoning efficiency and the system stability are remarkably improved.

The invention relates to the technical field of storage system IO performance optimization, and provides a redirection data aggregation method and equipment, and the method comprises the steps: recognizing random small IO data from a written IO request, aggregating and writing back-end storage objects, and constructing a storage mapping relation in an index table; traversing the rear-end storage object in which the random small IO data is stored, and distributing data from the same logic address space to point to the same target rear-end storage object through a hash algorithm; writing the data distributed to point to the same target back-end storage object into the continuous physical space of the target back-end storage object in sequence, and updating the mapping relation in the index table; the step S2 and the step S3 are repeated before a preset termination triggering condition is met, and a hash algorithm different from all previous times is adopted when the step S2 is repeatedly executed each time; when the data are read, the storage mapping relation is obtained from the index table, and the read requests corresponding to the data located in the same back-end storage object are aggregated and then read at a time.

According to one embodiment, a memory system includes a nonvolatile memory, and a memory controller including first and second caches and a first controller. The first cache includes a first memory unit and a first control unit. The second cache includes a second memory unit and a second control unit. The first memory unit includes a plurality of entries each having a cache tag including a first field and a cache line. Upon receiving a first prefetch request for first data of a first logical address, the first control unit stores the first data in the cache line of a first entry included in the first memory unit, and stores a first value in the first field of the first entry. The first control unit maintains the first entry until receiving a read request or a write request for the first logical address from the host.

The invention discloses a unified data access method and system for multi-protocol industrial equipment, and the method comprises the steps: constructing a unified equipment information model, and respectively establishing communication connection with at least two different types of industrial control protocol equipment through at least two different protocol adapters, receiving an original data message from the industrial equipment; starting a protocol adapter to parse the original data message so as to extract protocol specific data containing a device logic address, a data value and state information; mapping the protocol specific data to the unified equipment information model to generate a standard chemical control data object conforming to the specification of the unified equipment information model; and issuing the standard chemical control data object to an internal data communication bus so as to realize unified data supply for upper-layer application services. Therefore, an application developer can access and process all equipment data in a consistent and standard manner, the system integration complexity is greatly reduced, and the data fusion efficiency and stability are improved.

Systems, methods and apparatus of intelligent wear-leveling with reduced write-amplification for data storage devices configured on autonomous vehicles. For example, a data storage device of a vehicle includes: storage media components; a controller configured to store data into and retrieve data from the storage media components according to commands received in the data storage device; an address map configured to map between: logical addresses specified in the commands received in the data storage device, and physical addresses of memory cells in the storage media components; and an artificial neural network configured to receive, as input and as a function of time, operating parameters indicative a data access pattern, and generate, based on the input, a prediction to determine an optimized operation for wear leveling among memory cells in the data storage device. The controller is configured to perform the optimized operation for wear leveling based on the prediction.

The invention discloses an address allocation method and electronic equipment, and relates to the technical field of address allocation, and the method comprises the steps: analyzing an electrical connection netlist, determining a plurality of link entities in a target link, constructing a link topology tree, and generating an address allocation rule set; determining logical addresses of a plurality of link entities; determining actual configuration addresses of a plurality of link entities; performing address conflict verification on the plurality of link entities based on the actually configured addresses and the logic addresses, and judging the link entities as address conflict entities if the link entities do not pass the address conflict verification; a set of modifiable variables and a set of minimum cost modification solutions are determined based on address information for the address conflicting entities. According to the method, the address can be automatically planned and allocated based on the electrical connection netlist, and conflict repair after address conflict verification is realized, so that the problems of insufficient utilization of address space, difficulty in timely discovery of path conflicts, low conflict positioning and repair efficiency and the like in related technologies are solved.

Requests for a write storage operation are stored in a ring buffer. The next available request is retrieved from the ring buffer. When the next available request comprises a write operation that overlaps in a logical address range with a previous request stored in the ring buffer, the next available request is suspended. The next available request and the previous request are merged to generate a single request that includes logical address ranges of the next available request and the previous request.

The invention discloses a multi-device network access method which comprises the following steps: time-sharing enabling: a master station controls the network distribution process of a slave station by pulling down a GPIO (General Purpose Input / Output) pin; directional broadcasting: the master station sends configuration information to the slave station through the broadcast address; dynamic response is carried out, after the slave station receives the configuration information, distribution network information is fed back to the master station, and binding of the hardware identification and the logic address is carried out; and closed-loop confirmation: the master station sends a confirmation response message to the slave station, and the network distribution process of the slave station is ended by pulling up the GPIO pin. The invention also discloses a multi-device network access system. According to the method and the device, the technical problems that the upper-level equipment needs to manually allocate the sub-equipment address or the equipment position cannot be accurately positioned in the hierarchical topology by adopting broadcast type automatic allocation, and the traditional polling mechanism needs to wait for response step by step in the traditional scheme are solved.

The invention discloses a mapping table reconstruction method and storage equipment. The method comprises the following steps: determining a final check point in a storage medium; determining a target mapping table needing data recovery based on the final check point; sequentially reading metadata of each data block in the storage medium according to the last check point, wherein the metadata comprises a logic address of currently written data and a historical physical address corresponding to the logic address when the logic address is written last time; determining a target block matched with the target mapping table in the data block according to the logic address; constructing a data writing linked list of the logic address according to the historical physical address of the target block; and reconstructing the target mapping table according to the data write-in linked list. According to the invention, the reconstruction efficiency of the mapping table can be improved while accurate reconstruction of the mapping table is ensured.

The invention discloses an NVMe storage array virtualization device based on an FPGA (Field Programmable Gate Array), which is characterized in that single I / O (Input / Output) virtualization (SR-IOV) is realized in the FPGA, and a plurality of NVMe virtual functions which can be directly accessed by a virtual machine are externally provided; mapping from a virtual volume logic address to a physical storage address is completed in hardware, striping management and RAID verification calculation are carried out on a plurality of NVMe solid state disks at the rear end, and storage resource pooling is achieved; the partial reconfigurable characteristic of the FPGA is utilized, I / O scheduling, data compression and prefetching strategies are dynamically adjusted, and the adaptability and performance efficiency of the system are improved. Hardware unloading of the whole I / O path is completed in the FPGA, intervention of a host CPU is not needed, delay is remarkably reduced, the throughput capacity is improved, service quality isolation and elastic expansion in a multi-tenant environment are supported, and an effective technical path is provided for constructing a next-generation high-performance and low-delay storage infrastructure.

The embodiment of the invention provides a data management method and device, electronic equipment and a storage medium. The method comprises the following steps: receiving a data access request for target data; the data access request carries a to-be-accessed logic address corresponding to target data; determining a target logic address section to which the to-be-accessed logic address belongs; determining a target physical space block corresponding to the target logic address section in a preset mapping relation; executing an access operation of the target data in the target physical space block according to the to-be-accessed logic address; the preset mapping relationship comprises a one-to-one correspondence relationship between each logical address section and each physical space block of the memory module. Visibly, in the technical scheme, the data volume in the preset mapping relationship can be greatly reduced, so that the storage space occupied by storing the mapping relationship is reduced, the memory space overhead is saved, the query speed can be improved, and the data access delay caused by searching the mapping relationship is reduced.

The invention discloses a memory card false capacity expansion detection method and system, and relates to the field of memory card detection, and the method comprises the steps: obtaining the nominal capacity information of a to-be-detected memory card, and dividing a logic address into a plurality of test address blocks based on the capacity; respectively executing distributed small data write-in operation in each test address block, and recording write-in delay; reading the data and comparing consistency results, generating a delay behavior curve taking the logic address as a horizontal axis and the write-in delay as a longitudinal axis, and marking a read-back consistency state on the curve; and identifying a local fluctuation abnormal region in the curve, and if the region is overlapped with the read-back consistency failure region, preferentially judging the intersection as a pseudo capacity expansion region. According to the invention, the problem of capacity false bidding of the memory card can be effectively solved without writing in the whole disk.

The invention discloses a task processing method, device and system and related equipment, and relates to the technical field of storage. The task processing device receives a data migration task used for migrating target data indicated by the source logic address to a target logic address, wherein the data migration task comprises the source logic address and the target logic address; converting the source logic address into a first physical address, converting the destination logic address into a second physical address, and generating a migration request carrying the first physical address and the second physical address; and sending a migration request to the first storage device to indicate the first storage device to migrate the target data from the first physical address to the second physical address. Therefore, the storage device executes the process of transmitting and processing the data among different storage devices, so that the number of IO stacks and network stacks needing to be executed can be effectively reduced, and the task execution efficiency is improved. And moreover, the CPU does not need to intervene, so that the CPU can improve the performance of the storage system based on more computing power.

A data access method, apparatus and device, in the application, a physical space of a storage device is mapped into a logic space, the logic space comprises a plurality of logic blocks, and the physical space comprises a plurality of physical blocks. The storage device obtains a data reading instruction, wherein the data reading instruction is used for requesting to read the first data; the storage device determines a target index entry according to the logical address of the first data, the target index entry indicates a mapping relationship between a first logical block and a first physical block, and the first logical block is a logical block to which the logical address belongs. The storage device determines the physical address of the compressed first data according to the first physical block and a first target data volume, wherein the first target data volume is the data volume of the compressed first data; the storage device obtains the compressed first data according to the physical address; and decompressing the compressed first data, and obtaining and feeding back the first data. The construction granularity of the index entry is a physical block and a logic block, and the data volume of the compressed data does not need to be recorded, so that the complexity of data indexing is effectively reduced.

The invention discloses a data migration system and method, electronic equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that under the condition that a target data disk meets a data migration session establishment request sent by the source data disk, a corresponding target namespace of to-be-migrated data of the source data disk is established, the information of successful establishment of the data migration session is sent to the corresponding source data disk; the source data disk writes to-be-migrated data into a target namespace of a corresponding target data disk according to a corresponding source logic address of the to-be-migrated data in the source data disk based on the data migration session, and the storage cluster management module stores the to-be-migrated data in the target namespace of the corresponding target data disk under the condition that the data migration task is completed. And recording a corresponding relationship between the source logic address of the to-be-migrated data and the target namespace of the target data disk corresponding to the to-be-migrated data in a system layer. The technical problem that the performance of the storage system is reduced due to the fact that data migration needs to modify a large amount of metadata in the related technology is solved, and the technical effect of improving the performance of the storage system is achieved.

The invention discloses a mapping segment management method and device, electronic equipment and a storage medium, and relates to the technical field of storage. The method comprises the following steps: acquiring the total access times of a plurality of mapping segments included in a mapping table corresponding to the solid state disk in a current period, the first access times of a first mapping segment, and a first mapping temperature corresponding to the first mapping segment in a previous period; determining a second mapping temperature of the first mapping section in the current period according to the first mapping temperature, the first access times and the total access times; according to the second mapping temperature, the preset mapping temperature and the cache region where the first mapping section is located currently, whether cache region migration operation is conducted on the first mapping section or not is determined, and the cache region migration operation comprises migration from the hot cache region to the cold cache region or migration from the cold cache region to the hot cache region. According to the embodiment of the invention, the problems of long time consumption and high delay of random writing and poor writing performance of the solid state disk caused by large capacity of a mapping table from a logic address to a physical address are solved.

A data reading / writing method includes a processor that sends a read / write request to the storage. The read / write request is used to request to perform data reading / writing in the storage, and the read / write request carries a logical address of data. After receiving the read / write request, the storage maps the logical address to target positions in banks of N storage chips in the storage, and performs data reading / writing at the target positions in the banks of the N storage chips. The target positions in the banks of the N storage chips are distributed in different areas.

The invention provides a memory erasing management method and device, electronic equipment and a storage medium. Determining a target storage page for storing the to-be-processed data according to the erasing management information in the management area of each storage page; determining a first logical address corresponding to a first physical address of the target storage page and a second physical address corresponding to a second logical address of the to-be-processed data according to page address mapping information in the erasing management information; switching the mapping of the first logic address to the second physical address, switching the mapping of the second logic address to the first physical address, and updating the read erasing management information; and writing the to-be-processed data into a content area of the target storage page based on a mapping relationship between the second logic address and the first physical address. According to the method, the appropriate target storage page is selected for the to-be-processed data to be stored, so that all the storage pages are subjected to balanced loss together, and the purpose of aging together is achieved.

Example systems and methods for data migration in memory systems are disclosed. One example method includes receiving, by a memory controller of a memory system, a command comprising a first logical address and a second logical address. In response to the command, a correspondence of data to the second logical address is established based on a correspondence of the data to the first logical address. The first logical address is deallocated based on the command.