437 results about "Logical address" patented technology

The invention belongs to the field of memory control, and provides a mapping table management method and a storage device.The method comprises the steps that a write-in instruction from a host system is received; judging an access mode of the write-in instruction according to an access feature of a logic address corresponding to the write-in instruction; if the access mode of the write-in instruction is judged to be a continuous access mode, updating a mapping relation from a logic address to a physical address corresponding to the write-in instruction to a main mapping table; and if it is judged that the access mode of the write-in instruction is a random access mode, recording and managing a mapping relation from a logic address to a physical address corresponding to the write-in instruction through a temporary mapping table arranged in a buffer memory, and delaying updating of a main mapping table. Therefore, the random write-in performance of the storage device is improved, and the service life is prolonged.

The invention relates to the technical field of storage control, in particular to a memory control method, which comprises the following steps: acquiring a target logic address in response to a reading request from a host system; determining a data access mode associated with the target logic address in real time based on the historical access information, wherein the data access mode at least comprises a continuous mode, a random mode and a hotspot mode; according to the determined data access mode, triggering a data prefetching strategy and a flash translation layer query strategy matched with the access mode; obtaining target data from a memory module based on a data prefetching strategy and a flash translation layer query strategy; and scheduling the cache resources and the input / output bandwidth according to a predetermined resource management strategy, and returning the target data to the host system. The prefetching accuracy and the cache utilization rate are improved.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

The invention relates to the technical field of network operation and maintenance and communication monitoring, and discloses a machine room fault node identification method and system based on network topology, and the method comprises the steps: obtaining real-time network topology data and link transmission indexes, and constructing a weighted directed graph and an evolution sequence; performing time sequence projection on the historical data according to the sequence to obtain a node state vector; calculating a deviation value, and if the deviation value exceeds the limit, extracting deviation characteristics and searching to obtain a potential abnormal region; dominant indexes are obtained through clustering and grouping, propagation influences are evaluated, and a priority sequence is determined; an initial fault source is positioned, a congestion link is tracked, and a service influence range is mapped through a logic address; extracting link safety risk characteristics, calculating a correction coefficient, adjusting an abnormal threshold value, and evaluating a positioning difficulty level; and finally, similar cases are retrieved to generate a repair instruction, model parameters are fed back and adjusted, and optimized stable configuration is obtained. According to the method, accurate recognition and closed-loop optimization of machine room faults can be realized.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention discloses a unified data access method and system for multi-protocol industrial equipment, and the method comprises the steps: constructing a unified equipment information model, and respectively establishing communication connection with at least two different types of industrial control protocol equipment through at least two different protocol adapters, receiving an original data message from the industrial equipment; starting a protocol adapter to parse the original data message so as to extract protocol specific data containing a device logic address, a data value and state information; mapping the protocol specific data to the unified equipment information model to generate a standard chemical control data object conforming to the specification of the unified equipment information model; and issuing the standard chemical control data object to an internal data communication bus so as to realize unified data supply for upper-layer application services. Therefore, an application developer can access and process all equipment data in a consistent and standard manner, the system integration complexity is greatly reduced, and the data fusion efficiency and stability are improved.

The invention discloses an address allocation method and electronic equipment, and relates to the technical field of address allocation, and the method comprises the steps: analyzing an electrical connection netlist, determining a plurality of link entities in a target link, constructing a link topology tree, and generating an address allocation rule set; determining logical addresses of a plurality of link entities; determining actual configuration addresses of a plurality of link entities; performing address conflict verification on the plurality of link entities based on the actually configured addresses and the logic addresses, and judging the link entities as address conflict entities if the link entities do not pass the address conflict verification; a set of modifiable variables and a set of minimum cost modification solutions are determined based on address information for the address conflicting entities. According to the method, the address can be automatically planned and allocated based on the electrical connection netlist, and conflict repair after address conflict verification is realized, so that the problems of insufficient utilization of address space, difficulty in timely discovery of path conflicts, low conflict positioning and repair efficiency and the like in related technologies are solved.

The invention discloses an NVMe storage array virtualization device based on an FPGA (Field Programmable Gate Array), which is characterized in that single I / O (Input / Output) virtualization (SR-IOV) is realized in the FPGA, and a plurality of NVMe virtual functions which can be directly accessed by a virtual machine are externally provided; mapping from a virtual volume logic address to a physical storage address is completed in hardware, striping management and RAID verification calculation are carried out on a plurality of NVMe solid state disks at the rear end, and storage resource pooling is achieved; the partial reconfigurable characteristic of the FPGA is utilized, I / O scheduling, data compression and prefetching strategies are dynamically adjusted, and the adaptability and performance efficiency of the system are improved. Hardware unloading of the whole I / O path is completed in the FPGA, intervention of a host CPU is not needed, delay is remarkably reduced, the throughput capacity is improved, service quality isolation and elastic expansion in a multi-tenant environment are supported, and an effective technical path is provided for constructing a next-generation high-performance and low-delay storage infrastructure.

The embodiment of the invention provides a data management method and device, electronic equipment and a storage medium. The method comprises the following steps: receiving a data access request for target data; the data access request carries a to-be-accessed logic address corresponding to target data; determining a target logic address section to which the to-be-accessed logic address belongs; determining a target physical space block corresponding to the target logic address section in a preset mapping relation; executing an access operation of the target data in the target physical space block according to the to-be-accessed logic address; the preset mapping relationship comprises a one-to-one correspondence relationship between each logical address section and each physical space block of the memory module. Visibly, in the technical scheme, the data volume in the preset mapping relationship can be greatly reduced, so that the storage space occupied by storing the mapping relationship is reduced, the memory space overhead is saved, the query speed can be improved, and the data access delay caused by searching the mapping relationship is reduced.

A data access method, apparatus and device, in the application, a physical space of a storage device is mapped into a logic space, the logic space comprises a plurality of logic blocks, and the physical space comprises a plurality of physical blocks. The storage device obtains a data reading instruction, wherein the data reading instruction is used for requesting to read the first data; the storage device determines a target index entry according to the logical address of the first data, the target index entry indicates a mapping relationship between a first logical block and a first physical block, and the first logical block is a logical block to which the logical address belongs. The storage device determines the physical address of the compressed first data according to the first physical block and a first target data volume, wherein the first target data volume is the data volume of the compressed first data; the storage device obtains the compressed first data according to the physical address; and decompressing the compressed first data, and obtaining and feeding back the first data. The construction granularity of the index entry is a physical block and a logic block, and the data volume of the compressed data does not need to be recorded, so that the complexity of data indexing is effectively reduced.

A data reading / writing method includes a processor that sends a read / write request to the storage. The read / write request is used to request to perform data reading / writing in the storage, and the read / write request carries a logical address of data. After receiving the read / write request, the storage maps the logical address to target positions in banks of N storage chips in the storage, and performs data reading / writing at the target positions in the banks of the N storage chips. The target positions in the banks of the N storage chips are distributed in different areas.

The invention provides a memory erasing management method and device, electronic equipment and a storage medium. Determining a target storage page for storing the to-be-processed data according to the erasing management information in the management area of each storage page; determining a first logical address corresponding to a first physical address of the target storage page and a second physical address corresponding to a second logical address of the to-be-processed data according to page address mapping information in the erasing management information; switching the mapping of the first logic address to the second physical address, switching the mapping of the second logic address to the first physical address, and updating the read erasing management information; and writing the to-be-processed data into a content area of the target storage page based on a mapping relationship between the second logic address and the first physical address. According to the method, the appropriate target storage page is selected for the to-be-processed data to be stored, so that all the storage pages are subjected to balanced loss together, and the purpose of aging together is achieved.

The invention relates to the technical field of storage control, in particular to a memory control method, a storage device, a medium and computer equipment, a three-level index structure is arranged, only a first-level root table resides in a cache, an index is rapidly extracted through bit operation so as to reduce cache occupation and invalid IO overhead, the search range is narrowed through a hash bucket of a three-level page table, and the search efficiency is improved. Conflicts are solved through a linked list, and the mapping efficiency and the system stability can be improved through a fixed structure; and the second-level block table and the third-level page table are loaded in a non-blocking manner without occupying a CPU, so that the bandwidth is saved, and the concurrency performance and the cache hit rate are improved. Through the overall scheme of three-level index, chained hash table, loading on demand and bit operation, the delay of the whole process from logic address input to physical address output is remarkably reduced, and the low delay requirement of a high-performance storage system is met; the three-level index structure supports flexible adjustment of the sizes of a root table, a block table and a page table, adapts to storage devices with different capacities, and has good expandability.

The embodiment of the invention relates to a data processing method and device, computer equipment and a storage medium, and the method comprises the steps: carrying out the coding operation of an erasure code on first data under the condition of receiving a write-in request for the first data, and obtaining a plurality of logic units and a plurality of fragments; according to the first identifier of the logic unit and the second identifier of each fragment, writing the plurality of fragments into a storage node; and under the condition that a reading request is received, obtaining a target first identifier and a target second identifier of the second data, reading the plurality of target fragments of the second data from the plurality of storage nodes, and carrying out merging processing to obtain the second data. Therefore, the data can be divided into the fragments with the unique identifiers for storage in the writing stage, and the target fragments can be quickly positioned according to the logic addresses and the recovered data can be merged in the reading stage, so that the metadata query overhead is reduced, the reading and writing efficiency is improved, and the storage and network transmission cost is reduced; and the overall performance of the distributed storage system in a high-concurrency scene is improved.

Provided herein may be a computing system for storing data and a method of operating the same. The computing system may include a host device configured to output a write operation request for a plurality of pieces of data corresponding to a plurality of consecutive logical addresses, and a storage device including a plurality of memory areas to be operated according to an interleaving scheme, the storage device configured to, when the write operation request is received from the host device, determine a write order of the plurality of pieces of data so that the pieces of data are read from the plurality of memory areas according to a sequential order of the plurality of logical addresses during a read operation, and provide, to the host device, data transmission requests corresponding to each of the plurality of pieces of data based on the determined write order.

The invention discloses a task processing method, device and system and related equipment, and relates to the technical field of storage. The task processing device receives a data migration task used for migrating target data indicated by the source logic address to a target logic address, wherein the data migration task comprises the source logic address and the target logic address; converting the source logic address into a first physical address, converting the destination logic address into a second physical address, and generating a migration request carrying the first physical address and the second physical address; and sending a migration request to the first storage device to indicate the first storage device to migrate the target data from the first physical address to the second physical address. Therefore, the storage device executes the process of transmitting and processing the data among different storage devices, so that the number of IO stacks and network stacks needing to be executed can be effectively reduced, and the task execution efficiency is improved. And moreover, the CPU does not need to intervene, so that the CPU can improve the performance of the storage system based on more computing power.

The invention discloses a data protection method, a memory, electronic equipment and a storage medium, and relates to the field of storage, the method is applied to the memory, and a logical address-to-physical address mapping table is configured and comprises a first mapping area and a second mapping area; wherein the first mapping area is used for recording an original mapping relation between a logic address and a physical address corresponding to read-write operation performed on the snapshot area before the snapshot protection mode is started; the second mapping area is used for recording a mapping relation between a logic address and a physical address corresponding to incremental read-write operation executed on the snapshot area after the snapshot protection mode is started; after a snapshot starting instruction is received, entering a snapshot protection mode, and determining a snapshot area needing to be protected according to preset configuration information; and locking an original mapping relation of the snapshot area in the first mapping area, and redirecting a data operation request initiated for the snapshot area to the second mapping area to execute incremental read-write operation.

A task processing method comprising obtaining a first identifier (ID) sequence from a logical unit number (LUN) mapping table based on logical addresses of first data, where IDs in the first ID sequence are allocated based on a sequence of physical addresses, where the LUN mapping table includes mapping relationships between the logical addresses and the IDs; obtaining first physical addresses from an ID mapping table based on one ID in the first ID sequence when the IDs in the first ID sequence are consecutive, where the ID mapping table includes a mapping relationship between an ID and a physical address and the first physical addresses are a plurality of physical addresses corresponding to the first ID sequence; and reading the first data based on the first physical addresses.

The invention relates to a hard disk control system and method. The hard disk control method is executed by a complex programmable logic device, and comprises the following steps: detecting a first voltage of a first data line connected with a first node and a second voltage of a second data line connected with a second node under the triggering of a management instruction, and judging at least one of the first node and the second node as a target node according to the first voltage and the second voltage, reading a pre-stored mapping table corresponding to the target node, judging a target hard disk address according to the pre-stored mapping table and the target logic address, and controlling a hard disk corresponding to the target hard disk address according to the target operation.

The application discloses a soft and hard bidirectional semantic addressing jump method, belongs to the technical field of artificial intelligence data addressing and end-side storage, and is applied to the scene of artificial intelligence end-side equipment and edge computing equipment. According to the application, the semantic unit division is completed according to the minimum semantic granularity for the data to be processed, the unique mapping binding relationship between the software end logical address and the hardware end physical address is established based on the semantic unit, the one-way or bidirectional corresponding switching of the two types of addresses is realized through jump or table lookup operation, and the address one-to-one mapping alignment is kept through the semantic unit in the whole switching process and after the switching is completed. The application can cover the bidirectional addressing scene, solves the problems of asynchronous addressing, data disorder, power-off loss of mapping and high power consumption in the prior art, and improves the addressing stability of equipment.

The present invention relates to a method for recommending an optimal applied voltage for data extraction of a NAND flash memory. The method for recommending an optimal applied voltage for data extraction of a NAND flash memory according to one aspect of the present invention comprises: an initial data extraction step of applying a preset initial applied voltage to an input pin of a NAND flash memory, extracting data included in the NAND flash memory, and storing a logical address of the data; a per-voltage data extraction step of applying a plurality of voltages, obtained by repeatedly increasing or decreasing the initial applied voltage by a predetermined voltage, to the input pin of the NAND flash memory, each at different time points, and extracting, for each voltage, data having the same logical address as the logical address of the data extracted in the initial data extraction step; and a step of recommending an optimal applied voltage on the basis of binary data generated by performing an XOR operation between data having the same logical address extracted according to different applied voltages.

Example systems and methods for data migration in a storage system are disclosed. One example method includes receiving, by a memory controller of a storage system, a command including a first logical address and a second logical address. In response to the command, a relative relationship between the data and the second logical address is established based on a correspondence between the data and the first logical address. The first logical address is reassigned based on the command.

A data storage apparatus may include a storage device; a buffer memory device configured to temporarily store write data and a mapping table; and a memory controller configured to control the storage device to program the write data. The memory controller is configured to when externally receiving write commands including a logical addresses, store the logical addresses by mapping the logical addresses to physical addresses sequentially stored in the mapping table in a sequence in which the write commands are received, and when a program operation corresponding to a first write command fails, invalidate first mapping information corresponding to the first write command and update the first mapping information by allocating a new physical address to a logical addresses including the first write command in response to a reprogram command generated with respect to the first write command.

Methods, systems, and devices supporting techniques for pre-fetching information using pattern detection are described. Some memory systems may support pre-fetching information, such as logical-to-physical (L2P) mapping tables, data, or both, if a sequential pattern of read commands is detected. In some examples, the memory system may store a list of logical addresses indicated by received read commands and may determine whether the list corresponds to a sequential pattern independent of intervening write-alike commands. The list may store previous logical addresses for read commands, allowing the memory system to determine whether subsequent read commands form a sequential pattern. Additionally or alternatively, the memory system may track a ratio of hibernate commands to other commands (e.g., sequential read commands) and may refrain from pre-fetching L2P mapping tables for a detected sequence if the tracked ratio satisfies (e.g., exceeds) a threshold ratio.

A device includes a processing system configured to receive, via an inter-integrated circuit (I2C) bus, one or more scan acknowledgement messages respectively associated with one or more secondary devices and to send, via the I2C bus, one or more address assignment messages to the one or more secondary devices. The one or more address assignment messages respectively include one or more logical addresses that are associated with the one or more secondary devices. The processing system is further configured to communicate, via the I2C bus, a data message with at least one secondary device of the one or more secondary devices. The data message includes an address field including a logical address indicating that the data message is associated with the at least one secondary device. A length of the address field is based on a quantity of the one or more scan acknowledgement messages.

A storage system includes a storage device and a host device. The storage device includes a non-volatile memory device configured to store data and a storage controller configured to control the non-volatile memory device to isolate and store the data by grouping storage spaces of the non-volatile memory device into a plurality of isolated storage spaces. The host device includes a file system configured to generate and manage a plurality of file allocation instances corresponding to a plurality of file allocation system calls from an application program by allocating, with respect to each of the plurality of file allocation system calls, a logical address range and an isolated identifier of a plurality of isolated identifiers corresponding to the plurality of isolated storage spaces.

A memory device is provided. The memory device includes: a buffer memory; and a memory controller configured to: obtain map data and meta data for recovering the map data from at least one external storage device; store the map data and the meta data obtained from the at least one external storage device in the buffer memory, the buffer memory being allocated for the at least one external storage device; translate a logical address corresponding to the at least one external storage device into a physical address of the buffer memory; and send the map data and the meta data to the at least one external storage device in response to detecting a sudden power-off event.

An input / output (I / O) erase request directed at memory devices is received by a processing device. The erase request includes logical block address that is associated with a data object. The memory devices include groups of zones corresponding to sequential logical addresses. The plurality of zones are associated with a compound data object that includes a plurality of data objects, including the data object. One or more zones associated with the data object are identified. A data set counter associated with each of the one or more zones is decremented. The data set counter represents a number of sets of data associated with the zone. Responsive to determining that the data set counter associated with one of the one or more ones satisfies a criterion, the one of the one or more zones is a caused to be erased.

A system can include a memory component and a processing device. The processing device can receive an indication to remove a group of memory cells of a memory sub-system from a logical address space that is used to access the memory sub-system. The processing device can, responsive to receiving the indication, remove the group of memory cells of the memory sub-system from the logical address space. The processing device can program the group of memory cells that have been removed from the logical address space with a voltage state.