1190 results about "Logical address" patented technology

This disclosure provides techniques for managing writes of data useful for storage systems that do not permit overwrite of a logical address. One implementation provides a nonvolatile memory storage drive, such as a flash memory drive, that provides support for zoned drive and / or Open Channel-compliant architectures. Circuitry on the storage drive tracks storage location release metadata for addressable memory space, optionally providing to a host system information upon which maintenance decisions or related scheduling can be based. The storage drive can also provide buffering support for accommodating receipt of out-of-order writes and unentanglement and performance of out of order writes, with buffering resources being configurable according to any one of a number of parameters. The disclosed storage drive facilitates reduced error rates and lower request traffic in a manner consistent with newer memory standards that mandate that writes to logical addresses be sequential.

The invention relates to the technical field of microprocessors, and discloses a safety debugging method of an embedded microprocessor and the embedded microprocessor, the method comprises the following steps: implanting a random module in the microprocessor, constructing a resistance network array through random distribution of silicon substrate lattice defects to generate a disordered sequence, and if microprocessor data access is carried out, starting the random module; if physical intrusion is detected, a debugging session is established, three types of physical characteristics are synchronously generated to construct a composite key, a triple dynamic confusion layer is constructed in the microprocessor, the dynamic confusion layer and the composite key construct physical logic linkage protection, a probe access instruction logic address is called, if physical intrusion is detected, a probe triggers an invisible check point, and the probe accesses the invisible check point. The integrity of an execution environment is verified, if abnormal debugging is detected, a hardware defense mechanism is triggered, an access attack model is established, confusion parameters are trained and optimized, and a module interconnection mode is changed, so that the learning cycle of an attacker is broken, and the risk of attacking a processor in a machine learning mode is reduced.

The invention discloses a semiconductor device communication system and method based on an SECS / GEM protocol. The system comprises an SECS / GEM protocol processing module, a PLC communication module and a service logic processing module. The protocol processing module realizes message coding and decoding and state management through an HSMS / GEM layered architecture, and supports equipment capability dynamic negotiation; the PLC communication module adopts a factory mode to adapt to a multi-manufacturer controller to realize online mapping of a physical register and a logic address; and the business logic module dynamically loads the command processor based on a reflection mechanism, and realizes multi-condition event triggering through a rule engine. The method comprises the processes of system initialization, message priority scheduling, composite alarm processing and exception recovery, and the equipment integration efficiency and the communication reliability are remarkably improved. The method solves the problems of rigid parameter mapping, single event processing and poor equipment compatibility of a traditional scheme, and can be widely applied to equipment automation control of scenes such as semiconductor wafer manufacturing and packaging testing.

The embodiment of the invention provides a data writing method and device of a storage system, a computer readable storage medium and electronic equipment. The method comprises the steps of obtaining historical data writing conditions of a plurality of logic address sections of the storage system; according to historical data writing conditions of the plurality of logical address sections, respectively determining writing heat of the plurality of logical address sections; and performing popularity grading on the to-be-written data according to the write popularity of the plurality of logic address sections to determine the popularity level of each to-be-written data. And writing the to-be-written data with the same heat level into the same physical address section of the storage system. According to the method, the to-be-written data with the same heat level is written into the same physical address section, classified writing of the data according to the heat level is realized, the heat of the data in the physical address section is relatively consistent, so that invalid data can be more effectively recovered due to the fact that the data with different heat is classified during data recovery, and the data recovery efficiency is improved. The data migration amount is reduced, and the recovery efficiency is improved.

The invention discloses an incidence relation establishing method, a version number generating method and device, electronic equipment, a computer readable storage medium and a computer program product, and relates to the technical field of computers.The method comprises the steps that write-in requests of N read-write nodes are obtained, each write-in request carries to-be-written data and a version number of the corresponding read-write node. And writing the to-be-written data carried by each write-in request into the corresponding logic address section, wherein the version number is used for distinguishing the to-be-written data carried by different write-in requests. Transmitting the to-be-written data to the physical address section for storage, and respectively establishing an association relationship between the physical address section of each piece of to-be-written data and the version number corresponding to each piece of to-be-written data. Different read-write requests can be distinguished by using the version number, multi-version storage of the data is realized, the corresponding data can be traced through the version number, and the processing capability of the distributed storage system for concurrent write requests is remarkably improved.

The invention belongs to the field of memory control, and provides a mapping table management method and a storage device.The method comprises the steps that a write-in instruction from a host system is received; judging an access mode of the write-in instruction according to an access feature of a logic address corresponding to the write-in instruction; if the access mode of the write-in instruction is judged to be a continuous access mode, updating a mapping relation from a logic address to a physical address corresponding to the write-in instruction to a main mapping table; and if it is judged that the access mode of the write-in instruction is a random access mode, recording and managing a mapping relation from a logic address to a physical address corresponding to the write-in instruction through a temporary mapping table arranged in a buffer memory, and delaying updating of a main mapping table. Therefore, the random write-in performance of the storage device is improved, and the service life is prolonged.

The invention relates to the technical field of storage control, in particular to a memory control method, which comprises the following steps: acquiring a target logic address in response to a reading request from a host system; determining a data access mode associated with the target logic address in real time based on the historical access information, wherein the data access mode at least comprises a continuous mode, a random mode and a hotspot mode; according to the determined data access mode, triggering a data prefetching strategy and a flash translation layer query strategy matched with the access mode; obtaining target data from a memory module based on a data prefetching strategy and a flash translation layer query strategy; and scheduling the cache resources and the input / output bandwidth according to a predetermined resource management strategy, and returning the target data to the host system. The prefetching accuracy and the cache utilization rate are improved.

A method for performing data access management of a memory device in predetermined communications architecture with aid of unbalanced table update size and associated apparatus are provided. The method may include: utilizing a memory controller to receive a set of first commands from a host device, receive a set of first data with a first active block according to the set of first commands, and update a temporary physical-to-logical (P2L) address mapping table corresponding to the first active block; determining a selected table update size among multiple predetermined table update sizes according to at least one predetermined rule, wherein the multiple predetermined table update sizes represent multiple table entry counts, respectively; and updating at least one logical-to-physical address mapping table in the NV memory according to a set of P2L table entries corresponding to the selected table update size in the temporary P2L address mapping table, for further data accessing.

An apparatus for storing data in a nonvolatile memory includes a controller configured to erase a group of physical memory cells in the nonvolatile memory. The controller is configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory. The controller is configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory. The controller is configured to determine if the first group of physical memory cells fails a data integrity test. If the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory. The controller writes a single bit of information per cell in the second group of physical memory cells. The controller is configured to map the logical address range to a second physical address range for the second group of physical memory cells.

The invention discloses a storage space management method and device, a storage medium, electronic equipment and a program product, and relates to the technical field of distributed storage, and the method comprises the steps: obtaining a plurality of physical addresses of a plurality of physical storage equipment on a server corresponding to different nodes in a distributed storage system; a plurality of physical addresses are connected in series to generate address space pools corresponding to different servers, and linked lists corresponding to the address space pools are determined; under the condition of determining that the target object initiates the logical volume creation request, determining a target number of logical addresses from the address space pool according to the linked list, and recording a mapping relationship among the logical volume, the logical addresses and a target physical address associated with the logical addresses; the storage space associated with the logical volume is managed based on the mapping relation, the storage space at least comprises two physical storage devices, and the problem that when an existing distributed storage system carries out data storage, metadata access delay is caused by data striping is solved.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

In some implementations, a memory device may receive, from a host device, a write command instructing the memory device to write host data to a portion of a memory associated with a logical address. The memory device may determine a physical location of the memory associated with the logical address by using a wear leveling algorithm to map the logical address to the physical location of the memory, wherein the portion of the memory is associated with a wear leveling pool, and wherein the wear leveling algorithm maps the logical address to a portion of the wear leveling pool based on a randomized parameter. The memory device may write the host data to the physical location of the memory.

According to one embodiment, a controller of the memory system manages a plurality of zones using first information indicating (i) a correspondence between the zones and storage areas of a nonvolatile memory and (ii) a status of each of the zones. The status includes a first status indicating that data is written over an entire logical address range corresponding to a zone and a second status indicating that a zone is reset. In response to receiving a first command from a host device, the controller transmits to the host device a first list including information indicating a zone which is to be garbage collected. The zone is determined based on the first information.

The invention relates to the technical field of storage, in particular to a storage array controller, a storage array system and a data processing method. The storage array controller comprises a storage interface control module which is used for receiving and analyzing message data sent by a remote host to obtain an operation command, carrying out scheduling management on the operation command based on a namespace and then transmitting the operation command to a redundancy module; the redundancy module is used for performing redundancy calculation on the data, writing the data into a controller memory, and managing the logic address space of the storage array and the controller memory based on the namespace; and the nonvolatile storage control module responds to the data transmission request of the redundancy module and maps the controller memory to realize data interaction with the storage array, so that the problem of low read-write data processing efficiency of the existing storage array controller can be solved.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The present disclosure discloses example memory systems and operating methods thereof, and electronic systems. An example memory system includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command from a host, access a corresponding region of the memory device according to the read command, update hotness information of the corresponding region in a hotness table, determine one or more active regions based on the hotness information of regions in the hotness table, and send mapping information corresponding to the one or more active regions to the host. The hotness information includes a number of times a region is accessed by read commands from the host. The mapping information includes a mapping relationship table from logical address to physical address.

The invention discloses a data storage method, electronic equipment, a storage medium and a program product, and relates to the technical field of computers, a write request is received, and the write request is used for indicating to write target data in a solid state disk; according to the write request, determining a target association relationship between a target logic address and a target physical address of the target data in the solid state disk; the target association relationship is stored in a temporary cache region, after a cache threshold value of the temporary cache region reaches a preset threshold value, the target association relationship is stored in a target storage unit of the solid state disk, and the target storage unit is a physical storage medium used for storing the association relationship. The processing efficiency of data storage can be improved.

The invention provides a solid state disk data writing method and device and electronic equipment, and the method comprises the steps: when a solid state disk receives to-be-written data from a host, the to-be-written data is preferentially written into a target SLC physical block in a plurality of SLC physical blocks; if the quantity of the data written into the target SLC physical block reaches a moving waterline, selecting a target QLC physical block from the plurality of QLC physical blocks, and moving the data written into the target SLC physical block to the target QLC physical block; in the moving process, if the current writing programming mode is a QLC mode, effective data are screened out from the data written into the target SLC physical block during first programming; according to the writing sequence, storing the physical address and the logic address corresponding to the valid data in a pre-constructed temporary cache table; and when the second programming is passed, extracting the physical address and the logic address stored in the temporary cache table according to the write-in sequence, and reading data corresponding to the extracted physical address and logic address.

The invention provides a data processing method, device and system, and relates to the technical field of computers. According to the data processing method, an access logic address of a user in the storage system is converted into a first physical address and a second physical address, an error correction code is read or written according to the first physical address and the second physical address, and the first physical address and the second physical address correspond to different address spaces of different storage particles in a memory. Under the condition that the storage medium fault area has aggregation characteristics and the fault areas of different storage particles are the same or similar, code words of error correction codes are written or read in different address spaces, namely different bit fault rate areas, in different storage particles, so that the code words of the error correction codes are dispersed in the address spaces of the different bit fault rate areas; the maximum error bit number of the code word of the error correction code can be reduced, the error bit number difference of accessing different address spaces is reduced, the waste of error correction code resources is reduced, and the reliability of a memory is improved while the utilization rate of the error correction code resources is improved.

The invention relates to the technical field of network operation and maintenance and communication monitoring, and discloses a machine room fault node identification method and system based on network topology, and the method comprises the steps: obtaining real-time network topology data and link transmission indexes, and constructing a weighted directed graph and an evolution sequence; performing time sequence projection on the historical data according to the sequence to obtain a node state vector; calculating a deviation value, and if the deviation value exceeds the limit, extracting deviation characteristics and searching to obtain a potential abnormal region; dominant indexes are obtained through clustering and grouping, propagation influences are evaluated, and a priority sequence is determined; an initial fault source is positioned, a congestion link is tracked, and a service influence range is mapped through a logic address; extracting link safety risk characteristics, calculating a correction coefficient, adjusting an abnormal threshold value, and evaluating a positioning difficulty level; and finally, similar cases are retrieved to generate a repair instruction, model parameters are fed back and adjusted, and optimized stable configuration is obtained. According to the method, accurate recognition and closed-loop optimization of machine room faults can be realized.

The embodiment of the invention discloses a storage device, a controller of the storage device and a data reading method, the storage device comprises a plurality of storage areas, each storage area comprises a plurality of storage blocks, and the controller of the storage device comprises a cache management unit, a data cache unit and a control unit. The control unit is configured to determine whether read data meets a preset pre-reading condition or not, and in response to the fact that the read data meets the pre-reading condition, pre-reading operation of the at least one storage area is started, so that the read data in the at least one storage area is sequentially read into the data cache unit, and the read data in the at least one storage area are stored in the data cache unit. And storing the cache management information to a cache management unit, wherein the cache management information comprises a logic address of a storage block of the pre-read data. Therefore, according to the embodiment, pre-reading can be started after the read data meets the pre-reading condition, so that the problems of pre-reading failure, pre-reading cutoff and the like are avoided, the cache management information is managed by adopting the cache management unit, a software record management structure is reduced, and access delay is further reduced.

The invention discloses a power collection task allocation method, electronic equipment and a storage medium. The method comprises the steps that in response to a received task allocation instruction of a power collection task, a concentrator list of a power system is obtained, and the concentrator list comprises logic addresses, communication modes and allocation numbers of multiple concentrators; a target concentrator is determined based on the logic address in the concentrator list, and the target concentrator is a concentrator of a current to-be-allocated task in the plurality of concentrators; generating a power collection task of the target concentrator based on the communication mode of the target concentrator in the concentrator list and the factory information of the target concentrator; and allocating the power collection task to the target concentrator based on the task type of the power collection task. According to the invention, the technical problem of low distribution efficiency in the electric power collection task in the prior art is solved.

The invention discloses a fault recovery method of a storage pool, computer equipment, a storage medium and a product, and relates to the technical field of computers, and the method comprises the following steps: preferentially identifying and scanning a metadata area after the storage pool is offline, screening persistent effective metadata before offline, and storing the effective metadata in a database; metadata reconstruction is taken as a core to preferentially complete integration and restoration of a mapping relation between a logic address and a physical address instead of waiting for synchronous reconstruction of business data, so that the dilemma of long-time logic unavailability of a storage pool caused by synchronous processing of the metadata and the business data in a traditional restoration scheme is effectively broken through; according to the method, the target mapping relation table is quickly generated through conflict resolution and deletion completion processing, so that the interruption duration of the storage pool from offline to online can be remarkably shortened while the mapping accuracy is guaranteed, and the service access delay caused by unready metadata can be avoided.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

A host system can include a memory and a processing device, operatively coupled with the memory. The processing device is configured to perform operations including sending, to a memory device, data to be stored in the memory device, wherein the memory device comprises a plurality of dynamic capacity devices, wherein the plurality of dynamic capacity devices comprises a plurality of memory sections; receiving, from the memory device, a response including tag information, wherein the tag information comprises a set of tags in an order, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of the data; mapping the tags to logical addresses of the data; and accessing the data by aggregating, in the order of the set of tags, a plurality of device physical address (DPA) ranges, wherein each DPA range of the plurality of DPA ranges is associated with a respective tag of the tags.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention provides a key value cache scheduling method and device, a data processing method and device, a server and a medium. Relates to the technical field of data processing. The key value cache scheduling method is applied to a cache manager in a server for deploying a large model, and is used for uniformly scheduling cache resources when a heterogeneous accelerator executes large model reasoning. The method comprises the steps of obtaining a first request sent by a heterogeneous accelerator based on to-be-reasoned data, and determining the number of required cache blocks; selecting a plurality of target cache blocks from a preset memory cache region according to the cache block occupation state; and aggregating the logic addresses to generate a key value cache address and sending the key value cache address to the heterogeneous accelerator for accessing the key value data. According to the method, through a multi-level cache division and state awareness scheduling mechanism, the cache resource utilization rate and the cross-platform compatibility are effectively improved, the problems that an existing method is low in resource allocation efficiency and poor in compatibility are solved, and the large model reasoning efficiency and the system stability are remarkably improved.