957 results about "Logical address" patented technology

The invention relates to the technical field of microprocessors, and discloses a safety debugging method of an embedded microprocessor and the embedded microprocessor, the method comprises the following steps: implanting a random module in the microprocessor, constructing a resistance network array through random distribution of silicon substrate lattice defects to generate a disordered sequence, and if microprocessor data access is carried out, starting the random module; if physical intrusion is detected, a debugging session is established, three types of physical characteristics are synchronously generated to construct a composite key, a triple dynamic confusion layer is constructed in the microprocessor, the dynamic confusion layer and the composite key construct physical logic linkage protection, a probe access instruction logic address is called, if physical intrusion is detected, a probe triggers an invisible check point, and the probe accesses the invisible check point. The integrity of an execution environment is verified, if abnormal debugging is detected, a hardware defense mechanism is triggered, an access attack model is established, confusion parameters are trained and optimized, and a module interconnection mode is changed, so that the learning cycle of an attacker is broken, and the risk of attacking a processor in a machine learning mode is reduced.

The invention discloses a semiconductor device communication system and method based on an SECS / GEM protocol. The system comprises an SECS / GEM protocol processing module, a PLC communication module and a service logic processing module. The protocol processing module realizes message coding and decoding and state management through an HSMS / GEM layered architecture, and supports equipment capability dynamic negotiation; the PLC communication module adopts a factory mode to adapt to a multi-manufacturer controller to realize online mapping of a physical register and a logic address; and the business logic module dynamically loads the command processor based on a reflection mechanism, and realizes multi-condition event triggering through a rule engine. The method comprises the processes of system initialization, message priority scheduling, composite alarm processing and exception recovery, and the equipment integration efficiency and the communication reliability are remarkably improved. The method solves the problems of rigid parameter mapping, single event processing and poor equipment compatibility of a traditional scheme, and can be widely applied to equipment automation control of scenes such as semiconductor wafer manufacturing and packaging testing.

The invention discloses an incidence relation establishing method, a version number generating method and device, electronic equipment, a computer readable storage medium and a computer program product, and relates to the technical field of computers.The method comprises the steps that write-in requests of N read-write nodes are obtained, each write-in request carries to-be-written data and a version number of the corresponding read-write node. And writing the to-be-written data carried by each write-in request into the corresponding logic address section, wherein the version number is used for distinguishing the to-be-written data carried by different write-in requests. Transmitting the to-be-written data to the physical address section for storage, and respectively establishing an association relationship between the physical address section of each piece of to-be-written data and the version number corresponding to each piece of to-be-written data. Different read-write requests can be distinguished by using the version number, multi-version storage of the data is realized, the corresponding data can be traced through the version number, and the processing capability of the distributed storage system for concurrent write requests is remarkably improved.

The invention belongs to the field of memory control, and provides a mapping table management method and a storage device.The method comprises the steps that a write-in instruction from a host system is received; judging an access mode of the write-in instruction according to an access feature of a logic address corresponding to the write-in instruction; if the access mode of the write-in instruction is judged to be a continuous access mode, updating a mapping relation from a logic address to a physical address corresponding to the write-in instruction to a main mapping table; and if it is judged that the access mode of the write-in instruction is a random access mode, recording and managing a mapping relation from a logic address to a physical address corresponding to the write-in instruction through a temporary mapping table arranged in a buffer memory, and delaying updating of a main mapping table. Therefore, the random write-in performance of the storage device is improved, and the service life is prolonged.

The invention relates to the technical field of storage control, in particular to a memory control method, which comprises the following steps: acquiring a target logic address in response to a reading request from a host system; determining a data access mode associated with the target logic address in real time based on the historical access information, wherein the data access mode at least comprises a continuous mode, a random mode and a hotspot mode; according to the determined data access mode, triggering a data prefetching strategy and a flash translation layer query strategy matched with the access mode; obtaining target data from a memory module based on a data prefetching strategy and a flash translation layer query strategy; and scheduling the cache resources and the input / output bandwidth according to a predetermined resource management strategy, and returning the target data to the host system. The prefetching accuracy and the cache utilization rate are improved.

The invention discloses a storage space management method and device, a storage medium, electronic equipment and a program product, and relates to the technical field of distributed storage, and the method comprises the steps: obtaining a plurality of physical addresses of a plurality of physical storage equipment on a server corresponding to different nodes in a distributed storage system; a plurality of physical addresses are connected in series to generate address space pools corresponding to different servers, and linked lists corresponding to the address space pools are determined; under the condition of determining that the target object initiates the logical volume creation request, determining a target number of logical addresses from the address space pool according to the linked list, and recording a mapping relationship among the logical volume, the logical addresses and a target physical address associated with the logical addresses; the storage space associated with the logical volume is managed based on the mapping relation, the storage space at least comprises two physical storage devices, and the problem that when an existing distributed storage system carries out data storage, metadata access delay is caused by data striping is solved.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

In some implementations, a memory device may receive, from a host device, a write command instructing the memory device to write host data to a portion of a memory associated with a logical address. The memory device may determine a physical location of the memory associated with the logical address by using a wear leveling algorithm to map the logical address to the physical location of the memory, wherein the portion of the memory is associated with a wear leveling pool, and wherein the wear leveling algorithm maps the logical address to a portion of the wear leveling pool based on a randomized parameter. The memory device may write the host data to the physical location of the memory.

According to one embodiment, a controller of the memory system manages a plurality of zones using first information indicating (i) a correspondence between the zones and storage areas of a nonvolatile memory and (ii) a status of each of the zones. The status includes a first status indicating that data is written over an entire logical address range corresponding to a zone and a second status indicating that a zone is reset. In response to receiving a first command from a host device, the controller transmits to the host device a first list including information indicating a zone which is to be garbage collected. The zone is determined based on the first information.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention discloses a data storage method, electronic equipment, a storage medium and a program product, and relates to the technical field of computers, a write request is received, and the write request is used for indicating to write target data in a solid state disk; according to the write request, determining a target association relationship between a target logic address and a target physical address of the target data in the solid state disk; the target association relationship is stored in a temporary cache region, after a cache threshold value of the temporary cache region reaches a preset threshold value, the target association relationship is stored in a target storage unit of the solid state disk, and the target storage unit is a physical storage medium used for storing the association relationship. The processing efficiency of data storage can be improved.

The invention provides a data processing method, device and system, and relates to the technical field of computers. According to the data processing method, an access logic address of a user in the storage system is converted into a first physical address and a second physical address, an error correction code is read or written according to the first physical address and the second physical address, and the first physical address and the second physical address correspond to different address spaces of different storage particles in a memory. Under the condition that the storage medium fault area has aggregation characteristics and the fault areas of different storage particles are the same or similar, code words of error correction codes are written or read in different address spaces, namely different bit fault rate areas, in different storage particles, so that the code words of the error correction codes are dispersed in the address spaces of the different bit fault rate areas; the maximum error bit number of the code word of the error correction code can be reduced, the error bit number difference of accessing different address spaces is reduced, the waste of error correction code resources is reduced, and the reliability of a memory is improved while the utilization rate of the error correction code resources is improved.

The invention relates to the technical field of network operation and maintenance and communication monitoring, and discloses a machine room fault node identification method and system based on network topology, and the method comprises the steps: obtaining real-time network topology data and link transmission indexes, and constructing a weighted directed graph and an evolution sequence; performing time sequence projection on the historical data according to the sequence to obtain a node state vector; calculating a deviation value, and if the deviation value exceeds the limit, extracting deviation characteristics and searching to obtain a potential abnormal region; dominant indexes are obtained through clustering and grouping, propagation influences are evaluated, and a priority sequence is determined; an initial fault source is positioned, a congestion link is tracked, and a service influence range is mapped through a logic address; extracting link safety risk characteristics, calculating a correction coefficient, adjusting an abnormal threshold value, and evaluating a positioning difficulty level; and finally, similar cases are retrieved to generate a repair instruction, model parameters are fed back and adjusted, and optimized stable configuration is obtained. According to the method, accurate recognition and closed-loop optimization of machine room faults can be realized.

The embodiment of the invention discloses a storage device, a controller of the storage device and a data reading method, the storage device comprises a plurality of storage areas, each storage area comprises a plurality of storage blocks, and the controller of the storage device comprises a cache management unit, a data cache unit and a control unit. The control unit is configured to determine whether read data meets a preset pre-reading condition or not, and in response to the fact that the read data meets the pre-reading condition, pre-reading operation of the at least one storage area is started, so that the read data in the at least one storage area is sequentially read into the data cache unit, and the read data in the at least one storage area are stored in the data cache unit. And storing the cache management information to a cache management unit, wherein the cache management information comprises a logic address of a storage block of the pre-read data. Therefore, according to the embodiment, pre-reading can be started after the read data meets the pre-reading condition, so that the problems of pre-reading failure, pre-reading cutoff and the like are avoided, the cache management information is managed by adopting the cache management unit, a software record management structure is reduced, and access delay is further reduced.

The invention discloses a fault recovery method of a storage pool, computer equipment, a storage medium and a product, and relates to the technical field of computers, and the method comprises the following steps: preferentially identifying and scanning a metadata area after the storage pool is offline, screening persistent effective metadata before offline, and storing the effective metadata in a database; metadata reconstruction is taken as a core to preferentially complete integration and restoration of a mapping relation between a logic address and a physical address instead of waiting for synchronous reconstruction of business data, so that the dilemma of long-time logic unavailability of a storage pool caused by synchronous processing of the metadata and the business data in a traditional restoration scheme is effectively broken through; according to the method, the target mapping relation table is quickly generated through conflict resolution and deletion completion processing, so that the interruption duration of the storage pool from offline to online can be remarkably shortened while the mapping accuracy is guaranteed, and the service access delay caused by unready metadata can be avoided.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

A host system can include a memory and a processing device, operatively coupled with the memory. The processing device is configured to perform operations including sending, to a memory device, data to be stored in the memory device, wherein the memory device comprises a plurality of dynamic capacity devices, wherein the plurality of dynamic capacity devices comprises a plurality of memory sections; receiving, from the memory device, a response including tag information, wherein the tag information comprises a set of tags in an order, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of the data; mapping the tags to logical addresses of the data; and accessing the data by aggregating, in the order of the set of tags, a plurality of device physical address (DPA) ranges, wherein each DPA range of the plurality of DPA ranges is associated with a respective tag of the tags.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention provides a key value cache scheduling method and device, a data processing method and device, a server and a medium. Relates to the technical field of data processing. The key value cache scheduling method is applied to a cache manager in a server for deploying a large model, and is used for uniformly scheduling cache resources when a heterogeneous accelerator executes large model reasoning. The method comprises the steps of obtaining a first request sent by a heterogeneous accelerator based on to-be-reasoned data, and determining the number of required cache blocks; selecting a plurality of target cache blocks from a preset memory cache region according to the cache block occupation state; and aggregating the logic addresses to generate a key value cache address and sending the key value cache address to the heterogeneous accelerator for accessing the key value data. According to the method, through a multi-level cache division and state awareness scheduling mechanism, the cache resource utilization rate and the cross-platform compatibility are effectively improved, the problems that an existing method is low in resource allocation efficiency and poor in compatibility are solved, and the large model reasoning efficiency and the system stability are remarkably improved.

The invention provides a data processing method and device of a storage device, a medium and computer equipment. The data processing method comprises the following steps: analyzing a reading request initiated by a user, and obtaining a logical addresses to be read; determining c L2P mapping tables associated with the a logical addresses according to the range of the a logical addresses, wherein c is a positive integer greater than or equal to 1; backing up an original mapping relation of the c L2P mapping tables; b latest mapping relations of a temporary information layer are updated to the c L2P mapping tables, and the original mapping relations of the c L2P mapping tables are covered; querying the updated c L2P mapping tables according to the reading request, obtaining physical addresses corresponding to the a logical addresses, and reading data; and after the reading is completed, restoring the backed-up original mapping relation to the c L2P mapping tables. Through the mapping management process of the scheme, redundancy check can be avoided, accurate locking of an updating range is realized, the check times are greatly reduced, physical limitation of bandwidth is released, and delay is greatly reduced.

The invention relates to the technical field of data cache management, and discloses a segmented multi-level data cache management method and device, computer equipment and a storage medium. The method comprises the following steps: defining a hierarchical data management module, wherein the data management module comprises a first-level data interaction sub-module and a second-level cache hit management sub-module; receiving an upper-layer data access request, and performing data splitting according to the logic address relationship; querying the module state of the position according to the actual situation, and marking the cache hit management module state of the corresponding position; if the second-level cache hit management sub-modules to which the first-level data interaction sub-modules belong are all hit, realizing data communication with lower-layer storage equipment according to large granularity; and if part of data enters the cache, according to the continuity of the data hit state, respectively constructing commands with corresponding lengths to lower-layer storage equipment. By implementing the method provided by the invention, access requirements of different types of data can be effectively realized, the cache hit rate is improved, and better performance improvement is obtained.

The invention relates to the technical field of industrial automation, in particular to a PLC system control method and device based on dynamic address allocation and a storage medium, and the method comprises the steps that S1, a CPU module obtains a physical ID of an IO module; s2, generating a unique logic address for each physical ID, and establishing a mapping database; s3, the CPU module carries out handshake by taking the physical ID of the IO module as a communication identifier, and allocates the corresponding logic address to the corresponding IO module as a dynamic address; and S4, in the running process, the CPU module monitors the online state of the IO module through a heartbeat detection mechanism, releases the dynamic logic address of the offline IO module and updates the mapping database, and if a new IO module is online, the CPU module allocates the unoccupied logic address according to the physical ID number of the new IO module. According to the method, the unique logic address is generated for the physical ID, the security of the IO module is improved, the dynamic address is reallocated after the new IO module is online, the address allocation flexibility is improved, the physical ID and the dynamic address of the offline IO module are released, and limited address resources are saved.

The invention provides a data erasing method and a memory storage device, which can reduce the response time of a data erasing instruction so as to improve the performance of a host system. The memory storage device comprises a memory module and a memory control circuit unit. The data erasing method comprises the steps that in response to a data erasing instruction, multiple target mapping tables are determined according to a target logic address of the data erasing instruction, and the multiple target mapping tables comprise a first mapping table and a second mapping table; executing a data erasing operation on the first mapping table to erase mapping information corresponding to the target logic address in the first mapping table; performing data pre-erasing operation on the second mapping table to mark the second mapping table in the target index table; and sending a reply to indicate that the data erasing instruction is completed.

A storage device, including: a nonvolatile memory device including a plurality of memory cells; and a controller configured to, based on receiving an open zone command from an external host device: based on a number of free erase units from among a plurality of erase units included in the plurality of memory cells being greater than a threshold value, allocate at least two free erase units to a first-type zone, and based on the number of the free erase units being smaller than or equal to the threshold value, allocate the at least two free erase units to a second-type zone, wherein the controller is further configured to permit a random write based on a random logical address received from the external host device for the first-type zone, and to permit a zone write based on a sequential logical address received from the external host device for the second-type zone.

The invention relates to the technical field of storage system IO performance optimization, and provides a redirection data aggregation method and equipment, and the method comprises the steps: recognizing random small IO data from a written IO request, aggregating and writing back-end storage objects, and constructing a storage mapping relation in an index table; traversing the rear-end storage object in which the random small IO data is stored, and distributing data from the same logic address space to point to the same target rear-end storage object through a hash algorithm; writing the data distributed to point to the same target back-end storage object into the continuous physical space of the target back-end storage object in sequence, and updating the mapping relation in the index table; the step S2 and the step S3 are repeated before a preset termination triggering condition is met, and a hash algorithm different from all previous times is adopted when the step S2 is repeatedly executed each time; when the data are read, the storage mapping relation is obtained from the index table, and the read requests corresponding to the data located in the same back-end storage object are aggregated and then read at a time.

A method of controlling a storage device includes grouping one or more memory blocks in which physical addresses are continuous, among a plurality of memory blocks included in the device, generating a plurality of zones by mapping continuous physical addresses to continuous logical addresses, controlling sequential write operations using write pointers indicating a logical address of a region in which data is to be written in a next order in each of the plurality of zones, determining invalid zones in which all stored data is invalid data, among the plurality of zones, determining a utilization rate of a storage space of the storage device, determining a write pointer threshold based on the utilization rate, determining a target zone in which a write pointer value is greater than the write pointer threshold, among the invalid zones, and controlling the storage device to erase all memory blocks included in the target zone.

According to one embodiment, a memory system includes a nonvolatile memory, and a memory controller including first and second caches and a first controller. The first cache includes a first memory unit and a first control unit. The second cache includes a second memory unit and a second control unit. The first memory unit includes a plurality of entries each having a cache tag including a first field and a cache line. Upon receiving a first prefetch request for first data of a first logical address, the first control unit stores the first data in the cache line of a first entry included in the first memory unit, and stores a first value in the first field of the first entry. The first control unit maintains the first entry until receiving a read request or a write request for the first logical address from the host.

The invention discloses a data prefetching method and device, computer equipment and a storage medium, and belongs to the technical field of cloud computing. In the method, a host operating system of a first device can obtain a first IO request generated by the first device, determine a logic address of to-be-prefetched data based on the first IO request and a plurality of previous second IO requests, and further obtain the to-be-prefetched data from a second device based on the logic address of the to-be-prefetched data. Therefore, by pulling the data from the far-end device in advance, the time delay of reading the data subsequently by the home-end device can be reduced, so that the performance of a computer system is improved. Moreover, the to-be-prefetched data is predicted and prefetched by the host operating system, so that the data prefetching irrelevant to the storage hardware and the client operating system can be realized, and the application range is wider.

The present application relates to the technical field of storage application, and discloses a physical address query method, a flash memory device controller and a flash memory device. The physical address query method comprises: acquiring a logical address; by querying a compact array, determining whether the compact array can map the logical address to a corresponding physical address; if the compact array cannot map the logical address to the corresponding physical address, querying a range bucket hash structure to determine whether a range bucket node corresponding to the logical address exists in a least recently used cache; and if the range bucket node corresponding to the logical address exists in the least recently used cache, querying the logical address from the range bucket node to obtain the physical address corresponding to the logical address. By querying from the compact array and the range bucket hash structure the physical address corresponding to the logical address, the present application can save DRAM resources and also maintain high indexing performance, thereby improving the query efficiency of the physical address.