59 results about "Bit time" patented technology

The invention relates to the technical field of integrated circuits, and provides a self-adaptive frequency modulation and voltage regulation chip control circuit and method, the circuit comprises a time sequence monitoring module which comprises a critical path replication sub-module and a daisy chain delay sub-module which are connected, and the critical path replication sub-module is used for simulating an actual critical data path in a chip; the daisy chain delay sub-module is used for applying a configurable delay amount on a time sequence to the output data signal; the time sequence performance after different time points is simulated; the first trigger is used for transmitting data signals; the sampling trigger module is used for sampling the data signal output by the time sequence monitoring module; the comparison logic module is used for generating a multi-bit time sequence margin indication code according to a comparison result; the time sequence margin indication code is used for adaptively adjusting the working frequency or the working voltage of the chip. According to the invention, through accurate monitoring and self-adaptive adjustment of a chip time sequence, all design margins can be utilized, and the energy utilization efficiency is improved, so that extreme low power consumption is realized.

A commander substation for a serial bus system and a method for communication in a serial bus system are provided. The commander substation has a frame validity check block for checking whether a frame corresponding to a received signal is equal to a predetermined frame and thus error-free and therefore valid. The frame validity check block is configured to perform a first check to determine whether the frame corresponding to the received signal is valid if the bit time of the first communication phase of the predetermined frame has a predetermined value corresponding to a bit rate that is equal to or less than a predetermined bit rate. The frame validity check block is configured to perform a second check to determine whether the frame corresponding to the received signal is valid.if the bit time of the first communication phase of the predetermined frame has a predetermined value corresponding to a bit rate that is greater than the predetermined bit rate, and where the first check and the second check are at least partially different.

The application provides a dead loop processing method and device, electronic equipment and storage medium, a preset script function is run, and the number of instructions executed when the preset script function is run is monitored; if the number of instructions is greater than a preset number threshold, a function call stack when the preset script function executes instructions is acquired and recorded; the number of times that the function call stack is recorded within a preset time period is determined, if the number of times recorded satisfies a preset condition, the function call stack is determined as a dead loop stack; the dead loop stack is interrupted to remove the current dead loop. Through monitoring the number of instruction executions and the number of times that the function call stack is recorded, the method can realize fault positioning to the function point level, greatly shortening the dead loop positioning time; meanwhile, after the existence of a dead loop problem is found, the method automatically removes the dead loop, improving the server dead loop troubleshooting efficiency.

The application relates to the technical field of data processing, and discloses a continuous casting production process time sequence data segmentation method and device and computer equipment. The method comprises the following steps: collecting time sequence data in a continuous casting production process, covering a pulling speed, a stopper position, a crystallizer liquid level and the like. Any kind of time sequence data collected in a preset data segmentation period is denoised to obtain denoised time sequence data. The denoised time sequence data is grouped based on a preset unit time span, a dynamic time warping distance of a reference denoised time sequence data group corresponding to a plurality of preset key events of each group is calculated, and a reference group is determined. When the reference group exists, the number of preset unit time spans covering the preset unit time span is determined according to the comparison between the preset duration of the key event corresponding to the reference group and the preset unit time span, and then an actual data segment is determined and marked. The denoised time sequence data is flexibly and reasonably segmented according to different situations, and more suitable data units can be provided for subsequent data analysis and processing.

The invention provides an encoding device, a decoding device, an encoding method, a decoding method and a storage medium. An encoding device (100) is provided with a circuit and a memory connected to the circuit, and the circuit calculates a DPB output time [id] of a picture in a lower time sub-layer when id represents the lower time sub-layer other than the uppermost time sub-layer included in a plurality of time sub-layers (S201). In step S201, a circuit of an encoding device 100 subtracts a DPB output difference [id] provided for each time sub-layer from a common DPB output delay among a plurality of time sub-layers, and calculates a DPB output difference [id] by subtracting a CPB removal delay [max] and an offset [id] from a CPB removal delay [id] when max represents an uppermost time sub-layer. Next, the circuit stores an offset [id] in a bit stream (S202), calculates a value equal to or less than a DPB output delay [maxid] as the DPB output difference [id] by subtracting the offset [id], and estimates the offset [maxid] as zero without writing the offset [maxid] to the bit stream for the uppermost time sub-layer.

The invention discloses an SSL VPN tunnel speed limiting method and device and a storage medium. The method relates to the field of data transmission, and comprises the following steps: determining to send first data of a first data volume to a resource side from a client through an SSL VPN tunnel in unit time, and judging whether the first data volume reaches a preset proportion threshold of the maximum transmission volume of the SSL VPN tunnel; under the condition that the first data volume reaches a preset proportion threshold value of the maximum transmission volume, rewriting a first ACK acknowledgement message returned to the client by the resource side to obtain a second ACK acknowledgement message; and the second ACK confirmation message is transmitted to the client through the SSL VPN tunnel, and the client adjusts the data volume sent to the resource side in unit time according to the second ACK confirmation message. Through the method and the device, the problem that network transmission is unstable due to the fact that services in a tunnel cannot respond to tunnel speed limit in time and continue to send data at the original speed in the prior art is solved.

The application relates to a high-speed data acquisition and storage method, system, device and medium, and belongs to the technical field of signal acquisition and data storage. The method comprises the following steps: acquiring at least one high-voltage probe pulse signal and 24 switch probe signals in real time; attenuating the high-voltage probe pulse signal to the input threshold range of an optical coupling device, and performing signal conversion and electrical isolation to generate a TTL level signal; performing micro-capacitance charging and discharging detection on the switch probe signal to obtain switch probe timestamp data; encapsulating the TTL level signal, the switch probe timestamp data and 64-bit time reference data into a data frame, and transmitting the data frame through a main-backup dual-fiber channel in parallel; performing integrity check on the data frame at a receiving end, and dynamically allocating a storage physical address; responding to a host computer instruction to execute a storage data export or specified block erasing operation, and exporting a device digital signature and the storage physical address. The application can improve the data acquisition accuracy and storage security in transient events.

The application relates to the technical field of integrated circuits, and provides a chip control circuit and method for adaptive frequency modulation and voltage modulation, which comprises a timing monitoring module, a critical path replication submodule and a daisy chain delay submodule connected to the timing monitoring module, the critical path replication submodule is used for simulating an actual critical data path in a chip, the daisy chain delay submodule is used for applying a configurable delay amount on the timing of an output data signal, so as to simulate the timing performance after different time points, a first flip-flop is used for transmitting the data signal, a sampling flip-flop module is used for sampling the data signal output by the timing monitoring module, a comparison logic module is used for generating a multi-bit timing margin indication code through a comparison result, and the timing margin indication code is used for adaptively adjusting the working frequency or working voltage of the chip. Through accurate monitoring and adaptive adjustment of the timing of the chip, all design margins can be utilized, the energy utilization efficiency is improved, and therefore, the ultimate low power consumption is realized.

The application relates to a link quality detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: receiving a link layer discovery protocol packet sent by an interconnection device of a current device through a port of the interconnection device; determining a link factor corresponding to a link between the current device and the port according to the number of oscillations, the sending optical power and the receiving optical power of the port in a current unit time; the link factor is used to represent the link quality of the link; extracting the value of a link factor identification field in the link layer discovery protocol packet, determining the state of the link factor identification field according to the value of the link factor identification field; the state of the link factor identification field is used to represent the state of the port; and determining the link quality of the link according to the link factor and the state of the link factor identification field. The method can improve the accuracy of link quality detection.

The application provides a parameter dynamic configuration management method and device, equipment and medium. The method comprises the following steps: obtaining a running index corresponding to middleware in a preset unit time; analyzing the running index to determine whether the initial configuration of the consumption parameter of the middleware is dynamically adjusted; if the message accumulation quantity corresponding to the preset running index is greater than the maximum message accumulation quantity, the maximum consumption data quantity is increased for dynamic adjustment until the current running index is the optimal configuration; or / and, if the consumption data execution time in the preset running index is close to the maximum interval time of twice consumption, the maximum consumption data quantity is reduced for dynamic adjustment until the current running index is the optimal configuration. Through real-time analysis of the running index, the software can run in the optimal configuration, data accumulation is avoided, the consumption capacity of the middleware is improved, and the software has the advantages of high availability.

The invention provides a coding and decoding device and method and a storage medium. When id represents a lower time sub-layer other than the uppermost time sub-layer, the DPB output time [id] of the picture in the lower time sub-layer is calculated. A DPB output difference [id] provided for each sub-layer is subtracted from a common DPB output delay among a plurality of time sub-layers, and when max represents an uppermost sub-layer, the DPB output difference [id] is calculated by subtracting a CPB removal delay [max] and an offset [id] from the CPB removal delay [id]. Next, the offset [id] is stored in the bitstream, the offset [id] is subtracted to calculate a value equal to or less than the DPB output delay [maxid] as a DPB output difference [id], the offset [maxid] is estimated to be zero without writing the offset [maxid] to the bitstream for the uppermost time sub-layer, the offset [id] is subtracted to calculate a value equal to or less than the DPB output delay [maxid] as a DPB output difference [id] for the uppermost time sub-layer without using the DPB output difference [id], and the offset [maxid] is estimated to be zero without writing the offset [maxid] to the bitstream for the uppermost time sub-layer. The DPB output time [maxid] is calculated by adding the time calculated from the DPB output delay [maxid] to the CPB removal time [maxid].

The invention discloses a bandwidth control method and device, computing equipment, a storage medium and a program product, and the method comprises the steps: determining a target node in a plurality of nodes according to a received service request, the target node being used for responding to the service request; when it is detected that the bandwidth occupancy amount of the target node exceeds a preset value, predicting the bandwidth occupancy amount of the target node after a preset time to obtain a predicted value; when the predicted value meets a set condition, the limit of the target node is determined based on a first state machine and the current bandwidth occupation amount of the target node, and the limit is the scheduling amount allowed by the target node in unit time; the first state machine comprises a plurality of bandwidth occupancy intervals and a limit determination rule corresponding to each bandwidth occupancy interval. The limit can be determined according to the prediction condition of the bandwidth demand, the utilization rate of the bandwidth is ensured, and fast recovery of the limit is realized.

A commander subscriber station for a serial bus system and a method for communication in a serial bus system are provided. The commander subscriber station has a frame validity check block for checking whether a frame corresponding to a received signal is equal to a predetermined frame and is thus error-free and therefore valid. The frame validity check block is designed to carry out a first check as to whether the frame corresponding to the received signal is valid, if the bit time of the first communication phase of the predetermined frame has a predetermined value corresponding to a bit rate which is equal or less than a predetermined bit rate, and the frame validity check block is configured to carry out a second check as to whether the frame corresponding to the received signal is valid, if the bit time of the first communication phase of the predetermined frame has a predetermined value corresponding to a bit rate which is greater than the predetermined bit rate, the first check and the second check being at least partially different.

The fetch circuit (110) fetches, for each cycle time, a command at the cycle time as a reference command, and fetches, as a comparison command, a command at a cycle time before the cycle time by a shift time of one or more cycles. A comparison circuit (120) compares, for each cycle time, the fetched comparison command with a reference command fetched at a cycle time that is prior to the shift time than the cycle time at which the comparison command was fetched. A calculation circuit (140) calculates the compared reference command when the compared reference command matches the compared comparison command for each cycle time.

Disclosed herein are optical networks and nodes, including a head-end node comprising a controller and a line module. The line module comprises a first processor and first memory storing instructions that when executed by the first processor cause the first processor to receive fault information, generate a fault packet and a fault trigger request that include a sequence number, a sequence reset time, and the fault information, and send the fault packet via a first network path and the fault trigger request via a second network path to the controller. The controller comprises a second processor, second memory storing second instructions, and packet forwarding circuitry configured to receive and automatically forward the fault packet to a tail-end optical node. The second instructions cause the second processor to receive the fault trigger request, process the fault trigger request, and send the fault trigger request to the tail end optical node.

The invention relates to the technical field of industrial control network security, in particular to a role-based intelligent power plant industrial control network access control method, which comprises the following steps of S1, collecting an operation instruction stream, and generating an operation sequence with a timestamp; s2, extracting an operation type, a target equipment identifier and an operation frequency in unit time from the operation sequence to form a feature vector of the current operation; s3, performing similarity matching on the feature vector and a predefined role operation template; s4, if the similarity exceeds a preset dynamic threshold value, activating the access authority corresponding to the role; s5, generating a dynamic access token; and S6, verifying the validity and the permission range of the dynamic access token carried by the request. According to the invention, through multi-dimensional behavior matching and a dynamic token mechanism, accurate authorization and safety control of industrial control operation of the intelligent power plant are realized, and the flexibility of access management and the safety of system operation are improved.

The invention discloses a method and system for diagnosing interface mirroring different-rate CAN network segment communication and a vehicle. The method for mirroring different-rate CAN network segment communication through the diagnostic interface comprises the steps that a diagnostic message sent by a diagnostic instrument is received, and the system clock frequency and the target baud rate of a controller to be diagnosed are obtained according to the diagnostic message; obtaining a Baud rate pre-frequency division value according to the system clock frequency and the time quantum length; obtaining a first bit time period and a second bit time period of the total bit time of the CAN bus according to the system clock frequency and the target baud rate; and setting the timing register according to the Baud rate pre-frequency division value, the first bit time period and the second bit time period so as to change the CAN rate of the diagnosis interface. According to the embodiment of the invention, the method can effectively achieve the mirroring of the communication of CAN network segments at different rates through a diagnosis interface, and can achieve the efficient and comprehensive monitoring and diagnosis of all related CAN network segments.

A video player includes a processor; and a memory that includes instructions, which when executed, cause the processor to execute the following steps: predicting a future throughput by using a past throughput value; configuring a search space for identifying a quality adaptation schedule; extracting a plurality of paths in the search space; estimating, based on the future throughput, a quality of experience value for each path of the extracted plurality of paths; identifying a path corresponding to a highest quality of experience value from among the estimated quality of experience values, as the quality adaptation schedule; determining, based on the quality adaptation schedule, a quality value of a chunk to be requested for the future unit time interval subsequent to the current unit time interval; requesting the chunk with the determined quality value; and receiving the chunk with the determined quality value.

This invention relates to a bus-based data transmission method, apparatus, device, and storage medium. The bus-based data transmission method includes: when a signal edge is detected before the start of a synchronization segment of the next bit time on the bus, acquiring a sampling sequence obtained from multiple samplings, the sampling sequence being used to characterize the quality of the signal edge; determining a target bit synchronization strategy from among several preset bit synchronization strategies based on the sampling sequence, different bit synchronization strategies defining different bit segment adjustment methods; and adjusting a target phase buffer segment of the current bit time for data transmission based on the target bit synchronization strategy, the target phase buffer segment being the interval preceding the synchronization segment. This application evaluates signal quality through the sampling sequence and adopts a corresponding synchronization strategy based on the evaluation result, realizing dynamic adjustment of bit synchronization, effectively reducing synchronization errors caused by noise, and further improving the stability and reliability of data transmission.

The present application relates to general aviation equipment mobile edge computing data security technical field, specifically relates to the security mobile edge computing secret throughput efficiency optimization method of multi-unmanned plane cooperation, the method includes: building multi-unmanned plane cooperation security mobile edge computing system;Channel and rate model, task and delay model are constructed, and a secret throughput efficiency model is constructed;Based on the secret throughput efficiency model, a joint optimization problem with the maximum secret throughput efficiency as the target is constructed;The joint optimization problem is solved.The present application strengthens the data transmission security of physical layer by multi-unmanned plane cooperation, realizes the balance of data security and computing efficiency with composite index, and the solving framework is efficient and feasible, significantly improves the effective bit number of safe task completion per unit time of unmanned plane, and is suitable for low-altitude economy and other security sensitive edge computing scenarios.

The invention discloses a quick reset method of a solid state disk (SSD), the SSD comprises a plurality of command processing modules and is used for processing read-write commands issued by a host, and the method comprises the following steps: after receiving a reset request, immediately replying a reset completion response to the host; marking the command which is not processed at present as a discarding identifier so as to be identified by a plurality of command processing modules in the SSD; and in the subsequent task execution process, if the multiple command processing modules identify the discarding identifier, asynchronously releasing the resources associated with the corresponding commands without blocking the reply process of the reset completion response. Therefore, according to the SSD quick reset method provided by the embodiment of the invention, the reset time is shorter, the host response is faster, and the reset action completion time is at a millisecond level. When the link is abnormal or the controller is reset, the IO return-to-zero phenomenon can be avoided, and the reliability of the system and the user experience are improved.

A subscriber station (10; 30) for a serial bus system (1) and a method for communication in a serial bus system (1) are provided. The subscriber station (10; 30) has a communication control device (11; 31) for controlling communication of the subscriber station (10; 20; 30) with at least one further subscriber station (10; 20; 30) of the bus system (1) and for evaluating a signal (VDIFF) received from a bus (40) of the bus system (1), in which signal a bit time (t_bt1) in a first communication phase (451) can be different from a bit time (t_bt2) in a second communication phase (452), wherein the communication control device (11; 31) is designed to sample and evaluate the signal (VDIFF) received from the bus (40) on the basis of a transmission signal (TxD_TC) generated by a further subscriber station (10; 20; 30) in accordance with a predetermined frame (450; 450A).

The invention discloses a network security protection method and device, a storage medium and a computer program product, and belongs to the technical field of network security. The method comprises the steps that transmission behavior information of a to-be-analyzed file in a network link within a preset time period is acquired, and the transmission behavior information comprises processing actions of other security gateway devices in the network link on the to-be-analyzed file; according to the transmission behavior information, blocking related characteristics of the to-be-analyzed file are determined, and the blocking related characteristics comprise at least one of blocking frequency in preset unit time and blocking rate in the preset unit time; determining a virus risk level of the to-be-analyzed file according to the blocking related features; under the condition that the virus risk level is high risk, extracting target features of the to-be-analyzed file, and adding the target features to a temporary virus feature library; and under the condition that the features of the transfer file are matched with the features in the temporary virus feature library, performing blocking operation on the transfer file. According to the invention, the network security protection can be improved.

This invention discloses a two-step ADC circuit, conversion method, and application based on an automatically calibrated DCO. The circuit includes: automatically calibrating the DCO to perform frequency calibration of the coarse and fine quantization clocks; the first step of the ADC is a single-step M-bit SS ADC coarse quantization, and the second step is fine quantization. For fine quantization, the residual time is first extracted by a residual time detection module, and then the DCO is activated to generate a fine quantization clock to perform N-bit time-to-digital quantization on the residual time. Both steps together achieve an ADC with M+N-bit quantization accuracy. The automatic calibration ensures that the output fine quantization clock frequency of the DCO meets the frequency matching requirements of the two-step ADC system for the coarse and fine quantization clock frequencies. This circuit features small area, high sampling rate, high resolution, low power consumption, no need for global high-frequency clock transmission, and limited high-frequency clock duration, making it suitable for high-performance image sensors and infrared focal plane detector readout circuits.

The invention discloses a conveying line multi-direction in-place detection method and system and a storage medium. A first object detection sensor and a second object detection sensor are arranged in the diagonal direction of a transverse and longitudinal conveying intersection area of a tray conveying line; position information of the virtual deceleration detection points and the virtual in-place detection points in all directions and operation parameter information of the conveying line are set; recording the difference between the starting time and the ending time when one object detection sensor is shielded by the tray, measuring and calculating the size of the tray in the running direction by combining the actual speed of the conveying line read in real time, and synchronizing the actual speed of the conveying line; when the two sensors are triggered by the tray, the first trigger is a deceleration point, the later trigger is an in-place point, the distances from the two points to the corresponding virtual detection points are read according to the direction of the tray, deceleration parameters and in-place parameters are calculated in combination with the rated high speed and the rated low speed of the conveying line, and a deceleration instruction is sent when the deceleration time is reached; and sending a stop instruction when the bit time is reached. The virtual detection point is used for replacing an entity sensor for positioning, so that the hardware cost of the sensor is reduced.

This invention discloses a message encoding method to improve frame loss during OTA upgrades. The method sets a single-frame write message for an OTA upgrade to include a first message group, a second message group, and a third message group. Each of these groups consists of two bits. The first message group contains two bits of write data. The second message group includes one bit of time synchronization data and one bit of first restoration data. The third message group includes one bit of checksum data and one bit of second restoration data. The time synchronization data is sequentially and cyclically set within a certain range as the single-frame write messages are sent frame by frame. The checksum data is calculated using a set checksum algorithm. The first and second restoration data are the corresponding numbers of different functions in a preset restoration function library. The first and second restoration data of the current frame write message are obtained based on the write data of the current frame, the write data of the next frame write message, and the function library.

This disclosure provides an adaptive decoding method and system for aviation data bus, relating to the field of aviation data technology. The method includes receiving 429 aviation bus data to be decoded and converted; performing an AND-OR operation on the 429 aviation bus data and saving the result; calculating the bus bit time of the 429 aviation bus data, dividing the bus bit time by frequency and storing it in the sampling interval; sampling once at the rising edge of each sampling interval and shifting it left in real time to save it in a shift register; using a shift register sequence detection method to adaptively decode and receive the sampled values ​​saved in real time; designing a fault tolerance rate for the interval between two sampled values; when the transmission rate changes, if more than half of the current n data sampled values ​​are 1, and more than half of the subsequent n clock sampled values ​​are 0, then the sampled data is determined to be 1, thus achieving the correct decoding and reception process of the 429 aviation data. This disclosure ensures the accuracy of data decoding and reception.

A bandwidth used in a network of a communication system is suppressed. Communication system includes master device and slave device. Master device includes: first counter that increments a first count value every time a first unit time elapses; second counter that updates a second count value every time a second unit time elapses; and master transmitter that transmits timing information indicating a timing at which the second count value is updated to slave device. Slave device includes: third counter that increments a third count value every time the first unit time elapses; fourth counter that increments a fourth count value every time a third unit time shorter than the first unit time lapses, and resets the fourth count value at a timing of incrementing the third count value; and slave receiver that receives the timing information from master transmitter.

Apparatuses and methods for beamforming for joint phase-time arrays (JPTAs). In some embodiments, a method for operating a base station (BS) is provided. The method includes receiving a first value by at least one beamforming integrated circuit (BFIC) and receiving a second value by at least one time delay integrated circuit (TDIC). The method further includes configuring, by the at least one BFIC, a phase shift generated by at least one phase shifter based on the first value, configuring, by the at least one TDIC, a time delay generated by at least one time delay unit based on the second value, and generating one or more beams for JPTA based on the configured phase shift and time delay.

The present application relates to the technical field of integrated circuit design, more particularly, to a memory and computing unit circuit based on edge transmission delay, and a multi-bit time-domain multiply-accumulate calculation circuit constructed by using the unit circuit. The memory and computing unit circuit comprises two SRAM storage units, a delay calculation unit and a bit line connection switch. The two SRAM storage units are used for storing the weights required in calculation and providing 2-bit weights as multipliers. The delay calculation unit adopts four local delay units, each of which can calculate 2-bit weight multiplied by 2-bit input, so that the delay calculation unit can calculate 2-bit weight multiplied by 8-bit input, so as to improve the calculation efficiency. In addition, an inverter for regulating the edge signal is added in the local delay unit, so as to improve the accuracy of unit delay and time-domain accumulation.