110 results about "Bit time" patented technology

The invention discloses a multi-device high real-time control method based on an RS485 (Recommended Standard 485) bus. The system comprises two RS485 communication channels, one RS485 communication channel is used for generating a periodic synchronization pulse, the other RS485 communication channel is used for transmitting data, slave scanning and time sequence synchronization between each slave and a host are realized through the periodic synchronization pulse and a phase-locked loop of each slave, and each slave is connected with the host after a fixed delay duration of a periodic synchronization pulse signal. And starting to send data not exceeding the preset quantity. The method has the beneficial effects that the host and all the slaves are ensured to send data by using respective time slices in one communication period without conflicts, the synchronism of the data is ensured, the utilization rate of the bus is improved, and more data can be transmitted in unit time.

A resource configuration method, and a communication apparatus. In the method, a network device configures N PRACH resource sets for a terminal device, and on the basis of first sequence information, the terminal device sequentially uses M PRACH resource sets among the N PRACH resource sets to perform a random access attempt, the first sequence information being used for determining the sequence of using the M PRACH resource sets to attempt random access. In the method, different PRACH resource sets can be matched with terminal devices having different access capabilities, such that access of a plurality of types of terminals can be improved. In addition, because a plurality of PRACH resource sets are configured, the number of devices using each PRACH resource set for access is relatively reduced, such that PRACH resources configured for each PRACH resource set in a time domain and / or a frequency domain can be relatively sparse, reducing the number of PRACH resources configured per unit time and thus improving resource utilization.

This application discloses example service processing methods and apparatuses. One example method includes obtaining a quantity of transmission windows corresponding to each of n services within a unit time period or in a unit data frame, wherein the unit time period or the unit data frame comprises m transmission windows, a total quantity of transmission windows corresponding to the n services is not greater than m, and both m and n are integers greater than 1. Corresponding transmission windows from the m transmission windows can then be allocated to each service based on the quantity of transmission windows corresponding to each of the n services. Based on the transmission windows corresponding to each service, service data of then services can then be multiplexed into multiplexed data transmitted in one channel. The multiplexed data can then be sent.

The invention relates to the technical field of integrated circuits, and provides a self-adaptive frequency modulation and voltage regulation chip control circuit and method, the circuit comprises a time sequence monitoring module which comprises a critical path replication sub-module and a daisy chain delay sub-module which are connected, and the critical path replication sub-module is used for simulating an actual critical data path in a chip; the daisy chain delay sub-module is used for applying a configurable delay amount on a time sequence to the output data signal; the time sequence performance after different time points is simulated; the first trigger is used for transmitting data signals; the sampling trigger module is used for sampling the data signal output by the time sequence monitoring module; the comparison logic module is used for generating a multi-bit time sequence margin indication code according to a comparison result; the time sequence margin indication code is used for adaptively adjusting the working frequency or the working voltage of the chip. According to the invention, through accurate monitoring and self-adaptive adjustment of a chip time sequence, all design margins can be utilized, and the energy utilization efficiency is improved, so that extreme low power consumption is realized.

The invention relates to the technical field of integrated circuits, and discloses a bandwidth adaptive equalization method and device, equipment, a storage medium and a program product. The method comprises the following steps: monitoring the service condition of each secondary node, and performing classified caching according to a response data unloading rate to generate a request cache queue; generating a target number of traffic tokens corresponding to each secondary node according to the response data unloading rate every first unit time; polling the request cache queues and the traffic token number corresponding to each secondary node under each bandwidth competition node every second unit time, and generating node continuous marking request cache queues corresponding to each bandwidth competition node, and continuously scheduling the service requests of the node continuous mark request buffer queues corresponding to the bandwidth competition nodes to a target side for the target side to respond and execute. According to the scheme, the bandwidth of each secondary node can be distributed in a balanced manner all the time in the dynamic operation process of the system, and the stability of the bandwidth performance of the system is ensured.

The invention discloses a high-integration-level passive phase shifter based on 1-bit time sequence control of single side band time modulation. The high-integration-level passive phase shifter is provided with a differential orthogonal signal generation unit, an I-path input buffer unit, a Q-path input buffer unit, an I-path vector synthesis unit, a Q-path vector synthesis unit, an output amplification unit and a digital time sequence control unit. Radio frequency input differential signals RFin + and RFin-are connected with the differential orthogonal generation unit, the differential orthogonal generation unit is connected with the input buffer unit, vector synthesis is carried out through the I-path vector synthesis unit and the Q-path vector synthesis unit, the output end of the output amplification unit is the output end of the passive phase shifter, radio frequency output differential signals RFout + and RFout-are connected with the output end of the output amplification unit, and the output end of the output amplification unit is connected with the output end of the passive phase shifter. And the digital time sequence control unit controls insertion loss of the I-path vector synthesis unit and the Q-path vector synthesis unit, so that a digital control phase shift function is realized.

The invention relates to a clock calibration method and device. The method comprises the following steps: obtaining a corresponding relation between a reference clock frequency generated by an internal oscillator and a baud rate frequency of a universal asynchronous transceiver; obtaining a time sequence error of each bit time in a transmission period of the universal asynchronous transceiver according to the corresponding relationship, and accumulating the time sequence errors into an accumulated error; and compensating the accumulative error to calibrate the Baud rate frequency.

A subscriber station (10; 20; 30) and a method for deterministic communication in a serial bus system (1) are provided. The subscriber station (10; 20; 30) has a communication control device (11; 21; 31) for controlling communication between the subscriber station (10; 20; 30) and at least one other subscriber station (20; 30; 10) of the bus system (1) by generating messages (45; 46) based on a frame (450) and by sending the messages (45; 46) to a bus (40) of the bus system (1) and by evaluating at least one signal (VDIFF; RXD) received from a bus (40) of the bus system (1) based on the frame (450), in which frame (450) the bit time (t_bt1) in a first communication phase (451) can differ from a bit time (t_bt2) in a second communication phase (452), and a pause module (152) for evaluating at least one of the communication control device (11; 21;31) output status information (ST_A) regarding whether or not a predetermined frame (450_B) has been received from the bus (40), wherein the pause module (152) is configured to generate and output a transmission delay signal (TX_E) based on a result of its evaluation in order to delay or not delay the provision of a transmission message (1511A) to the communication control device (11; 21; 31);

The present disclosure relates to a system (108) and a method (500) for network congestion management. The system (108) receives a request for determining a back-off time value for one or more UEs (104) from one or more network entities (110). The system (108) validates the request and transmits an error response when the validation is unsuccessful. The system (108) retrieves a set of operational data associated with the one or more UEs (104) from a database (210) or the one or more network entities (110). The system (108) predicts the back-off time values for the requested one or more UEs (104). The back-off time value may be predicted using an Artificial Intelligence (AI) engine (214) based on a set of parameters associated with the retrieved data. The system (108) transmits the predicted back-off time value to the one or more network entities (110).

The invention relates to a high-speed data acquisition and storage method, system and device and a medium, and belongs to the technical field of signal acquisition and data storage, and the method comprises the steps: collecting at least one path of high-voltage probe pulse signals and 24 paths of switch probe signals in real time; attenuating the high-voltage probe pulse signal to an input threshold range of an optocoupler, and performing signal conversion and electrical isolation to generate a TTL level signal; performing micro-capacitor charging and discharging detection on the switch probe signal, and recording to obtain switch probe timestamp data; tTL level signals, switch probe timestamp data and 64-bit time reference data are packaged into data frames, and the data frames are parallel through main and standby dual-fiber channels; performing integrity verification on the data frame at a receiving end, and dynamically allocating and storing a physical address; and responding to an upper computer instruction, executing storage data export or specified block erasing operation, and exporting a data additional equipment digital signature and a storage physical address. According to the invention, the collection precision and storage security of the data in the transient event can be improved.

A commander substation for a serial bus system and a method for communication in a serial bus system are provided. The commander substation has a frame validity check block for checking whether a frame corresponding to a received signal is equal to a predetermined frame and thus error-free and therefore valid. The frame validity check block is configured to perform a first check to determine whether the frame corresponding to the received signal is valid if the bit time of the first communication phase of the predetermined frame has a predetermined value corresponding to a bit rate that is equal to or less than a predetermined bit rate. The frame validity check block is configured to perform a second check to determine whether the frame corresponding to the received signal is valid.if the bit time of the first communication phase of the predetermined frame has a predetermined value corresponding to a bit rate that is greater than the predetermined bit rate, and where the first check and the second check are at least partially different.

A subscriber station for a serial bus system and a method for communication in a serial bus system. The subscriber station has a communication control device for controlling a communication of the subscriber station with at least one other subscriber station of the bus system and for evaluating a signal received from a bus of the bus system, in which the bit time in a first communication phase may differ from a bit time in a second communication phase, and the communication control device is developed to sample and evaluate the signal received from the bus, which is based on a transmit signal generated by another subscriber station, according to a predefined frame.

The application provides a dead loop processing method and device, electronic equipment and storage medium, a preset script function is run, and the number of instructions executed when the preset script function is run is monitored; if the number of instructions is greater than a preset number threshold, a function call stack when the preset script function executes instructions is acquired and recorded; the number of times that the function call stack is recorded within a preset time period is determined, if the number of times recorded satisfies a preset condition, the function call stack is determined as a dead loop stack; the dead loop stack is interrupted to remove the current dead loop. Through monitoring the number of instruction executions and the number of times that the function call stack is recorded, the method can realize fault positioning to the function point level, greatly shortening the dead loop positioning time; meanwhile, after the existence of a dead loop problem is found, the method automatically removes the dead loop, improving the server dead loop troubleshooting efficiency.

The application relates to the technical field of data processing, and discloses a continuous casting production process time sequence data segmentation method and device and computer equipment. The method comprises the following steps: collecting time sequence data in a continuous casting production process, covering a pulling speed, a stopper position, a crystallizer liquid level and the like. Any kind of time sequence data collected in a preset data segmentation period is denoised to obtain denoised time sequence data. The denoised time sequence data is grouped based on a preset unit time span, a dynamic time warping distance of a reference denoised time sequence data group corresponding to a plurality of preset key events of each group is calculated, and a reference group is determined. When the reference group exists, the number of preset unit time spans covering the preset unit time span is determined according to the comparison between the preset duration of the key event corresponding to the reference group and the preset unit time span, and then an actual data segment is determined and marked. The denoised time sequence data is flexibly and reasonably segmented according to different situations, and more suitable data units can be provided for subsequent data analysis and processing.

The invention provides an encoding device, a decoding device, an encoding method, a decoding method and a storage medium. An encoding device (100) is provided with a circuit and a memory connected to the circuit, and the circuit calculates a DPB output time [id] of a picture in a lower time sub-layer when id represents the lower time sub-layer other than the uppermost time sub-layer included in a plurality of time sub-layers (S201). In step S201, a circuit of an encoding device 100 subtracts a DPB output difference [id] provided for each time sub-layer from a common DPB output delay among a plurality of time sub-layers, and calculates a DPB output difference [id] by subtracting a CPB removal delay [max] and an offset [id] from a CPB removal delay [id] when max represents an uppermost time sub-layer. Next, the circuit stores an offset [id] in a bit stream (S202), calculates a value equal to or less than a DPB output delay [maxid] as the DPB output difference [id] by subtracting the offset [id], and estimates the offset [maxid] as zero without writing the offset [maxid] to the bit stream for the uppermost time sub-layer.

The invention discloses an SSL VPN tunnel speed limiting method and device and a storage medium. The method relates to the field of data transmission, and comprises the following steps: determining to send first data of a first data volume to a resource side from a client through an SSL VPN tunnel in unit time, and judging whether the first data volume reaches a preset proportion threshold of the maximum transmission volume of the SSL VPN tunnel; under the condition that the first data volume reaches a preset proportion threshold value of the maximum transmission volume, rewriting a first ACK acknowledgement message returned to the client by the resource side to obtain a second ACK acknowledgement message; and the second ACK confirmation message is transmitted to the client through the SSL VPN tunnel, and the client adjusts the data volume sent to the resource side in unit time according to the second ACK confirmation message. Through the method and the device, the problem that network transmission is unstable due to the fact that services in a tunnel cannot respond to tunnel speed limit in time and continue to send data at the original speed in the prior art is solved.

The application relates to a high-speed data acquisition and storage method, system, device and medium, and belongs to the technical field of signal acquisition and data storage. The method comprises the following steps: acquiring at least one high-voltage probe pulse signal and 24 switch probe signals in real time; attenuating the high-voltage probe pulse signal to the input threshold range of an optical coupling device, and performing signal conversion and electrical isolation to generate a TTL level signal; performing micro-capacitance charging and discharging detection on the switch probe signal to obtain switch probe timestamp data; encapsulating the TTL level signal, the switch probe timestamp data and 64-bit time reference data into a data frame, and transmitting the data frame through a main-backup dual-fiber channel in parallel; performing integrity check on the data frame at a receiving end, and dynamically allocating a storage physical address; responding to a host computer instruction to execute a storage data export or specified block erasing operation, and exporting a device digital signature and the storage physical address. The application can improve the data acquisition accuracy and storage security in transient events.

The application relates to the technical field of integrated circuits, and provides a chip control circuit and method for adaptive frequency modulation and voltage modulation, which comprises a timing monitoring module, a critical path replication submodule and a daisy chain delay submodule connected to the timing monitoring module, the critical path replication submodule is used for simulating an actual critical data path in a chip, the daisy chain delay submodule is used for applying a configurable delay amount on the timing of an output data signal, so as to simulate the timing performance after different time points, a first flip-flop is used for transmitting the data signal, a sampling flip-flop module is used for sampling the data signal output by the timing monitoring module, a comparison logic module is used for generating a multi-bit timing margin indication code through a comparison result, and the timing margin indication code is used for adaptively adjusting the working frequency or working voltage of the chip. Through accurate monitoring and adaptive adjustment of the timing of the chip, all design margins can be utilized, the energy utilization efficiency is improved, and therefore, the ultimate low power consumption is realized.

The embodiment of the present application discloses a clock synchronization method and related devices, which can be applied to smart phones or wireless speakers. The method includes: obtaining a first time slice group, the first time slice group including multiple first time slices. The first timestamps in the first time slices are continuous, and the first timestamps corresponding to two adjacent first time slices are partially the same. According to the first time slice group, the first detection clock or the second detection clock is adjusted. Through the sliding window technology, the timestamp data is effectively multiplexed in adjacent time slices, and the number of detection signals sent by the computing device per unit time is reduced as much as possible under the premise of providing a sufficient number of time slices. Under the premise of ensuring clock synchronization, the burden on the computing device and the network is reduced.

The application relates to a link quality detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: receiving a link layer discovery protocol packet sent by an interconnection device of a current device through a port of the interconnection device; determining a link factor corresponding to a link between the current device and the port according to the number of oscillations, the sending optical power and the receiving optical power of the port in a current unit time; the link factor is used to represent the link quality of the link; extracting the value of a link factor identification field in the link layer discovery protocol packet, determining the state of the link factor identification field according to the value of the link factor identification field; the state of the link factor identification field is used to represent the state of the port; and determining the link quality of the link according to the link factor and the state of the link factor identification field. The method can improve the accuracy of link quality detection.

A subscriber station (10; 30) for a serial bus system (1) and a method for communicating in a serial bus system (1) are provided. The subscriber station (10; 30) has a communication control device (11; 31) for controlling the communication of the subscriber station (10; 20; 30) with at least one further subscriber station (10; 20; 30) of the bus system (1) and for generating a transmission signal (TXD) such that for messages (45) exchanged between subscriber stations (10, 20, 30) of the bus system (1) a bit time (t_bt1) of the signal transmitted onto the bus (40) in a first communication phase (451) is distinguishable from a bit time (t_bt2) of the signal transmitted in a second communication phase (452); wherein the communication control device (11; 31) is configured to generate the transmission signal (TxD) in accordance with a frame (450) and to insert a field (DAS) with an edge into the frame (450) after the second communication phase (452); wherein the field (DAS) has a predetermined length before the edge corresponding to a duration (T_RB) which is longer than a duration of the bit time (t_bt1) of the first communication phase (451); and wherein a communication control device (21; 31; 11) of at least one further subscriber station (10; 20; 30) of the bus system (1) is provided with an edge for synchronizing to the communication on the bus (40), a transmission / reception device (22; 32; 12) of the at least one further subscriber station (10; 20; 30) switching into an operating mode (B_451) for transmitting and receiving the frame (450) in the first communication phase (451) before the predetermined duration (T_RB).

The application provides a parameter dynamic configuration management method and device, equipment and medium. The method comprises the following steps: obtaining a running index corresponding to middleware in a preset unit time; analyzing the running index to determine whether the initial configuration of the consumption parameter of the middleware is dynamically adjusted; if the message accumulation quantity corresponding to the preset running index is greater than the maximum message accumulation quantity, the maximum consumption data quantity is increased for dynamic adjustment until the current running index is the optimal configuration; or / and, if the consumption data execution time in the preset running index is close to the maximum interval time of twice consumption, the maximum consumption data quantity is reduced for dynamic adjustment until the current running index is the optimal configuration. Through real-time analysis of the running index, the software can run in the optimal configuration, data accumulation is avoided, the consumption capacity of the middleware is improved, and the software has the advantages of high availability.

The invention provides a coding and decoding device and method and a storage medium. When id represents a lower time sub-layer other than the uppermost time sub-layer, the DPB output time [id] of the picture in the lower time sub-layer is calculated. A DPB output difference [id] provided for each sub-layer is subtracted from a common DPB output delay among a plurality of time sub-layers, and when max represents an uppermost sub-layer, the DPB output difference [id] is calculated by subtracting a CPB removal delay [max] and an offset [id] from the CPB removal delay [id]. Next, the offset [id] is stored in the bitstream, the offset [id] is subtracted to calculate a value equal to or less than the DPB output delay [maxid] as a DPB output difference [id], the offset [maxid] is estimated to be zero without writing the offset [maxid] to the bitstream for the uppermost time sub-layer, the offset [id] is subtracted to calculate a value equal to or less than the DPB output delay [maxid] as a DPB output difference [id] for the uppermost time sub-layer without using the DPB output difference [id], and the offset [maxid] is estimated to be zero without writing the offset [maxid] to the bitstream for the uppermost time sub-layer. The DPB output time [maxid] is calculated by adding the time calculated from the DPB output delay [maxid] to the CPB removal time [maxid].

The invention discloses a bandwidth control method and device, computing equipment, a storage medium and a program product, and the method comprises the steps: determining a target node in a plurality of nodes according to a received service request, the target node being used for responding to the service request; when it is detected that the bandwidth occupancy amount of the target node exceeds a preset value, predicting the bandwidth occupancy amount of the target node after a preset time to obtain a predicted value; when the predicted value meets a set condition, the limit of the target node is determined based on a first state machine and the current bandwidth occupation amount of the target node, and the limit is the scheduling amount allowed by the target node in unit time; the first state machine comprises a plurality of bandwidth occupancy intervals and a limit determination rule corresponding to each bandwidth occupancy interval. The limit can be determined according to the prediction condition of the bandwidth demand, the utilization rate of the bandwidth is ensured, and fast recovery of the limit is realized.

A video player includes a processor; and a memory that includes instructions, which when executed, cause the processor to execute the following steps: predicting a future throughput by using a past throughput value; configuring a search space for identifying a quality adaptation schedule; extracting a plurality of paths in the search space; estimating, based on the future throughput, a quality of experience value for each path of the extracted plurality of paths; identifying a path corresponding to a highest quality of experience value from among the estimated quality of experience values, as the quality adaptation schedule; determining, based on the quality adaptation schedule, a quality value of a chunk to be requested for the future unit time interval subsequent to the current unit time interval; requesting the chunk with the determined quality value; and receiving the chunk with the determined quality value.

The invention provides a method and a device for solving a time error in 2038. The method comprises the following steps: aiming at the condition that a kernel version of an operating system is smaller than a first preset version, responding to a first operation of a user, setting 64-bit time to obtain system calling and 64-bit time setting system calling, so that an application program obtains and sets 64-bit time, the bit number of RTC time is modified into 64 bits, and kernel time of the operating system comprises 64-bit time; when the application program is in the running state, the application program processes 64-bit time through a preset 64-bit time processing function, and the preset 64-bit time processing function is set in a source code of the application program. According to the method and the device, the operation system can directly process the 64-bit time by using the original kernel version without upgrading the kernel version, the scheme is simple, and the difficulty of processing the 64-bit time by the operation system is reduced.

An integrated circuit is described.This integrated circuit may comprise: a receiving circuit coupled to a segment of a LIN bus that receives bits; a measuring circuit coupled to the receiving circuit that measures: a rising edge time and a falling edge time in the bits or a bit time and a second bit time in the bits; control logic coupled to the measuring circuit that compares the rising edge time and the falling edge time or the bit time and the second bit time; a transmitting circuit coupled to the receiving circuit that transmits the bits on a second segment of the LIN bus; and a delay circuit coupled to the control logic that applies a delay to one or more rising edges or falling edges in the bits or one or more bit times or second bit times in the bits based at least in part on the comparison.

A commander subscriber station for a serial bus system and a method for communication in a serial bus system are provided. The commander subscriber station has a frame validity check block for checking whether a frame corresponding to a received signal is equal to a predetermined frame and is thus error-free and therefore valid. The frame validity check block is designed to carry out a first check as to whether the frame corresponding to the received signal is valid, if the bit time of the first communication phase of the predetermined frame has a predetermined value corresponding to a bit rate which is equal or less than a predetermined bit rate, and the frame validity check block is configured to carry out a second check as to whether the frame corresponding to the received signal is valid, if the bit time of the first communication phase of the predetermined frame has a predetermined value corresponding to a bit rate which is greater than the predetermined bit rate, the first check and the second check being at least partially different.

The fetch circuit (110) fetches, for each cycle time, a command at the cycle time as a reference command, and fetches, as a comparison command, a command at a cycle time before the cycle time by a shift time of one or more cycles. A comparison circuit (120) compares, for each cycle time, the fetched comparison command with a reference command fetched at a cycle time that is prior to the shift time than the cycle time at which the comparison command was fetched. A calculation circuit (140) calculates the compared reference command when the compared reference command matches the compared comparison command for each cycle time.

Disclosed herein are optical networks and nodes, including a head-end node comprising a controller and a line module. The line module comprises a first processor and first memory storing instructions that when executed by the first processor cause the first processor to receive fault information, generate a fault packet and a fault trigger request that include a sequence number, a sequence reset time, and the fault information, and send the fault packet via a first network path and the fault trigger request via a second network path to the controller. The controller comprises a second processor, second memory storing second instructions, and packet forwarding circuitry configured to receive and automatically forward the fault packet to a tail-end optical node. The second instructions cause the second processor to receive the fault trigger request, process the fault trigger request, and send the fault trigger request to the tail end optical node.