10 results about "Bit time" patented technology

The application relates to a link quality detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: receiving a link layer discovery protocol packet sent by an interconnection device of a current device through a port of the interconnection device; determining a link factor corresponding to a link between the current device and the port according to the number of oscillations, the sending optical power and the receiving optical power of the port in a current unit time; the link factor is used to represent the link quality of the link; extracting the value of a link factor identification field in the link layer discovery protocol packet, determining the state of the link factor identification field according to the value of the link factor identification field; the state of the link factor identification field is used to represent the state of the port; and determining the link quality of the link according to the link factor and the state of the link factor identification field. The method can improve the accuracy of link quality detection.

This invention relates to a bus-based data transmission method, apparatus, device, and storage medium. The bus-based data transmission method includes: when a signal edge is detected before the start of a synchronization segment of the next bit time on the bus, acquiring a sampling sequence obtained from multiple samplings, the sampling sequence being used to characterize the quality of the signal edge; determining a target bit synchronization strategy from among several preset bit synchronization strategies based on the sampling sequence, different bit synchronization strategies defining different bit segment adjustment methods; and adjusting a target phase buffer segment of the current bit time for data transmission based on the target bit synchronization strategy, the target phase buffer segment being the interval preceding the synchronization segment. This application evaluates signal quality through the sampling sequence and adopts a corresponding synchronization strategy based on the evaluation result, realizing dynamic adjustment of bit synchronization, effectively reducing synchronization errors caused by noise, and further improving the stability and reliability of data transmission.

The present application relates to general aviation equipment mobile edge computing data security technical field, specifically relates to the security mobile edge computing secret throughput efficiency optimization method of multi-unmanned plane cooperation, the method includes: building multi-unmanned plane cooperation security mobile edge computing system;Channel and rate model, task and delay model are constructed, and a secret throughput efficiency model is constructed;Based on the secret throughput efficiency model, a joint optimization problem with the maximum secret throughput efficiency as the target is constructed;The joint optimization problem is solved.The present application strengthens the data transmission security of physical layer by multi-unmanned plane cooperation, realizes the balance of data security and computing efficiency with composite index, and the solving framework is efficient and feasible, significantly improves the effective bit number of safe task completion per unit time of unmanned plane, and is suitable for low-altitude economy and other security sensitive edge computing scenarios.

This invention discloses a message encoding method to improve frame loss during OTA upgrades. The method sets a single-frame write message for an OTA upgrade to include a first message group, a second message group, and a third message group. Each of these groups consists of two bits. The first message group contains two bits of write data. The second message group includes one bit of time synchronization data and one bit of first restoration data. The third message group includes one bit of checksum data and one bit of second restoration data. The time synchronization data is sequentially and cyclically set within a certain range as the single-frame write messages are sent frame by frame. The checksum data is calculated using a set checksum algorithm. The first and second restoration data are the corresponding numbers of different functions in a preset restoration function library. The first and second restoration data of the current frame write message are obtained based on the write data of the current frame, the write data of the next frame write message, and the function library.

This disclosure provides an adaptive decoding method and system for aviation data bus, relating to the field of aviation data technology. The method includes receiving 429 aviation bus data to be decoded and converted; performing an AND-OR operation on the 429 aviation bus data and saving the result; calculating the bus bit time of the 429 aviation bus data, dividing the bus bit time by frequency and storing it in the sampling interval; sampling once at the rising edge of each sampling interval and shifting it left in real time to save it in a shift register; using a shift register sequence detection method to adaptively decode and receive the sampled values ​​saved in real time; designing a fault tolerance rate for the interval between two sampled values; when the transmission rate changes, if more than half of the current n data sampled values ​​are 1, and more than half of the subsequent n clock sampled values ​​are 0, then the sampled data is determined to be 1, thus achieving the correct decoding and reception process of the 429 aviation data. This disclosure ensures the accuracy of data decoding and reception.

A fetch circuit (110) fetches, for each cycle time, an instruction of the cycle time as a reference instruction, and also fetches an instruction of a cycle time that is earlier than the cycle time by a shift time of one or more cycles as a comparison instruction. A comparison circuit (120) compares, for each cycle time, a comparison instruction that is fetched with a reference instruction fetched at a cycle time that is earlier than a cycle time at which the comparison instruction is fetched by the shift time. When the compared reference instruction matches the compared comparison instruction, an operation circuit (140) executes the compared reference instruction, for each cycle time.

This invention discloses a method and system for intelligent load balancing regulation of charging piles, specifically relating to the field of power distribution load control technology. The method includes: collecting station-level and pile-level operating data at a preset cycle, and constructing a closed-loop operating record containing timestamps of command issuance, confirmation, and response arrival; based on the record, statistically analyzing communication and execution delays within a sliding monitoring window to generate a comprehensive quantity of link and execution delay stability and a set of target value reachability constraints; performing predictive scheduling and command shaping based on dynamic safety margins, and outputting target power or current commands for each pile; performing acceptance testing according to response arrival criteria, and updating the comprehensive quantity of oscillation tendency to correct scheduling parameters in a closed loop. The system includes a closed-loop timing archive module, a delay steady-state constraint module, a margin prediction scheduling module, and an execution acceptance correction module for implementing the above steps.

The application discloses an FM0 decoding method and device with anti-interference capability, and comprises the following steps: S1, four one-bit-width FIFOs, fifo0, fifo1, fifo2 and fifo3, input signals are sampled by a clock and stored in the FIFOs, and two FM0 encoding bit time sampling data are stored in the FIFOs; S2, four accumulators record the accumulated values of the sampling values in the corresponding FIFOs; S3, the four accumulated values are respectively judged as high or low F0, F1, F2 and F3; S4, after being converted into absolute values, the accumulators are summed to obtain a total value; S5, the change of the total value is used to find a peak value, and the peak value is used to correct a sampling time; and S6, whether the high and low values and the total value are greater than a threshold value is used to judge whether the FM0 encoding is valid, and the FM0 output data is valid, and the application relates to the technical field of communication. The application solves the problem that many high-frequency interferences often occur in a real communication system, and the interferences can cause communication failure of a decoding method relying on a jump time.

The present disclosure relates to a 5G or 6G communication system that supports higher data transmission rates than 4G communication systems such as LTE (Long Term Evolution). For an Open Radio Access Network (O-RAN) system, the supported hybrid beamforming settings are indicated based on the number of analog ports, the number of digital ports, the number of analog ports per transceiver, and the supported codebook. The hybrid beamforming settings to be used include control bit vectors for phase shifters, each control bit vector being mapped to a phase value, an in-phase (I) value, and an orthogonal phase (Q) value. The hybrid beamforming settings may include analog and digital beamforming parameters or Joint Phase-Time Array (JPTA) parameters applicable to a frequency band or subband.