3 results about "Duty cycle distortion" patented technology

This application relates to data bus duty cycle distortion compensation. An electrical circuit arrangement includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit operably coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle of a plurality of signals communicated via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles, and comparing the representative duty cycle of the plurality of signals communicated via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting trim values associated with the plurality of duty cycles of the plurality of signals based on the comparison result to compensate for distortion in the plurality of duty cycles, and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim values.

The application discloses a delay modulation circuit, a method, a chip and a server. The delay modulation circuit comprises a delay circuit, a delay reference unit, a comparison signal generation unit and a control module. The delay circuit is used for outputting a first pulse signal after delay processing. The delay reference unit is used for outputting a corresponding second pulse signal according to a clock signal. The comparison signal generation unit is used for outputting a corresponding comparison signal according to the first pulse signal and the second pulse signal. The control module is used for generating a corresponding control signal according to the comparison signal, and adjusting a delay time of the delay circuit for delay processing according to the control signal. The deviation between the first pulse signal and the second pulse signal is represented by the comparison signal, the corresponding control signal is generated, the current delay time of the delay circuit is adjusted according to the control signal, the gap between the current delay time and a preset delay time is reduced, and the duty cycle distortion of the first pulse signal generated by the delay circuit is avoided, thereby ensuring the accuracy of the first pulse signal.

A delay optimizer includes circuits for detecting delay between the received data and the received clock, such as in an integrated circuit having separate dies coupled to communication via an interconnect that includes a clock channel and a data channel. The electrical characteristics of the clock channel and the data channel (including on-chip buffers) may introduce significant differences in the delay between the received clock and the received data coupled with the effects of clock jitter, inter-symbol interference, and duty-cycle distortion that may introduce significant sampling errors in the sampled data. The delay optimizer operates to detect the delay and optimize a sampling clock in real-time and on a continuous basis using the difference between the data edge of the received data and the received clock edge to determine an optimal delay value to sample the received data to produce the sampled data with the desired very-low bit-error-rate (BER).