12 results about "Duty cycle distortion" patented technology

A level-shifter is provided that balances the pull-up and pull-down of a pair of internal nodes. To balance the pull-down of the internal nodes, a pull-down strength of a pull-down network is also responsive to a power supply voltage for the level-shifter. To balance the pull-up of the internal nodes, a pull-up strength of a pull-up network is also responsive to an amplitude of an input signal being level-shifted by the level-shifter.

This application relates to data bus duty cycle distortion compensation. An electrical circuit arrangement includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit operably coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle of a plurality of signals communicated via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles, and comparing the representative duty cycle of the plurality of signals communicated via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting trim values associated with the plurality of duty cycles of the plurality of signals based on the comparison result to compensate for distortion in the plurality of duty cycles, and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim values.

The present disclosure relates to techniques for measuring slew rate in a current integrating phase interpolator. An apparatus is described that includes a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal containing a periodic sawtooth waveform therefrom; a digital-to-analog (D / A) converter for setting an input common mode voltage of the inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and a circuit for calculating a difference between a first state of the DCD of the clock signal corresponding to the inverter circuit being set to a high voltage input common mode voltage and a second state of the DCD of the clock signal corresponding to the inverter circuit being set to a low voltage input common mode voltage.

The invention relates to a single-wire communication method, a communication system, a readable storage medium and a program product, and the method comprises the steps: receiving a target carrier clock signal transmitted through a serial communication channel for an nth slave device; the target carrier clock signal is a carrier clock signal which is sent by the master device, carries an original carrier clock signal of target communication data, and is obtained after the original carrier clock signal is subjected to phase reversal processing of part or all of the first (n-1) slave devices; and decoding the target communication data from the target carrier clock signal by identifying the carrier level duration of the effective carrier level in the target carrier clock signal. In the transmission process of the carrier clock signal along the serial communication channel, the carrier clock signal is subjected to selective phase reversal processing by the slave device on the communication link, so that the problems of duty ratio distortion and signal attenuation caused by long-distance transmission can be effectively avoided, the accuracy and reliability of communication data transmission are guaranteed, and the transmission efficiency is improved. And the expandability of the communication system can be effectively improved.

A circuit for reducing duty cycle distortion of a clock signal includes an amplifier configured to receive an input clock signal and generate an amplified clock signal. The circuit also includes a filter coupled to the amplifier and configured to generate a filtered clock signal based on the amplified clock signal. The circuit also includes a gating circuit coupled to the filter and configured to receive the filtered clock signal and selectively output the filter clock signal responsive to a first control signal. The circuit also includes a control circuit coupled to the gating circuit and the filter, where the control circuit is configured to receive a timing signal, receive an enable signal, and generate the first and a second control signal based on the timing and enable signals. The second control signal alters impedance of a feedback path of the filter.

The application discloses a delay modulation circuit, a method, a chip and a server. The delay modulation circuit comprises a delay circuit, a delay reference unit, a comparison signal generation unit and a control module. The delay circuit is used for outputting a first pulse signal after delay processing. The delay reference unit is used for outputting a corresponding second pulse signal according to a clock signal. The comparison signal generation unit is used for outputting a corresponding comparison signal according to the first pulse signal and the second pulse signal. The control module is used for generating a corresponding control signal according to the comparison signal, and adjusting a delay time of the delay circuit for delay processing according to the control signal. The deviation between the first pulse signal and the second pulse signal is represented by the comparison signal, the corresponding control signal is generated, the current delay time of the delay circuit is adjusted according to the control signal, the gap between the current delay time and a preset delay time is reduced, and the duty cycle distortion of the first pulse signal generated by the delay circuit is avoided, thereby ensuring the accuracy of the first pulse signal.

In embodiments, a clock signal calibration circuit for communication transmitters includes a multiplexer that creates a combined output pattern from input data patterns in reaction to the clock signal's edges. It uses a calibration data pattern generator, which supplies two sequential patterns-the second being a shifted copy of the first-to the multiplexer. An averaging circuit then generates two averaged signals corresponding to these patterns. Duty cycle control circuitry corrects clock signal imbalances if these averaged signals are unequal, thus adjusting the duty cycle distortion to achieve an ideal 50% duty cycle.

A level-shifter is provided that balances the pull-up and pull-down of a pair of internal nodes. To balance the pull-down of the internal nodes, a pull-down strength of a pull-down network is also responsive to a power supply voltage for the level-shifter. To balance the pull-up of the internal nodes, a pull-up strength of a pull-up network is also responsive to an amplitude of an input signal being level-shifted by the level-shifter.

A memory device including an array of memory cells and a circuit disposed within the memory device to compare a voltage level associated with a selected digital data input signal corresponding to a write operation associated with a set of memory cells of the array of memory cells to a reference voltage level to generate a comparison result. The memory device further includes control logic operatively coupled to the circuit, the control logic to identify, based on the comparison result, a duty cycle distortion level associated with the selected digital data input signal; and generate, based on the duty cycle distortion level, a command comprising a code to adjust a duty cycle associated with the selected digital data input signal.

A measurement circuit includes a ring oscillator, a first counter coupled to an output of the ring oscillator, and a second counter coupled to the output of the ring oscillator. The measurement circuit also includes a signal generator configured to receive a clock signal, generate a first count enable signal based the clock signal and output the first count enable signal to the first counter, and generate a second count enable signal based on the clock signal and output the second count enable signal to the second counter.

The invention discloses a method for improving the IO anti-noise capability of an eMMC memory, and belongs to the technical field of eMMC memories. The eMMC particle mainly solves the problem that an existing eMMC particle is prone to communication errors under changes of process, temperature and voltage due to lack of timing sequence adjusting capacity. Through software and hardware collaborative design of an eMMC particle end, a signal time sequence is actively optimized. In the aspect of hardware, a delay chain and a duty ratio adjusting circuit are introduced into an IO path and are used for adjusting the relative phase relation between a clock and data and correcting duty ratio distortion of an input clock respectively. In the aspect of software, through a set of parameter search process, an optimal parameter combination capable of maximizing an effective data window is dynamically searched and locked. The data transmission robustness of the eMMC interface in a severe environment, the compatibility with different hosts and the overall reliability of the system are effectively improved, and meanwhile the low power consumption cost is kept.

A delay optimizer includes circuits for detecting delay between the received data and the received clock, such as in an integrated circuit having separate dies coupled to communication via an interconnect that includes a clock channel and a data channel. The electrical characteristics of the clock channel and the data channel (including on-chip buffers) may introduce significant differences in the delay between the received clock and the received data coupled with the effects of clock jitter, inter-symbol interference, and duty-cycle distortion that may introduce significant sampling errors in the sampled data. The delay optimizer operates to detect the delay and optimize a sampling clock in real-time and on a continuous basis using the difference between the data edge of the received data and the received clock edge to determine an optimal delay value to sample the received data to produce the sampled data with the desired very-low bit-error-rate (BER).