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Level shifter having low duty cycle distortion

A level converter, level technology, applied in electrical components, generating electrical pulses, pulse technology and other directions, can solve problems such as large duty cycle distortion

Active Publication Date: 2010-03-31
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Its duty cycle distortion is larger than the circuit specification allows

Method used

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  • Level shifter having low duty cycle distortion
  • Level shifter having low duty cycle distortion
  • Level shifter having low duty cycle distortion

Examples

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Embodiment Construction

[0022] image 3 is a simplified diagram of a level shifting circuit according to one novel aspect. The level shift circuit 100 includes: an input node 101, a cross-coupled level shift latch 102, a set-reset (SR) logic gate latch 103, an inverter circuit 104, an inverter 105, a buffer 106, and an output Node 107. The digital input signal IN is received on input node 101, then level shifted and output on node 107 as a digital output signal OUT. The digital input signal IN transitions within a first signal voltage range (eg, from ground potential to a VDDL voltage of about 1.2 volts). The digital output signal OUT transitions within the second signal voltage range (eg, from ground potential to a VDDH voltage of approximately 1.8 volts). The level shifting circuit 100 is implemented in complementary logic including P-channel field effect transistors and N-channel field effect transistors.

[0023] The inverter circuit 104 includes a non-inverting digital logic circuit 108 and a...

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PUM

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Abstract

A level shifter (100) includes an inverting circuit (104), a cross-coupled level shifting latch (102), and a SR logic gate latch (103). The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal (IND) onto a first input of the level shifting latch (112) and supplies an inverted version of the input signal (INB) onto a second input of the level shifting latch (113). A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, andthe level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.

Description

technical field [0001] Embodiments disclosed herein relate to level shifting circuits, and more particularly, to high speed level shifting circuits exhibiting low duty cycle distortion and high supply voltage margin. Background technique [0002] Digital logic circuits can be powered by different supply voltages. In one example, an integrated circuit includes a first digital logic block operating at a first supply voltage, and a second digital logic block operating at a second supply voltage. If a digital signal is passed from one logic block to another, the digital level of the signal must be converted. Circuits called level shifters are sometimes used to perform this level shifting function. [0003] FIG. 1 (Prior Art) is a circuit diagram of a conventional level shifter 1 . Reference VDDL designates a first supply voltage (eg, 1.2 volts) and reference VDDH designates a second supply voltage (eg, 1.8 volts). If the digital input signal IN on input node 2 transitions fr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/356
CPCH03K3/356113
Inventor C·李
Owner QUALCOMM INC
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