164 results about "Digital logic circuits" patented technology

The invention provides a method and device for optimizing the layout of a digital logic circuit and a storage medium, and the method comprises the steps: dividing a layout diagram of the digital logic circuit into a plurality of cells, each cell comprises a plurality of elements, determining to-be-optimized elements in the cells based on the current layout and an optimization target of the digital logic circuit, and optimizing the layout of the digital logic circuit according to the to-be-optimized elements. The optimization target comprises at least one of a line length target, a congestion target or a density target, obtaining a target density function value according to the target model based on the layout characteristics of the cells, and adjusting the position of the element to be optimized in the cells based on the target density function value so as to optimize the layout of the digital logic circuit. By means of the method, automatic layout optimization of the digital logic circuit can be achieved, labor time and cost are saved, and the performance of a chip is further improved.

A system, method and apparatus for executing a bioinformatics analysis on genetic sequence data is provided. Particularly, a genomics analysis platform for executing a sequence analysis pipeline is provided. The genomics analysis platform includes one or more of a first integrated circuit, where each first integrated circuit forms a central processing unit (CPU) that is responsive to one or more software algorithms that are configured to instruct the CPU to perform a first set of genomic processing steps of the sequence analysis pipeline. Additionally, a second integrated circuit is also provided, where each second integrated circuit forming a field programmable gate array (FPGA), the FPGA being configured by firmware to arrange a set of hardwired digital logic circuits that are interconnected by a plurality of physical interconnects to perform a second set of genomic processing steps of the sequence analysis pipeline, the set of hardwired digital logic circuits of each FPGA being arranged as a set of processing engines to perform the second set of genomic processing steps. A shared memory is also provided.

Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.

The invention provides a method and device for optimizing the layout of a digital logic circuit and a storage medium, and the method comprises the steps: determining a first layout of the digital logic circuit, the first layout comprises a plurality of macro cells and a plurality of standard cells, determining channels formed between the adjacent macro cells, and optimizing the layout of the digital logic circuit based on an optimization target of the digital logic circuit, according to the positions of the standard unit and the channel, the target step length parameter of the standard unit is determined, the optimization target comprises at least one of a line length target, a density target and a time sequence target, and the standard unit is adjusted based on the target step length parameter so as to optimize the layout of the digital logic circuit. By means of the method, automatic layout optimization of the digital logic circuit can be achieved, the influence of a channel on layout optimization is reduced, and the performance of a chip is further improved.

The embodiment of the invention provides a chip module and a laser radar, and the chip module comprises a photosensitive chip which is provided with a photosensitive area and comprises a first substrate, at least one photosensitive unit and at least one quenching unit, the photosensitive unit and the quenching unit are located on the first substrate, and the photosensitive unit is located in the photosensitive area; the signal processing chip is electrically connected with the photosensitive chip in a first direction through a hybrid bonding stacking process, is suitable for processing electric signals output by the photosensitive unit and comprises a second substrate, a control circuit, a digital reading circuit and a digital logic circuit, and the control circuit, the digital reading circuit and the digital logic circuit are located on the second substrate. And the projections of the digital logic circuit and the photosensitive area in the direction vertical to the first direction are at least partially overlapped. By adopting the technical scheme, the utilization rate of the photosensitive area in the chip module can be improved.

The embodiment of the invention provides a noise shaping circuit and an analog-to-digital converter, which can be applied to the technical field of integrated circuits. The noise shaping circuit comprises a plurality of switches, a first capacitor, a second capacitor and a buffer connected between the first capacitor and the second capacitor, the plurality of switches are configured to respond to a switch control signal and alternatively enable one of the first capacitor and the second capacitor to serve as an integrating capacitor to be connected to the analog signal input end, so that the integrating capacitor provides an integrating voltage for the buffer based on a margin voltage provided by the analog signal input end and a capacitor voltage stored in the integrating capacitor; the other one of the first capacitor and the second capacitor is used as a storage capacitor, and the integral voltage flowing through the buffer is received and stored; the integrating capacitor is configured to output an integrating voltage to the output end of the noise shaping circuit, so that the digital logic circuit performs analog-to-digital conversion on the integrating voltage to obtain a margin voltage and provide the margin voltage to the analog signal input end.

Technologies directed to determine whether a frequency of a clock signal is outside a specified frequency range are described. One integrated circuit includes a signal generator circuit, a voltage divider circuit, and digital logic circuitry. The signal generator circuit generates phase signals from a clock signal. The voltage divider circuit converts a frequency of the clock signal to a voltage representing the frequency. The voltage divider circuit includes a first resistor and a first switched-capacitor structure to receive the phase signals. An average resistance of the first switched-capacitor structure is inversely proportional to the frequency of the clock signal. The digital logic circuitry can determine, using the voltage, whether the frequency is outside of a specified frequency range, and output an indication responsive to the frequency being outside the specified frequency range.

The invention discloses a circuit area optimization method based on an AND XOR majority diagram, and relates to a digital logic circuit area optimization method. According to the method, an input integrated circuit is converted into an AIG netlist, then cutting and replacement are carried out in the AIG netlist according to AIG equivalent structures of XOR gate nodes and majority logic gate nodes, equivalent gate nodes are covered on the AIG netlist according to a cutting result, and the AIG netlist is finally converted into an AXMIG netlist through mapping. Area optimization of the AND gate not limited to two inputs can be carried out, the optimization effect is good, and an integrated circuit can have good comprehensive performance. As the area of the circuit is closely related to the number of mapping gates of the logic netlist, the simple logic netlist generally corresponds to a smaller circuit area, and the aim of optimizing the area of the circuit is fulfilled by simplifying the logic netlist.

The invention discloses a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input. The digital-to-analog converter interface circuit comprises an ESD protection circuit, a DEMUX multiplexer, an MUX multiplexer, an LVDS receiver, an inverter chain and a digital logic circuit. The output end of the ESD protection circuit is connected with the DEMUX demultiplexer; the digital logic circuit is used for generating a synchronous control signal according to an external mode switching signal and coordinating the working state of each module; the DEMUX demultiplexer distributes an input signal output by the ESD protection circuit to a corresponding signal processing path under the action of a control signal output by the digital logic circuit; the LVDS receiver receives the LVDS signal, converts the LVDS signal into a single-ended CMOS signal, and outputs the single-ended CMOS signal to the MUX multiplexer; the inverter chain is used for receiving a CMOS signal; and the MUX multiplexer outputs a control signal according to the digital logic circuit, so that one of the two paths of input signals is selected to be output to the DAC core circuit. According to the invention, LVDS / CMOS dual-mode input is efficiently supported in a single chip, and meanwhile, the requirements of high speed, low power consumption and time sequence consistency are met.

Reconfigurable digital logic circuits and methods of operation can be used to accelerate computation of Fast Fourier Transforms (FFT) and discrete Fourier transforms (DFT) for a range of sizes. In some embodiments, the same circuit can be reconfigurable to support FFT of any size 2k (for positive integer k) and DFT for of any size 2a*3b*5c for non-negative integers a, b, c.

The invention provides a series battery management system, a management method, a communication method and a medium, the system correspondingly configures a battery controller for each battery in series batteries, and the battery controllers are connected in series through communication links and communicate with an MCU controller; the MCU controller and the battery controller both work in a low-voltage power supply domain, a non-isolated interface is adopted for data transmission, and the method comprises the following steps: acquiring electric quantity information of each battery, and determining a working mode of the corresponding battery; the switch state in the battery controller is adjusted to realize battery access switching, and power supply of the level converter and the digital logic circuit is ensured; meanwhile, self-adaptive level conversion is carried out through a level converter according to the potential difference between the adjacent levels of battery controllers. All chips in the system work in a low-voltage power supply domain, the response speed of the system is high, the system is not limited by the number of series battery packs, and the system has good expansibility and is suitable for battery management in the fields of electric automobiles, energy storage and the like.

The application provides a method for generative heterogeneous logic optimization based on critical path partitioning. The method includes: converting a digital logic circuit into an And-Inverter Graph (AIG) format; partitioning the AIG using reinforcement learning based on critical path information of the circuit to obtain critical-path-aware partitions so as to reduce influence of critical path changes brought by the partitioning on timing performance; respectively and automatically exploring an optimized structure and synthesis flow suitable for each partition using the reinforcement learning method; selecting optimization operators for various structures using a reinforcement learning agent guided by area-delay metrics and optimizing each partition; and merging the optimized partitions in the AIG format. In the application, the digital logic circuit is partitioned based on critical paths, and reinforcement learning is used to explore and optimize structures and strategies based on area and delay.

The invention discloses a write-once locking circuit and a write-once locking method, and relates to the technical field of integrated circuit design and information security. The circuit comprises a data storage unit, a state locking unit and a logic control module. The logic control module provides an effective signal for the data storage unit to allow writing when the state signal indicates that the data storage unit has the writing permission and the external writing enable signal is effective, and simultaneously triggers the state locking unit to overturn to a state of forbidding the writing permission and keep the state; thereafter, the logic control module continuously blocks the provision of the valid write signal to the data storage unit based on the write prohibition state. On the premise of not increasing additional process steps and manufacturing cost, the standard digital logic circuit can be used for realizing data single-time writing and locking functions similar to OTP (One Time Programmable).

The invention discloses an OR gate, a NOR gate and a maximum gate circuit realized based on a three-valued memristor, and belongs to the technical field of digital logic circuit design, the three-valued memristor is used in a three-valued digital logic circuit, and the OR gate, the NOR gate and the maximum gate circuit are realized. The multi-valued digital logic circuit carries more information, the complexity degree between circuit connecting lines is lower, the area and power consumption of the logic circuit are effectively reduced, the operational capability of the circuit is higher, the structure is clear and simple, implementation is easy, and the multi-valued digital logic circuit can be used for application research in many fields such as multi-valued digital logic operation.

The present invention discloses a two-step high-speed ADC circuit based on a single-slope and level-coded TDC. The circuit is characterized by comprising a single-slope digital logic ADC circuit and a time-to-digital conversion TDC circuit. The output of the single-slope digital logic circuit and the output of the time-to-digital conversion TDC circuit are output through an accumulator as the analog-to-digital conversion result OUT of the entire circuit. The TDC employs a cyclic level coding scheme, automatically performing a carry function to the single-slope counting logic. Furthermore, the circuit is effectively compatible with digital correlated double sampling technology, subtracting two quantization results with non-ideal factors to obtain a more accurate quantization result.

A driver circuit of an image sensor is provided. The driver circuit includes: a row decoder that decodes an address indicating a target row of a pixel array and generates an operation instruction signal corresponding to the target row; a digital logic circuit including: a target row logic circuit that generates a pixel control signal based on the operation instruction signal; a power switch that is configured to connect a power supply voltage to the target row logic circuit during a first time period based on the operation instruction signal and to isolate the power supply voltage from the target row logic circuit during a second time period; an output circuit that is configured to output a default signal during the second time period; and a row driver that is configured to drive the target row based on the pixel control signal during the first time period and to drive the target row based on the default signal during the second time period.

The application relates to a signal folding amplifier based on a capacitive digital-to-analog converter and a signal chain circuit thereof, which comprises a low-noise amplifier, a threshold detection circuit, a digital logic circuit and a capacitive digital-to-analog converter feedback network; the threshold detection circuit generates downward, holding and upward signals according to the comparison result of the amplitude of the low-noise amplifier output signal and high and low threshold voltages; the digital logic circuit counts the downward, holding or upward signals by minus one, unchanged or plus one to obtain a counting signal; the capacitive digital-to-analog converter feedback network is used for feeding back the low-noise amplifier output signal to the input end and controlling the output signal folding counting signal folding steps, so that the low-noise amplifier output signal is not saturated. The beneficial effect is that the design is simple, the response speed is fast, the input and output amplitudes are large, the input signal amplitude is large, and the output signal is not saturated under the condition of large gain.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

The invention discloses a generative heterogeneous logic optimization method based on critical path partition. The method comprises the following steps of: firstly, converting a digital logic circuit into an AIG format, and partitioning an AIG by adopting reinforcement learning according to key path information of the circuit to obtain key path sensing partitions so as to reduce the influence of key path change caused by the partitions on time sequence performance; automatically exploring an optimized structure and an optimized comprehensive flow which are suitable for the partition for the partitioned circuit by using a reinforcement learning method, and selecting optimization operators of various structures to optimize the partition by using an area time delay as a guide by a reinforcement learning agent; and merging the optimized partitions in an AIG form. According to the method, a digital logic circuit is partitioned according to critical paths, reinforcement learning is used for exploring and optimizing a structure and a strategy by taking area time delay as guidance, the influence of partitioning on time sequence performance is reduced, a locally optimal solution is jumped out, a globally better solution is obtained, and meanwhile, manual intervention is not needed by automatic exploration, so that the labor cost in chip design can be reduced.

The utility model provides an unmanned aerial vehicle defect detection system. The unmanned aerial vehicle defect detection system comprises a visible light sensor, an infrared sensor, a speed sensor, a fusion unit and an image recognition unit, the visible light sensor, the infrared sensor and the speed sensor are all connected with the fusion unit; the fusion unit is connected with the image recognition unit. Through the arrangement of the speed sensor and the digital logic circuit influenced by the speed value, the visible light image and the infrared image can be accurately fused, a clear grey-scale map with more information is output for image recognition, and unmanned aerial vehicle defect detection is achieved with low cost.

This document relates to communication by backscattering of satellite signals. One example includes a satellite backscatter transmitter having a first antenna configured to receive a radio frequency satellite signal, a modulator configured to modulate the radio frequency satellite signal to obtain a modulated radio frequency satellite signal, a digital logic circuit configured to selectively control the modulator to encode information according to a communication scheme, and a second antenna configured to passively retransmit the modulated radio frequency satellite signal to a receiver.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

The present invention discloses a system and method for compensating the optical path power of a fiber optic gyroscope using a binary modulation depth method, and belongs to the technical field of fiber optic gyroscopes. The system includes a fiber optic gyroscope closed-loop system and a signal processing circuit. In the signal processing circuit, the photocurrent signal detected by the photodetector is amplified and converted into a digital signal. In the FPGA digital logic circuit, the signal is modulated using a binary modulation depth method, and the optical path power and angular velocity in the digital signal are demodulated using a digital operation method. The generated feedback signal is fed back to the current control port of the wide-spectrum light source and the phase modulator of the Y-waveguide integrated optical chip. The present invention uses a shared A / D detection channel for optical path power compensation and fiber optic gyroscope angular velocity detection, eliminating the need for an additional optical power detection module. Real-time compensation of the optical path power of the fiber optic gyroscope can be achieved without affecting the performance and size of the fiber optic gyroscope, thereby increasing the reliability and stability of the fiber optic gyroscope.

The dynamic memory array of a DRAM device is operated using at least two voltages. The first voltage, which is used to power the sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write), is the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The second voltage, which determines the voltage written to the capacitor of the DRAM cells (i.e., bitline voltage) is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage written to the capacitors of the DRAM array. This allows lower voltage swing digital logic to be used for a majority of the logic on the DRAM device while writing a larger voltage to the DRAM cells.

The invention provides a direct current offset correction circuit and method of a single current source. The direct current offset correction circuit comprises a numerical control multi-path current mirror circuit, a comparison circuit, an intermediate frequency link and a digital logic circuit, the numerical control multi-path current mirror circuit comprises a path of reference current source; the comparison circuit detects the in-phase output voltage and the inverted output voltage of the intermediate-frequency link; when the in-phase output voltage is greater than the inverted output voltage, the output voltage is sent to the digital logic circuit; the digital logic circuit controls the sign bit to be a high level according to the output voltage, so that the numerical control multi-path current mirror circuit injects current into the inverted input end, and the inverted output voltage is increased; when the in-phase output voltage is still greater than the inverted-phase output voltage, changing the size of the injected current by adopting a dichotomy according to the high level output by the comparison circuit until the in-phase output voltage is equal to the inverted-phase output voltage, and obtaining a corresponding code word; the circuit area is optimized, the current direction and size control is completed through one reference current source, the precision is not affected, and the control circuit is simplified.

The invention discloses a crane rotating speed monitoring system and a crane, the crane rotating speed monitoring system comprises a permanent magnet ratchet ring and a double-sensor assembly, the double-sensor assembly is installed on a winding drum and comprises a first magneto-dependent sensor and a second magneto-dependent sensor, and when the winding drum rotates, the first magneto-dependent sensor and the second magneto-dependent sensor are connected; the first magneto-dependent sensor and the second magneto-dependent sensor respectively output a first square wave signal and a second square wave signal with constant phase difference, so that the rotation direction of the winding drum is represented through the phase relationship between the first square wave signal and the second square wave signal; and the direction distinguishing module is used for generating a direction signal and a counting pulse signal based on pure digital logic circuit processing. Therefore, the crane rotating speed monitoring system realizes real-time judgment of forward and reverse rotation and quadruplicated frequency counting through orthogonal signal output of the permanent magnet ratchet ring and the double magneto-dependent sensors in combination with a pure hardware direction judgment module, and the position monitoring resolution is improved.

Sets of digital samples associated with received wireless signals are received, each of the sets of digital samples corresponding to a particular RF path. The sets of digital samples are provided to a plurality of pipelines, each of the plurality of pipelines including a plurality of stages, each of the plurality of stages including one or more digital logic circuits. Sets of interconnect data are generated by the plurality of pipelines based on the sets of digital samples, the sets of interconnect data including at least one accumulating value. The sets of interconnect data are passed between adjacent pipelines of the plurality of pipelines along a direction. A result is generated by a last pipeline of the plurality of pipelines based on the at least one accumulating value.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

The unmanned aerial vehicle ranging system provided by the embodiment of the utility model comprises a laser radar ranging unit, a visual ranging unit, a meteorological detection unit and a calculation unit, the calculation unit is a digital logic circuit; wherein the visual ranging unit is connected with the meteorological detection unit; the calculation unit comprises a weight selection circuit and a distance calculation circuit; the weight selection circuit is connected with the meteorological detection unit; the weight selection circuit, the laser radar ranging unit and the visual ranging unit are all connected with the distance calculation circuit. A simple digital logic circuit is arranged in the unmanned aerial vehicle to replace a complex calculation program, a high-power processor is not needed, the correspondingly configured power supply capacity can be correspondingly reduced, and the size of the unmanned aerial vehicle is effectively reduced.