117 results about "Digital logic circuits" patented technology

A system, method and apparatus for executing a bioinformatics analysis on genetic sequence data is provided. Particularly, a genomics analysis platform for executing a sequence analysis pipeline is provided. The genomics analysis platform includes one or more of a first integrated circuit, where each first integrated circuit forms a central processing unit (CPU) that is responsive to one or more software algorithms that are configured to instruct the CPU to perform a first set of genomic processing steps of the sequence analysis pipeline. Additionally, a second integrated circuit is also provided, where each second integrated circuit forming a field programmable gate array (FPGA), the FPGA being configured by firmware to arrange a set of hardwired digital logic circuits that are interconnected by a plurality of physical interconnects to perform a second set of genomic processing steps of the sequence analysis pipeline, the set of hardwired digital logic circuits of each FPGA being arranged as a set of processing engines to perform the second set of genomic processing steps. A shared memory is also provided.

Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.

The invention provides a method and device for optimizing the layout of a digital logic circuit and a storage medium, and the method comprises the steps: determining a first layout of the digital logic circuit, the first layout comprises a plurality of macro cells and a plurality of standard cells, determining channels formed between the adjacent macro cells, and optimizing the layout of the digital logic circuit based on an optimization target of the digital logic circuit, according to the positions of the standard unit and the channel, the target step length parameter of the standard unit is determined, the optimization target comprises at least one of a line length target, a density target and a time sequence target, and the standard unit is adjusted based on the target step length parameter so as to optimize the layout of the digital logic circuit. By means of the method, automatic layout optimization of the digital logic circuit can be achieved, the influence of a channel on layout optimization is reduced, and the performance of a chip is further improved.

The invention discloses a circuit area optimization method based on an AND XOR majority diagram, and relates to a digital logic circuit area optimization method. According to the method, an input integrated circuit is converted into an AIG netlist, then cutting and replacement are carried out in the AIG netlist according to AIG equivalent structures of XOR gate nodes and majority logic gate nodes, equivalent gate nodes are covered on the AIG netlist according to a cutting result, and the AIG netlist is finally converted into an AXMIG netlist through mapping. Area optimization of the AND gate not limited to two inputs can be carried out, the optimization effect is good, and an integrated circuit can have good comprehensive performance. As the area of the circuit is closely related to the number of mapping gates of the logic netlist, the simple logic netlist generally corresponds to a smaller circuit area, and the aim of optimizing the area of the circuit is fulfilled by simplifying the logic netlist.

The invention discloses a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input. The digital-to-analog converter interface circuit comprises an ESD protection circuit, a DEMUX multiplexer, an MUX multiplexer, an LVDS receiver, an inverter chain and a digital logic circuit. The output end of the ESD protection circuit is connected with the DEMUX demultiplexer; the digital logic circuit is used for generating a synchronous control signal according to an external mode switching signal and coordinating the working state of each module; the DEMUX demultiplexer distributes an input signal output by the ESD protection circuit to a corresponding signal processing path under the action of a control signal output by the digital logic circuit; the LVDS receiver receives the LVDS signal, converts the LVDS signal into a single-ended CMOS signal, and outputs the single-ended CMOS signal to the MUX multiplexer; the inverter chain is used for receiving a CMOS signal; and the MUX multiplexer outputs a control signal according to the digital logic circuit, so that one of the two paths of input signals is selected to be output to the DAC core circuit. According to the invention, LVDS / CMOS dual-mode input is efficiently supported in a single chip, and meanwhile, the requirements of high speed, low power consumption and time sequence consistency are met.

Reconfigurable digital logic circuits and methods of operation can be used to accelerate computation of Fast Fourier Transforms (FFT) and discrete Fourier transforms (DFT) for a range of sizes. In some embodiments, the same circuit can be reconfigurable to support FFT of any size 2k (for positive integer k) and DFT for of any size 2a*3b*5c for non-negative integers a, b, c.

The invention provides a series battery management system, a management method, a communication method and a medium, the system correspondingly configures a battery controller for each battery in series batteries, and the battery controllers are connected in series through communication links and communicate with an MCU controller; the MCU controller and the battery controller both work in a low-voltage power supply domain, a non-isolated interface is adopted for data transmission, and the method comprises the following steps: acquiring electric quantity information of each battery, and determining a working mode of the corresponding battery; the switch state in the battery controller is adjusted to realize battery access switching, and power supply of the level converter and the digital logic circuit is ensured; meanwhile, self-adaptive level conversion is carried out through a level converter according to the potential difference between the adjacent levels of battery controllers. All chips in the system work in a low-voltage power supply domain, the response speed of the system is high, the system is not limited by the number of series battery packs, and the system has good expansibility and is suitable for battery management in the fields of electric automobiles, energy storage and the like.

The application provides a method for generative heterogeneous logic optimization based on critical path partitioning. The method includes: converting a digital logic circuit into an And-Inverter Graph (AIG) format; partitioning the AIG using reinforcement learning based on critical path information of the circuit to obtain critical-path-aware partitions so as to reduce influence of critical path changes brought by the partitioning on timing performance; respectively and automatically exploring an optimized structure and synthesis flow suitable for each partition using the reinforcement learning method; selecting optimization operators for various structures using a reinforcement learning agent guided by area-delay metrics and optimizing each partition; and merging the optimized partitions in the AIG format. In the application, the digital logic circuit is partitioned based on critical paths, and reinforcement learning is used to explore and optimize structures and strategies based on area and delay.

The invention discloses a write-once locking circuit and a write-once locking method, and relates to the technical field of integrated circuit design and information security. The circuit comprises a data storage unit, a state locking unit and a logic control module. The logic control module provides an effective signal for the data storage unit to allow writing when the state signal indicates that the data storage unit has the writing permission and the external writing enable signal is effective, and simultaneously triggers the state locking unit to overturn to a state of forbidding the writing permission and keep the state; thereafter, the logic control module continuously blocks the provision of the valid write signal to the data storage unit based on the write prohibition state. On the premise of not increasing additional process steps and manufacturing cost, the standard digital logic circuit can be used for realizing data single-time writing and locking functions similar to OTP (One Time Programmable).

The invention discloses an OR gate, a NOR gate and a maximum gate circuit realized based on a three-valued memristor, and belongs to the technical field of digital logic circuit design, the three-valued memristor is used in a three-valued digital logic circuit, and the OR gate, the NOR gate and the maximum gate circuit are realized. The multi-valued digital logic circuit carries more information, the complexity degree between circuit connecting lines is lower, the area and power consumption of the logic circuit are effectively reduced, the operational capability of the circuit is higher, the structure is clear and simple, implementation is easy, and the multi-valued digital logic circuit can be used for application research in many fields such as multi-valued digital logic operation.

The present invention discloses a two-step high-speed ADC circuit based on a single-slope and level-coded TDC. The circuit is characterized by comprising a single-slope digital logic ADC circuit and a time-to-digital conversion TDC circuit. The output of the single-slope digital logic circuit and the output of the time-to-digital conversion TDC circuit are output through an accumulator as the analog-to-digital conversion result OUT of the entire circuit. The TDC employs a cyclic level coding scheme, automatically performing a carry function to the single-slope counting logic. Furthermore, the circuit is effectively compatible with digital correlated double sampling technology, subtracting two quantization results with non-ideal factors to obtain a more accurate quantization result.

The application relates to a signal folding amplifier based on a capacitive digital-to-analog converter and a signal chain circuit thereof, which comprises a low-noise amplifier, a threshold detection circuit, a digital logic circuit and a capacitive digital-to-analog converter feedback network; the threshold detection circuit generates downward, holding and upward signals according to the comparison result of the amplitude of the low-noise amplifier output signal and high and low threshold voltages; the digital logic circuit counts the downward, holding or upward signals by minus one, unchanged or plus one to obtain a counting signal; the capacitive digital-to-analog converter feedback network is used for feeding back the low-noise amplifier output signal to the input end and controlling the output signal folding counting signal folding steps, so that the low-noise amplifier output signal is not saturated. The beneficial effect is that the design is simple, the response speed is fast, the input and output amplitudes are large, the input signal amplitude is large, and the output signal is not saturated under the condition of large gain.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

This document relates to communication by backscattering of satellite signals. One example includes a satellite backscatter transmitter having a first antenna configured to receive a radio frequency satellite signal, a modulator configured to modulate the radio frequency satellite signal to obtain a modulated radio frequency satellite signal, a digital logic circuit configured to selectively control the modulator to encode information according to a communication scheme, and a second antenna configured to passively retransmit the modulated radio frequency satellite signal to a receiver.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

The present invention discloses a system and method for compensating the optical path power of a fiber optic gyroscope using a binary modulation depth method, and belongs to the technical field of fiber optic gyroscopes. The system includes a fiber optic gyroscope closed-loop system and a signal processing circuit. In the signal processing circuit, the photocurrent signal detected by the photodetector is amplified and converted into a digital signal. In the FPGA digital logic circuit, the signal is modulated using a binary modulation depth method, and the optical path power and angular velocity in the digital signal are demodulated using a digital operation method. The generated feedback signal is fed back to the current control port of the wide-spectrum light source and the phase modulator of the Y-waveguide integrated optical chip. The present invention uses a shared A / D detection channel for optical path power compensation and fiber optic gyroscope angular velocity detection, eliminating the need for an additional optical power detection module. Real-time compensation of the optical path power of the fiber optic gyroscope can be achieved without affecting the performance and size of the fiber optic gyroscope, thereby increasing the reliability and stability of the fiber optic gyroscope.

The dynamic memory array of a DRAM device is operated using at least two voltages. The first voltage, which is used to power the sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write), is the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The second voltage, which determines the voltage written to the capacitor of the DRAM cells (i.e., bitline voltage) is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage written to the capacitors of the DRAM array. This allows lower voltage swing digital logic to be used for a majority of the logic on the DRAM device while writing a larger voltage to the DRAM cells.

The invention provides a direct current offset correction circuit and method of a single current source. The direct current offset correction circuit comprises a numerical control multi-path current mirror circuit, a comparison circuit, an intermediate frequency link and a digital logic circuit, the numerical control multi-path current mirror circuit comprises a path of reference current source; the comparison circuit detects the in-phase output voltage and the inverted output voltage of the intermediate-frequency link; when the in-phase output voltage is greater than the inverted output voltage, the output voltage is sent to the digital logic circuit; the digital logic circuit controls the sign bit to be a high level according to the output voltage, so that the numerical control multi-path current mirror circuit injects current into the inverted input end, and the inverted output voltage is increased; when the in-phase output voltage is still greater than the inverted-phase output voltage, changing the size of the injected current by adopting a dichotomy according to the high level output by the comparison circuit until the in-phase output voltage is equal to the inverted-phase output voltage, and obtaining a corresponding code word; the circuit area is optimized, the current direction and size control is completed through one reference current source, the precision is not affected, and the control circuit is simplified.

The invention discloses a crane rotating speed monitoring system and a crane, the crane rotating speed monitoring system comprises a permanent magnet ratchet ring and a double-sensor assembly, the double-sensor assembly is installed on a winding drum and comprises a first magneto-dependent sensor and a second magneto-dependent sensor, and when the winding drum rotates, the first magneto-dependent sensor and the second magneto-dependent sensor are connected; the first magneto-dependent sensor and the second magneto-dependent sensor respectively output a first square wave signal and a second square wave signal with constant phase difference, so that the rotation direction of the winding drum is represented through the phase relationship between the first square wave signal and the second square wave signal; and the direction distinguishing module is used for generating a direction signal and a counting pulse signal based on pure digital logic circuit processing. Therefore, the crane rotating speed monitoring system realizes real-time judgment of forward and reverse rotation and quadruplicated frequency counting through orthogonal signal output of the permanent magnet ratchet ring and the double magneto-dependent sensors in combination with a pure hardware direction judgment module, and the position monitoring resolution is improved.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

The invention provides a six-input 4-bit successive approximation type quantizer with an embedded feed-forward coefficient, and relates to an analog integrated circuit. The quantizer comprises a capacitive digital-to-analog converter, a comparator and an asynchronous successive approximation digital logic circuit; the capacitive digital-to-analog converter is composed of a group of binary increasing capacitors. According to the quantizer, the operation of proportionally adding a feed-forward path and the output of each stage of integrator is embedded on a capacitance type digital-to-analog converter capacitor of a 4-bit successive approximation type analog-to-digital converter. During sampling, upper and lower polar plates of a capacitor of the capacitive digital-to-analog converter perform sampling operation at the same time. After sampling is completed, the upper and lower polar plates of the capacitor are disconnected with the six input sources. The lower electrode plates of the capacitors are connected to a common mode voltage VCM, at the moment, signals are input at the joint of the upper electrode plates of the capacitors and the input end of the comparator after proportional addition, the addition result is sent to asynchronous logic for dichotomy search, 4-bit digital codes are obtained in sequence, and therefore the quantization process is completed.

The invention belongs to the technical field of integrated circuits, and discloses a circuit of a PWM controller of a high-speed low-power-consumption current mode. The PWM controller circuit comprises a reference circuit, an error amplifier, a current mode comparator, a clock circuit, a protection circuit and a digital logic circuit module. And the control on the duty ratio is realized by detecting the external current, so that the control on the output power is realized, and the control on the output voltage is finally realized. According to the invention, the voltage in an application input range can be controlled to be 4-20V, the quiescent current is 30uA, and the working frequency is 1.5 MHz.

The invention relates to a chip system, a startup and shutdown manager, a power supply circuit and electronic equipment, and relates to the technical field of terminals. The chip system comprises a startup and shutdown manager, a power supply circuit and a data processing system, wherein the startup and shutdown manager comprises a digital logic circuit. The digital logic circuit is used for responding to the input of the device button and sending a first pulse signal to the power supply circuit through the enabling output end, and the first pulse signal is used for controlling the power supply circuit to supply power to the data processing system. In response to a constant electric signal received by the feedback controlled end from the feedback output end of the power supply circuit or the feedback output end of the data processing system, a first power supply signal is sent to the power supply circuit through the enabling output end, and the first power supply signal is used for controlling the power supply circuit to continuously supply power to the data processing system. Therefore, the cost can be reduced.

The present invention discloses a method and a system for efficiently simplifying digital logic circuits. The present invention performs multiple random simulations on the same digital logic circuit, and takes the nodes with the same simulation results each time as a candidate set; performs incremental simulations on the nodes in the candidate set to obtain an equivalent class set; screens out the nodes located at a high level and with constant simulation results, and obtains the values of the primary input nodes through SAT solving; uses the values of the primary input nodes to simulate the original digital logic circuit, filters out the nodes in the equivalent class set with different simulation result values, and further obtains an optimized equivalent class set; based on the optimized equivalent class set, uses a SAT solver to test all node pairs to simplify the original digital logic circuit. The present invention reduces the number of calls to the SAT solver through innovative incremental simulation, hierarchical optimization, and hybrid verification technologies, helps improve the chip design efficiency, reduces the amount of ineffective work and the number of design iterations, and thus shortens the chip design cycle.

In accordance with the described techniques, a device or system includes a digital logic circuit organized into multiple partitions, and a power gating circuit. Further, the digital logic circuit includes base logic representing the digital logic circuit before being modified by external logic of the system that is external to the digital logic circuit. The power gating circuit is configured to independently control power supplied to the multiple partitions of the digital logic circuit. As part of this, the power gating circuit initiates a power state transition to a power state in which an entirety of the base logic of the digital logic circuit is powered off.

The application relates to the technical field of integrated circuit signal detection, and provides a baud rate signal detection circuit and a CDR loop structure which are composed of two data samplers, one error sampler and a digital logic circuit, can provide better jitter performance compared with a traditional MMPD, do not need to depend on accurate reference level VRFE amplitude setting, and have relatively lower design difficulty compared with traditional designs. In addition, the signal detection circuit can also detect the frequency deviation between input data and a sampling clock, so that the baud rate CDR function with a wide frequency capture range can be realized by using only a single control loop without increasing additional clock and sampling circuits, external reference clocks are not needed, the difficulty of the performance and cost compromise mentioned above can be greatly reduced, and the overall design cost is greatly reduced.

A device includes an open-drain driver, a comparator, and digital logic circuitry. The open-drain driver is operable to pull down and release a reset voltage on a reset line in response to an open-drain enable signal. The comparator is operable to generate a comparison signal by comparing the reset voltage to an active threshold voltage. The digital logic circuitry is operable to test a connection to the reset line. The test includes asserting the open-drain enable signal to pull down the reset voltage on the reset line, asserting the open-drain enable signal to make the reset voltage unreferenced, and determining, in response to a change in the reset voltage relative to the active threshold voltage, that the connection is either good or failed.

The invention relates to a safety module used in civil and military aircraft, in which the control of power layers is carried out via a safety analysis algorithm on an internal programmable digital logic circuit, where the temperature, current, and voltage values of the hardware are monitored with a contactless and integrated sensor in order to detect situations of overheating, excessive power consumption, overvoltage, spark, and gas – smoke emission.

The application discloses a one-time fuse trimming circuit based on an SPI communication protocol and belongs to the field of electronic circuits, comprising an SPI communication module and a fuse burning and writing digital logic circuit; the SPI communication module comprises a normal mode and a fuse mode; the normal mode comprises data bits, control bits and redundant bits; the fuse mode comprises a fuse address bit, a fuse control bit, a fuse mode bit, a fuse flag bit and a fuse enable bit; the fuse burning and writing digital logic circuit comprises a FIFO unit, an interlocking unit, a rising edge trigger unit and a fuse burning and writing execution unit. The application reuses the general SPI communication protocol, can temporarily reuse the SPI channel to burn and write the fuse according to a special method, can burn and break the end flag fuse after burning and writing the fuse, permanently closes the burning and writing path, is safe and reliable, will not appear misoperation, and saves a large amount of interface resources.