15 results about "Digital logic circuits" patented technology

The application provides a method for generative heterogeneous logic optimization based on critical path partitioning. The method includes: converting a digital logic circuit into an And-Inverter Graph (AIG) format; partitioning the AIG using reinforcement learning based on critical path information of the circuit to obtain critical-path-aware partitions so as to reduce influence of critical path changes brought by the partitioning on timing performance; respectively and automatically exploring an optimized structure and synthesis flow suitable for each partition using the reinforcement learning method; selecting optimization operators for various structures using a reinforcement learning agent guided by area-delay metrics and optimizing each partition; and merging the optimized partitions in the AIG format. In the application, the digital logic circuit is partitioned based on critical paths, and reinforcement learning is used to explore and optimize structures and strategies based on area and delay.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

The application relates to the technical field of integrated circuit signal detection, and provides a baud rate signal detection circuit and a CDR loop structure which are composed of two data samplers, one error sampler and a digital logic circuit, can provide better jitter performance compared with a traditional MMPD, do not need to depend on accurate reference level VRFE amplitude setting, and have relatively lower design difficulty compared with traditional designs. In addition, the signal detection circuit can also detect the frequency deviation between input data and a sampling clock, so that the baud rate CDR function with a wide frequency capture range can be realized by using only a single control loop without increasing additional clock and sampling circuits, external reference clocks are not needed, the difficulty of the performance and cost compromise mentioned above can be greatly reduced, and the overall design cost is greatly reduced.

The invention relates to a safety module used in civil and military aircraft, in which the control of power layers is carried out via a safety analysis algorithm on an internal programmable digital logic circuit, where the temperature, current, and voltage values of the hardware are monitored with a contactless and integrated sensor in order to detect situations of overheating, excessive power consumption, overvoltage, spark, and gas – smoke emission.

The present invention discloses a method for fabricating a driver chip based on hybrid bonding and heterogeneous integration. First, a first wafer is provided, and multiple first chips, each containing a high-voltage analog driver circuit and / or a medium-voltage analog driver circuit, are fabricated on the first wafer using a first process node. Then, a second wafer is provided, and multiple second chips, each containing digital logic circuits and memory cells, are fabricated on the second wafer using a second process node. The first process node is a more mature process node than the second process node. Finally, the first and second wafers are bonded together using a wafer-level hybrid bonding process to form the driver chip, and electrical interconnects are formed at the bonding interface. This achieves an optimal combination of the high-voltage / medium-voltage driver portion and the logic / memory portion at different process nodes.

The application discloses a relaxation oscillator based on a switched capacitor array and a peak feedback structure and a stabilizing method, the oscillator comprising a reference source, a switched capacitor array, a peak voltage feedback module, a comparator and a digital logic circuit, the switched capacitor array comprising two symmetric charge-discharge branches, each branch having a main charging capacitor and a tracking holding capacitor, and the peak voltage feedback module being composed of an operational amplifier, a feedback capacitor and a sampling switch. In operation, the capacitor voltage of one branch charged alternately is compared with a dynamic threshold, and the peak voltage on the tracking holding capacitor of the other branch is sampled to the feedback module at the switching moment, the comparator threshold is dynamically adjusted through the integral action, and finally the capacitor peak voltage is locked to the fixed reference voltage, so that the influence of non-ideal factors such as comparator delay on the oscillation period is systematically offset. The application also adopts a chopping comparator to eliminate the offset. The architecture significantly improves the stability of the oscillation frequency to the power supply voltage and temperature, and helps to realize low phase noise, and is suitable for high-precision on-chip clock sources.

An adaptive following capacitive sensor chip circuit, comprising: a CDAC circuit connected to an external load capacitor, a sample and hold circuit and a digital logic circuit respectively, for tracking the external load capacitor to keep consistent with the size of the external load capacitor; a RDAC circuit connected to the digital logic circuit and a comparator circuit group respectively, for generating a reference value that can be automatically adjusted to adapt to different degrees of external triggering action; an input end of the sample and hold circuit is connected between the external load capacitor and the CDAC circuit, and an output end is connected to the comparator circuit group, for controlling the acquisition of the external load capacitor size according to the signal sent by the digital logic circuit to the CDAC circuit, and outputting it to the comparator circuit group for comparison and judgment; the digital logic circuit is connected to the comparator circuit group and the sample and hold circuit, for providing the sample and hold circuit with a control timing signal, and providing the CDAC circuit and the RDAC circuit with an excitation voltage signal according to the output result of the comparator circuit group.

This invention provides a configurable hardware architecture and bit manipulation method based on Banyan networks, belonging to the fields of digital logic circuits and high-performance computing technology. The invention aims to solve the problems of high hardware overhead, high power consumption, and long latency caused by the need for separate hardware modules—a Banyan network and a barrel shifter—to achieve combined bit-gathering and cyclic shifting operations in existing technologies. The architecture of this invention includes a Banyan network switching module and a control signal generation module. The control signal generation module generates an offset prefix count by superimposing the cyclic shift amount *r* with the original prefix count based on a bit mask, and uses this count to generate control signals for each stage of the Banyan network via an LROTC circuit. Through innovative modifications to the Banyan network control logic, this invention enables a single network to simultaneously perform both advanced bit operations, bit-gathering and cyclic shifting. This invention offers significant advantages such as hardware resource savings, reduced power consumption, improved performance, flexible design, and easy expansion, and can be widely applied in processor design, cryptographic acceleration, digital signal processing, and other fields.

Circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

The invention provides a hybrid architecture analog-to-digital converter and a control method thereof. The analog-to-digital converter comprises an M-bit SAR ADC, a loop filter, a multiplexing control circuit and a digital logic circuit, an input signal is input into the loop filter to output a signal to be quantized; the multiplexing control circuit drives the SAR ADC to perform N-bit conversion on the to-be-quantized signal based on the first sampling signal and the first quantized signal to obtain an N-bit first quantized result; the multiplexing control circuit drives the SAR ADC to perform M-bit conversion on the input signal based on the second sampling signal and the second quantization signal to obtain an M-bit second quantization result; the digital logic circuit outputs an M-bit digital output result according to the first quantization result and the second quantization result. Structural multiplexing of the SAR ADC is achieved through the multiplexing control circuit, additional circuit design is not needed, the problem that the circuit occupies the area is effectively solved, and the overall power consumption condition is reduced.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

Abstract A system, method and apparatus for executing a bioinformatics analysis on genetic sequence data is provided. Particularly, a genomics analysis platform for executing a sequence analysis pipeline is provided. The genomics analysis platform includes one or more of a first integrated circuit, where each first integrated circuit forms a central processing unit (CPU) that is responsive to one or more software algorithms that are configured to instruct the CPU to perform a first set of genomic processing steps of the sequence analysis pipeline. Additionally, a second integrated circuit is also provided, where each second integrated circuit forming a field programmable gate array (FPGA), the FPGA being configured by firmware to arrange a set of hardwired digital logic circuits that are interconnected by a plurality of physical interconnects to perform a second set of genomic processing steps of the sequence analysis pipeline, the set of hardwired digital logic circuits of each FPGA being arranged as a set of processing engines to perform the second set of genomic processing steps. A shared memory is also provided. Abstract A system, method and apparatus for executing a bioinformatics analysis on genetic sequence data is provided. Particularly, a genomics analysis platform for executing a sequence analysis pipeline is provided. The genomics analysis platform includes one or more of a first integrated circuit, where each first integrated circuit forms a central processing unit (CPU) that is responsive to one or more software algorithms that are configured to instruct the CPU to perform a first set of genomic processing steps of the sequence analysis pipeline. Additionally, a second integrated circuit is also provided, where each second integrated circuit forming a field programmable gate array (FPGA), the FPGA being configured by firmware to arrange a set of hardwired digital logic circuits that are interconnected by a plurality of physical interconnects to perform a second set of genomic processing steps of the sequence analysis pipeline, the set of hardwired digital logic circuits of each FPGA being arranged as a set of processing engines to perform the second set of genomic processing steps. A shared memory is also provided. 20 24 20 51 08 25 J ul 2 02 4 2 0 2 4 2 0 5 1 0 8 2 5 J u l 2 0 2 4

Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.

The application discloses a kind of millimeter wave phase-locked loop, including by sub-sampling phase detector, voltage-controlled oscillator, proportional path unit, voltage comparator and integral path unit constitute feedback loop phase-locked loop, according to frequency control word and phase error signal gain control signal, first control word, second control word and the digital logic circuit of selection signal, according to reference signal, gain control signal and the digital time converter of first control word generation delay signal, according to delay signal and the auxiliary digital time converter of second control word duty cycle error compensation, generation digital output signal, according to digital output signal clock generation circuit generates a plurality of sampling clock signals, sub-sampling phase detector according to a plurality of sampling clock signals and the output signal of rising edge sampling and falling edge sampling of voltage-controlled oscillator according to selection signal.The embodiment of the application realizes extremely low jitter and in-band decimal spur, occupies extremely small area, can be widely applied in electronic circuit technical field.

The application provides a linearity optimization device and method of a successive approximation register analog-to-digital converter. The device provided by the application comprises a first analog-to-digital converter, a first digital-to-analog converter, a summation module, a second analog-to-digital converter, a second digital-to-analog converter and a digital logic circuit; the first analog-to-digital converter is used for converting a first analog voltage signal and a second analog voltage signal into a code value of a first preset bit; the first digital-to-analog converter is used for converting the code value into a second analog voltage signal; the summation module is used for obtaining a residual voltage signal according to the first analog voltage signal and the second analog voltage signal; the second analog-to-digital converter is used for converting the residual voltage signal into a code value of a second preset bit; the second digital-to-analog converter is used for obtaining the second analog voltage signal by taking out a code value of a third preset high bit; and the digital logic circuit is used for obtaining a digital signal according to the code value. The device provided by the application can improve the linearity of the output code value of a segmented SAR-ADC.