63 results about "Digital logic circuits" patented technology

The invention discloses a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input. The digital-to-analog converter interface circuit comprises an ESD protection circuit, a DEMUX multiplexer, an MUX multiplexer, an LVDS receiver, an inverter chain and a digital logic circuit. The output end of the ESD protection circuit is connected with the DEMUX demultiplexer; the digital logic circuit is used for generating a synchronous control signal according to an external mode switching signal and coordinating the working state of each module; the DEMUX demultiplexer distributes an input signal output by the ESD protection circuit to a corresponding signal processing path under the action of a control signal output by the digital logic circuit; the LVDS receiver receives the LVDS signal, converts the LVDS signal into a single-ended CMOS signal, and outputs the single-ended CMOS signal to the MUX multiplexer; the inverter chain is used for receiving a CMOS signal; and the MUX multiplexer outputs a control signal according to the digital logic circuit, so that one of the two paths of input signals is selected to be output to the DAC core circuit. According to the invention, LVDS / CMOS dual-mode input is efficiently supported in a single chip, and meanwhile, the requirements of high speed, low power consumption and time sequence consistency are met.

Reconfigurable digital logic circuits and methods of operation can be used to accelerate computation of Fast Fourier Transforms (FFT) and discrete Fourier transforms (DFT) for a range of sizes. In some embodiments, the same circuit can be reconfigurable to support FFT of any size 2k (for positive integer k) and DFT for of any size 2a*3b*5c for non-negative integers a, b, c.

The application provides a method for generative heterogeneous logic optimization based on critical path partitioning. The method includes: converting a digital logic circuit into an And-Inverter Graph (AIG) format; partitioning the AIG using reinforcement learning based on critical path information of the circuit to obtain critical-path-aware partitions so as to reduce influence of critical path changes brought by the partitioning on timing performance; respectively and automatically exploring an optimized structure and synthesis flow suitable for each partition using the reinforcement learning method; selecting optimization operators for various structures using a reinforcement learning agent guided by area-delay metrics and optimizing each partition; and merging the optimized partitions in the AIG format. In the application, the digital logic circuit is partitioned based on critical paths, and reinforcement learning is used to explore and optimize structures and strategies based on area and delay.

The invention discloses a write-once locking circuit and a write-once locking method, and relates to the technical field of integrated circuit design and information security. The circuit comprises a data storage unit, a state locking unit and a logic control module. The logic control module provides an effective signal for the data storage unit to allow writing when the state signal indicates that the data storage unit has the writing permission and the external writing enable signal is effective, and simultaneously triggers the state locking unit to overturn to a state of forbidding the writing permission and keep the state; thereafter, the logic control module continuously blocks the provision of the valid write signal to the data storage unit based on the write prohibition state. On the premise of not increasing additional process steps and manufacturing cost, the standard digital logic circuit can be used for realizing data single-time writing and locking functions similar to OTP (One Time Programmable).

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

The invention discloses a crane rotating speed monitoring system and a crane, the crane rotating speed monitoring system comprises a permanent magnet ratchet ring and a double-sensor assembly, the double-sensor assembly is installed on a winding drum and comprises a first magneto-dependent sensor and a second magneto-dependent sensor, and when the winding drum rotates, the first magneto-dependent sensor and the second magneto-dependent sensor are connected; the first magneto-dependent sensor and the second magneto-dependent sensor respectively output a first square wave signal and a second square wave signal with constant phase difference, so that the rotation direction of the winding drum is represented through the phase relationship between the first square wave signal and the second square wave signal; and the direction distinguishing module is used for generating a direction signal and a counting pulse signal based on pure digital logic circuit processing. Therefore, the crane rotating speed monitoring system realizes real-time judgment of forward and reverse rotation and quadruplicated frequency counting through orthogonal signal output of the permanent magnet ratchet ring and the double magneto-dependent sensors in combination with a pure hardware direction judgment module, and the position monitoring resolution is improved.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

In accordance with the described techniques, a device or system includes a digital logic circuit organized into multiple partitions, and a power gating circuit. Further, the digital logic circuit includes base logic representing the digital logic circuit before being modified by external logic of the system that is external to the digital logic circuit. The power gating circuit is configured to independently control power supplied to the multiple partitions of the digital logic circuit. As part of this, the power gating circuit initiates a power state transition to a power state in which an entirety of the base logic of the digital logic circuit is powered off.

The application relates to the technical field of integrated circuit signal detection, and provides a baud rate signal detection circuit and a CDR loop structure which are composed of two data samplers, one error sampler and a digital logic circuit, can provide better jitter performance compared with a traditional MMPD, do not need to depend on accurate reference level VRFE amplitude setting, and have relatively lower design difficulty compared with traditional designs. In addition, the signal detection circuit can also detect the frequency deviation between input data and a sampling clock, so that the baud rate CDR function with a wide frequency capture range can be realized by using only a single control loop without increasing additional clock and sampling circuits, external reference clocks are not needed, the difficulty of the performance and cost compromise mentioned above can be greatly reduced, and the overall design cost is greatly reduced.

The invention relates to a safety module used in civil and military aircraft, in which the control of power layers is carried out via a safety analysis algorithm on an internal programmable digital logic circuit, where the temperature, current, and voltage values of the hardware are monitored with a contactless and integrated sensor in order to detect situations of overheating, excessive power consumption, overvoltage, spark, and gas – smoke emission.

The application discloses a one-time fuse trimming circuit based on an SPI communication protocol and belongs to the field of electronic circuits, comprising an SPI communication module and a fuse burning and writing digital logic circuit; the SPI communication module comprises a normal mode and a fuse mode; the normal mode comprises data bits, control bits and redundant bits; the fuse mode comprises a fuse address bit, a fuse control bit, a fuse mode bit, a fuse flag bit and a fuse enable bit; the fuse burning and writing digital logic circuit comprises a FIFO unit, an interlocking unit, a rising edge trigger unit and a fuse burning and writing execution unit. The application reuses the general SPI communication protocol, can temporarily reuse the SPI channel to burn and write the fuse according to a special method, can burn and break the end flag fuse after burning and writing the fuse, permanently closes the burning and writing path, is safe and reliable, will not appear misoperation, and saves a large amount of interface resources.

The dynamic memory array of a DRAM device operates using at least two voltages. A first voltage is the operating (i.e., switching) voltage of most of the digital logic circuitry of the DRAM device, which is used to power sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write). A second voltage is greater than the operating (i.e., switching) voltage of most of the digital logic circuitry of the DRAM device, which determines the voltage written to the capacitor of a DRAM cell (i.e., the bit line voltage). The digital logic circuitry operates using a supply voltage, which is lower than the voltage written to the capacitor of the DRAM array. This allows lower voltage swing digital logic to be used for most of the logic on the DRAM device, while a larger voltage is written to the DRAM cell.

The present invention discloses a method for fabricating a driver chip based on hybrid bonding and heterogeneous integration. First, a first wafer is provided, and multiple first chips, each containing a high-voltage analog driver circuit and / or a medium-voltage analog driver circuit, are fabricated on the first wafer using a first process node. Then, a second wafer is provided, and multiple second chips, each containing digital logic circuits and memory cells, are fabricated on the second wafer using a second process node. The first process node is a more mature process node than the second process node. Finally, the first and second wafers are bonded together using a wafer-level hybrid bonding process to form the driver chip, and electrical interconnects are formed at the bonding interface. This achieves an optimal combination of the high-voltage / medium-voltage driver portion and the logic / memory portion at different process nodes.

The application discloses a relaxation oscillator based on a switched capacitor array and a peak feedback structure and a stabilizing method, the oscillator comprising a reference source, a switched capacitor array, a peak voltage feedback module, a comparator and a digital logic circuit, the switched capacitor array comprising two symmetric charge-discharge branches, each branch having a main charging capacitor and a tracking holding capacitor, and the peak voltage feedback module being composed of an operational amplifier, a feedback capacitor and a sampling switch. In operation, the capacitor voltage of one branch charged alternately is compared with a dynamic threshold, and the peak voltage on the tracking holding capacitor of the other branch is sampled to the feedback module at the switching moment, the comparator threshold is dynamically adjusted through the integral action, and finally the capacitor peak voltage is locked to the fixed reference voltage, so that the influence of non-ideal factors such as comparator delay on the oscillation period is systematically offset. The application also adopts a chopping comparator to eliminate the offset. The architecture significantly improves the stability of the oscillation frequency to the power supply voltage and temperature, and helps to realize low phase noise, and is suitable for high-precision on-chip clock sources.

The invention discloses a low-power-consumption remote wake-up circuit of a CAN FD transceiver. The low-power-consumption remote wake-up circuit comprises a comparator, a filtering time detection module and a wake-up circuit module. The comparator is used for comparing the level of the CANH and the level of the CANL, when the CANH is larger than the CANL, a high level is output and marked as a dominant state, and when the CANH is smaller than the CANL, a low level is output and marked as an implicit state. The filtering time detection module is composed of a phase inverter and a capacitor; the wake-up circuit module is composed of a digital logic circuit so as to achieve the function of multi-filtering dominant wake-up. When the CAN FD transceiver enters a low-power-consumption mode, the CAN FD transceiver receives CANH and CANL signals, the comparator compares the levels of the CANH and CANL signals and outputs the signals to the filtering time detection module, and the signals with dominant or implicit signal pulse width time smaller than tFilter are filtered out; through the wake-up circuit module, when an input signal satisfies an ''explicit-implicit-explicit'' signal sequence, the signal received by the CAN FD transceiver is output, and the low-power-consumption mode is not quitted, so that remote wake-up of the CAN FD transceiver is realized.

An adaptive following capacitive sensor chip circuit, comprising: a CDAC circuit connected to an external load capacitor, a sample and hold circuit and a digital logic circuit respectively, for tracking the external load capacitor to keep consistent with the size of the external load capacitor; a RDAC circuit connected to the digital logic circuit and a comparator circuit group respectively, for generating a reference value that can be automatically adjusted to adapt to different degrees of external triggering action; an input end of the sample and hold circuit is connected between the external load capacitor and the CDAC circuit, and an output end is connected to the comparator circuit group, for controlling the acquisition of the external load capacitor size according to the signal sent by the digital logic circuit to the CDAC circuit, and outputting it to the comparator circuit group for comparison and judgment; the digital logic circuit is connected to the comparator circuit group and the sample and hold circuit, for providing the sample and hold circuit with a control timing signal, and providing the CDAC circuit and the RDAC circuit with an excitation voltage signal according to the output result of the comparator circuit group.

In some examples, a circuit includes a first transistor (312), a second transistor (314), a first resistor (318), and a digital logic circuit (106). The first transistor has a control terminal and first and second terminals. The second transistor has a control terminal and first and second terminals, the first terminal of the second transistor coupled to the second terminal of the first transistor. The first resistor has first and second terminals, the first terminal of the first resistor coupled to the control terminal of the second transistor, and the second terminal of the first resistor coupled to the first terminal of the second transistor. The digital logic circuit has an output terminal and first and second input terminals, the output terminal of the digital logic circuit coupled to the control terminal of the second transistor, the first input terminal of the digital logic circuit coupled to a data transmit input terminal (TXD) of the circuit, and the second input terminal of the digital logic circuit coupled to a data receive output terminal (RXD) of the circuit.

The invention provides an inrush current limiting system supporting a full PD type. The system comprises a comparison delay circuit which is configured to generate a delay signal when a system state represented by a load voltage is changed from current limiting to inrush current limiting; an RS latch configured to output 1 or 0 for characterizing a signal type according to a signal input by the comparison delay circuit; a current sampling resistor configured to obtain a sampling current in the circuit loop; the surge current detection circuit is configured to input a corresponding limit threshold value into the positive end of the comparator according to the type of the signal output by the RS latch and input a sampling current into the negative end of the comparator; the comparator is configured to perform comparison according to a limit threshold and the sampling current and generate a corresponding driving signal; the driving signal is used for controlling the conduction condition of the hot plug transistor together with the digital logic circuit. According to the system, the problem that an existing surge current limiting circuit lacks compatibility is solved.

The application provides a successive approximation analog-digital converter and a conversion method thereof, the analog-digital converter comprising: a sequentially connected capacitor switch array, a comparator and a digital logic circuit; the capacitor switch array accepts an input analog signal, samples and converts the analog signal, and outputs a converted signal to the comparator for comparison; the comparator compares the converted signal, and outputs a comparison result to the digital logic circuit; the digital logic circuit outputs a feedback control signal to the capacitor switch array according to the comparison result, and outputs a digital signal, wherein the number of bits of the digital signal is N, and N is a positive integer; and the switches in the capacitor switch array are switched according to the feedback control signal to open and close. N The application can be applied to analog signals with common-mode voltage, and has simple structure and is easy to implement.

The application discloses a kind of based on deep learning's efficient simplified digital logic circuit method, system, electronic equipment and storage medium, comprising: constructing logic synthesis dataset, the logic synthesis dataset includes training set and test set, input data in the logic synthesis dataset is the circuit of RTL verilog description;Logic synthesis environment is constructed to input data is preprocessed, and efficient simplified digital logic circuit model based on deep learning is constructed;Efficient simplified digital logic circuit model based on deep learning is trained using the circuit of preprocessed training set, until efficient simplified digital logic circuit model converges;Using the efficient simplified digital logic circuit model based on deep learning that is trained, and logic optimization is carried out on test set, to test the logic optimization capability of efficient simplified digital logic circuit model.The application can efficiently optimize circuit, and its effect is better than the method of traditional node-by-node application single optimization algorithm.

The invention discloses a single-chip orthogonal pulse frequency division output method and system and a storage medium, and relates to the technical field of main shaft servo drivers, and the method comprises the steps: generating a high-frequency reference clock signal of a preset frequency through a timer module integrated on an MCU chip; based on the control demand information of the spindle servo driver, performing integer frequency division processing on the high-frequency reference clock signal by adopting a hardware frequency divider to obtain a pulse signal of a target frequency; performing phase discrimination processing on the pulse signal after frequency division through a built-in digital logic circuit of the MCU chip to generate an orthogonal pulse pair with a phase difference of 90 degrees; and performing pulse width modulation optimization on the duty ratio of the orthogonal pulse pair by using a PWM (Pulse Width Modulation) module to obtain a final orthogonal pulse pair, and outputting the final orthogonal pulse pair based on preset interruption priority scheduling information. The system manufacturing cost of the main shaft servo driver can be reduced, and the high-precision frequency division pulse output requirement can be met.

The invention relates to a precision reconfigurable high-speed time domain analog-to-digital converter, which comprises a voltage-time converter used for converting a received input voltage signal into a time pulse signal so as to transmit the time pulse signal to a reconfigurable pipeline time-to-digital converter, and outputting a one-bit digital code to a digital logic circuit at the same time; the reconfigurable pipeline time-to-digital converter comprises n stages of pipelines, and the total effective stage number of the n stages of pipelines is controlled by a first configuration signal. The quantization precision of each level of assembly line is independently configured between 1.5 bits and 2 bits, and the n levels of assembly lines work in parallel in an odd-even assembly line level alternating mode; each stage of assembly line is quantized and generates a current stage of digital code, and the quantized residual time quantity is amplified as output and provided for the next stage of assembly line; and the digital logic circuit sums all the received digital codes into M-bit effective digital codes according to weights. The device can adapt to various high-speed application scenes with different precision requirements.

The invention discloses an oscillator circuit without a comparator and reference voltage, which belongs to the field of integrated circuits and comprises a current-limiting resistor R, integrating capacitors C1 and C2, P-type charging and discharging switch tubes PM1 to PM3, N-type charging and discharging switch tubes NM1 to NM3, digital logic circuits INV1 to INV3, a NOR gate NOR1, a NAND gate NAND1 and a buffer BUF1. According to the invention, the structure is simple, and stable oscillation can be realized only by a small number of basic components; dependence on a comparator or a high-precision reference voltage source in a traditional scheme is abandoned, system power consumption is effectively reduced, and meanwhile the chip area is remarkably reduced. By adjusting resistance and capacitance parameters, the frequency and the duty ratio of the output square wave can be flexibly adjusted, and the wide application prospect is achieved.

The application provides a method, device and storage medium for optimizing a digital logic circuit layout, comprising the following steps: determining a first layout of the digital logic circuit, wherein the first layout comprises a plurality of macro cells and a plurality of standard cells; determining a channel formed between adjacent macro cells; determining a target step parameter of the standard cell according to a position of the standard cell and the channel based on an optimization target of the digital logic circuit, wherein the optimization target comprises at least one of a line length target, a density target and a timing target; and adjusting the standard cell based on the target step parameter to optimize the layout of the digital logic circuit. The method provided by the application can realize automatic layout optimization of the digital logic circuit, reduce the influence of the channel on the layout optimization, and further improve the performance of the chip.

The invention discloses a method and system for efficiently simplifying a digital logic circuit based on deep learning, electronic equipment and a storage medium, and the method comprises the steps: constructing a logic comprehensive data set which comprises a training set and a test set, and the input data in the logic comprehensive data set is a circuit described by RTL verilog; constructing a logic comprehensive environment to pre-process input data, and constructing an efficient simplified digital logic circuit model based on deep learning; training an efficient simplified digital logic circuit model based on deep learning by using a circuit of the preprocessed training set until the efficient simplified digital logic circuit model converges; and performing logic optimization on the test set by using the trained efficient simplified digital logic circuit model based on deep learning so as to test the logic optimization capability of the efficient simplified digital logic circuit model. According to the method, the circuit can be efficiently optimized, and the effect of the method is better than that of a traditional method of applying a single optimization algorithm node by node.

A self-adaptive following capacitive sensor chip circuit comprises a CDAC circuit which is respectively connected to an external load capacitor, a sampling hold circuit and a digital logic circuit and is used for tracking the external load capacitor so as to keep the capacitance value of the external load capacitor consistent with the capacitance value of the external load capacitor; the RDAC circuit is respectively connected to the digital logic circuit and the comparator circuit group and is used for generating a reference value capable of being automatically adjusted so as to adapt to external triggering actions of different degrees; the input end of the sampling hold circuit is connected between an external load capacitor and the CDAC circuit, the output end of the sampling hold circuit is connected to the comparator circuit group, and the sampling hold circuit is used for controlling and collecting an electric signal of the external load capacitor according to a signal sent to the CDAC circuit by the digital logic circuit and outputting the electric signal to the comparator circuit group for comparison and judgment; and the digital logic circuit is connected to the comparator circuit group and the sampling and holding circuit and is used for providing a control sequence signal for the sampling and holding circuit and providing an excitation voltage signal for the CDAC circuit and the RDAC circuit according to an output result of the comparator circuit group.

Embodiments of a microelectronic assembly comprise a plurality of transceiver modules, each transceiver module including a first antenna; a printed circuit board (PCB); and a reflector module coupled to the PCB and separated from the plurality of transceiver modules by a space. The reflector module comprises: a substrate having a first side and an opposing second side, the first side being proximate to the plurality of transceiver modules, an antenna-array on the first side of the substrate, the antenna-array including a plurality of second antennas; a first integrated circuit (IC) die on the second side of the substrate; and a second IC die on the second side of the substrate. The first IC die comprises radio frequency (RF) switches configured to operate at electromagnetic frequencies between 20 kHz and 1 THz, and the second IC die comprises memory cell arrays and digital logic circuits.

A battery management system and a battery management procedure. The battery management system incorporates an application-specific integrated circuit. The application-specific integrated circuit comprises a first interface circuit, a second interface circuit, a third interface circuit, and a digital logic circuit. The first interface circuit is configured to acquire state parameter information of a cell in a battery module. The second interface circuit is configured to acquire state parameter information of a battery pack. The third interface circuit is configured to connect to a processor chip of the battery management system. The digital logic circuit is configured to send the cell state parameter information and the battery pack state parameter information to the processor chip.

Embodiments of a system, method and apparatus are described for reducing power consumption of a battery-powered electronic device. A hardware polling peripheral operates in conjunction with a CPU within the batten -powered electronic device. When the CPU enters a quiescent state in order to save power, the hardware polling peripheral begins the polling cycle that polls one or more I / O pins of the hardware polling peripheral to detect a change in state. Polling is controlled by hardware registers and digital logic circuits without the use of firmware. When the hardware polling peripheral determines that an I / O pin has changed state, it wakes the CPU from the quiescent state via an interrupt.

A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store / retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.