90 results about "Digital logic circuits" patented technology

The invention provides a method and device for optimizing the layout of a digital logic circuit and a storage medium, and the method comprises the steps: determining a first layout of the digital logic circuit, the first layout comprises a plurality of macro cells and a plurality of standard cells, determining channels formed between the adjacent macro cells, and optimizing the layout of the digital logic circuit based on an optimization target of the digital logic circuit, according to the positions of the standard unit and the channel, the target step length parameter of the standard unit is determined, the optimization target comprises at least one of a line length target, a density target and a time sequence target, and the standard unit is adjusted based on the target step length parameter so as to optimize the layout of the digital logic circuit. By means of the method, automatic layout optimization of the digital logic circuit can be achieved, the influence of a channel on layout optimization is reduced, and the performance of a chip is further improved.

The invention discloses a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input. The digital-to-analog converter interface circuit comprises an ESD protection circuit, a DEMUX multiplexer, an MUX multiplexer, an LVDS receiver, an inverter chain and a digital logic circuit. The output end of the ESD protection circuit is connected with the DEMUX demultiplexer; the digital logic circuit is used for generating a synchronous control signal according to an external mode switching signal and coordinating the working state of each module; the DEMUX demultiplexer distributes an input signal output by the ESD protection circuit to a corresponding signal processing path under the action of a control signal output by the digital logic circuit; the LVDS receiver receives the LVDS signal, converts the LVDS signal into a single-ended CMOS signal, and outputs the single-ended CMOS signal to the MUX multiplexer; the inverter chain is used for receiving a CMOS signal; and the MUX multiplexer outputs a control signal according to the digital logic circuit, so that one of the two paths of input signals is selected to be output to the DAC core circuit. According to the invention, LVDS / CMOS dual-mode input is efficiently supported in a single chip, and meanwhile, the requirements of high speed, low power consumption and time sequence consistency are met.

Reconfigurable digital logic circuits and methods of operation can be used to accelerate computation of Fast Fourier Transforms (FFT) and discrete Fourier transforms (DFT) for a range of sizes. In some embodiments, the same circuit can be reconfigurable to support FFT of any size 2k (for positive integer k) and DFT for of any size 2a*3b*5c for non-negative integers a, b, c.

The invention provides a series battery management system, a management method, a communication method and a medium, the system correspondingly configures a battery controller for each battery in series batteries, and the battery controllers are connected in series through communication links and communicate with an MCU controller; the MCU controller and the battery controller both work in a low-voltage power supply domain, a non-isolated interface is adopted for data transmission, and the method comprises the following steps: acquiring electric quantity information of each battery, and determining a working mode of the corresponding battery; the switch state in the battery controller is adjusted to realize battery access switching, and power supply of the level converter and the digital logic circuit is ensured; meanwhile, self-adaptive level conversion is carried out through a level converter according to the potential difference between the adjacent levels of battery controllers. All chips in the system work in a low-voltage power supply domain, the response speed of the system is high, the system is not limited by the number of series battery packs, and the system has good expansibility and is suitable for battery management in the fields of electric automobiles, energy storage and the like.

The application provides a method for generative heterogeneous logic optimization based on critical path partitioning. The method includes: converting a digital logic circuit into an And-Inverter Graph (AIG) format; partitioning the AIG using reinforcement learning based on critical path information of the circuit to obtain critical-path-aware partitions so as to reduce influence of critical path changes brought by the partitioning on timing performance; respectively and automatically exploring an optimized structure and synthesis flow suitable for each partition using the reinforcement learning method; selecting optimization operators for various structures using a reinforcement learning agent guided by area-delay metrics and optimizing each partition; and merging the optimized partitions in the AIG format. In the application, the digital logic circuit is partitioned based on critical paths, and reinforcement learning is used to explore and optimize structures and strategies based on area and delay.

The invention discloses a write-once locking circuit and a write-once locking method, and relates to the technical field of integrated circuit design and information security. The circuit comprises a data storage unit, a state locking unit and a logic control module. The logic control module provides an effective signal for the data storage unit to allow writing when the state signal indicates that the data storage unit has the writing permission and the external writing enable signal is effective, and simultaneously triggers the state locking unit to overturn to a state of forbidding the writing permission and keep the state; thereafter, the logic control module continuously blocks the provision of the valid write signal to the data storage unit based on the write prohibition state. On the premise of not increasing additional process steps and manufacturing cost, the standard digital logic circuit can be used for realizing data single-time writing and locking functions similar to OTP (One Time Programmable).

The present invention discloses a two-step high-speed ADC circuit based on a single-slope and level-coded TDC. The circuit is characterized by comprising a single-slope digital logic ADC circuit and a time-to-digital conversion TDC circuit. The output of the single-slope digital logic circuit and the output of the time-to-digital conversion TDC circuit are output through an accumulator as the analog-to-digital conversion result OUT of the entire circuit. The TDC employs a cyclic level coding scheme, automatically performing a carry function to the single-slope counting logic. Furthermore, the circuit is effectively compatible with digital correlated double sampling technology, subtracting two quantization results with non-ideal factors to obtain a more accurate quantization result.

The application relates to a signal folding amplifier based on a capacitive digital-to-analog converter and a signal chain circuit thereof, which comprises a low-noise amplifier, a threshold detection circuit, a digital logic circuit and a capacitive digital-to-analog converter feedback network; the threshold detection circuit generates downward, holding and upward signals according to the comparison result of the amplitude of the low-noise amplifier output signal and high and low threshold voltages; the digital logic circuit counts the downward, holding or upward signals by minus one, unchanged or plus one to obtain a counting signal; the capacitive digital-to-analog converter feedback network is used for feeding back the low-noise amplifier output signal to the input end and controlling the output signal folding counting signal folding steps, so that the low-noise amplifier output signal is not saturated. The beneficial effect is that the design is simple, the response speed is fast, the input and output amplitudes are large, the input signal amplitude is large, and the output signal is not saturated under the condition of large gain.

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

This document relates to communication by backscattering of satellite signals. One example includes a satellite backscatter transmitter having a first antenna configured to receive a radio frequency satellite signal, a modulator configured to modulate the radio frequency satellite signal to obtain a modulated radio frequency satellite signal, a digital logic circuit configured to selectively control the modulator to encode information according to a communication scheme, and a second antenna configured to passively retransmit the modulated radio frequency satellite signal to a receiver.

The present invention discloses a system and method for compensating the optical path power of a fiber optic gyroscope using a binary modulation depth method, and belongs to the technical field of fiber optic gyroscopes. The system includes a fiber optic gyroscope closed-loop system and a signal processing circuit. In the signal processing circuit, the photocurrent signal detected by the photodetector is amplified and converted into a digital signal. In the FPGA digital logic circuit, the signal is modulated using a binary modulation depth method, and the optical path power and angular velocity in the digital signal are demodulated using a digital operation method. The generated feedback signal is fed back to the current control port of the wide-spectrum light source and the phase modulator of the Y-waveguide integrated optical chip. The present invention uses a shared A / D detection channel for optical path power compensation and fiber optic gyroscope angular velocity detection, eliminating the need for an additional optical power detection module. Real-time compensation of the optical path power of the fiber optic gyroscope can be achieved without affecting the performance and size of the fiber optic gyroscope, thereby increasing the reliability and stability of the fiber optic gyroscope.

The invention discloses a crane rotating speed monitoring system and a crane, the crane rotating speed monitoring system comprises a permanent magnet ratchet ring and a double-sensor assembly, the double-sensor assembly is installed on a winding drum and comprises a first magneto-dependent sensor and a second magneto-dependent sensor, and when the winding drum rotates, the first magneto-dependent sensor and the second magneto-dependent sensor are connected; the first magneto-dependent sensor and the second magneto-dependent sensor respectively output a first square wave signal and a second square wave signal with constant phase difference, so that the rotation direction of the winding drum is represented through the phase relationship between the first square wave signal and the second square wave signal; and the direction distinguishing module is used for generating a direction signal and a counting pulse signal based on pure digital logic circuit processing. Therefore, the crane rotating speed monitoring system realizes real-time judgment of forward and reverse rotation and quadruplicated frequency counting through orthogonal signal output of the permanent magnet ratchet ring and the double magneto-dependent sensors in combination with a pure hardware direction judgment module, and the position monitoring resolution is improved.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

The invention relates to a chip system, a startup and shutdown manager, a power supply circuit and electronic equipment, and relates to the technical field of terminals. The chip system comprises a startup and shutdown manager, a power supply circuit and a data processing system, wherein the startup and shutdown manager comprises a digital logic circuit. The digital logic circuit is used for responding to the input of the device button and sending a first pulse signal to the power supply circuit through the enabling output end, and the first pulse signal is used for controlling the power supply circuit to supply power to the data processing system. In response to a constant electric signal received by the feedback controlled end from the feedback output end of the power supply circuit or the feedback output end of the data processing system, a first power supply signal is sent to the power supply circuit through the enabling output end, and the first power supply signal is used for controlling the power supply circuit to continuously supply power to the data processing system. Therefore, the cost can be reduced.

In accordance with the described techniques, a device or system includes a digital logic circuit organized into multiple partitions, and a power gating circuit. Further, the digital logic circuit includes base logic representing the digital logic circuit before being modified by external logic of the system that is external to the digital logic circuit. The power gating circuit is configured to independently control power supplied to the multiple partitions of the digital logic circuit. As part of this, the power gating circuit initiates a power state transition to a power state in which an entirety of the base logic of the digital logic circuit is powered off.

The application relates to the technical field of integrated circuit signal detection, and provides a baud rate signal detection circuit and a CDR loop structure which are composed of two data samplers, one error sampler and a digital logic circuit, can provide better jitter performance compared with a traditional MMPD, do not need to depend on accurate reference level VRFE amplitude setting, and have relatively lower design difficulty compared with traditional designs. In addition, the signal detection circuit can also detect the frequency deviation between input data and a sampling clock, so that the baud rate CDR function with a wide frequency capture range can be realized by using only a single control loop without increasing additional clock and sampling circuits, external reference clocks are not needed, the difficulty of the performance and cost compromise mentioned above can be greatly reduced, and the overall design cost is greatly reduced.

A device includes an open-drain driver, a comparator, and digital logic circuitry. The open-drain driver is operable to pull down and release a reset voltage on a reset line in response to an open-drain enable signal. The comparator is operable to generate a comparison signal by comparing the reset voltage to an active threshold voltage. The digital logic circuitry is operable to test a connection to the reset line. The test includes asserting the open-drain enable signal to pull down the reset voltage on the reset line, asserting the open-drain enable signal to make the reset voltage unreferenced, and determining, in response to a change in the reset voltage relative to the active threshold voltage, that the connection is either good or failed.

The invention relates to a safety module used in civil and military aircraft, in which the control of power layers is carried out via a safety analysis algorithm on an internal programmable digital logic circuit, where the temperature, current, and voltage values of the hardware are monitored with a contactless and integrated sensor in order to detect situations of overheating, excessive power consumption, overvoltage, spark, and gas – smoke emission.

The application discloses a one-time fuse trimming circuit based on an SPI communication protocol and belongs to the field of electronic circuits, comprising an SPI communication module and a fuse burning and writing digital logic circuit; the SPI communication module comprises a normal mode and a fuse mode; the normal mode comprises data bits, control bits and redundant bits; the fuse mode comprises a fuse address bit, a fuse control bit, a fuse mode bit, a fuse flag bit and a fuse enable bit; the fuse burning and writing digital logic circuit comprises a FIFO unit, an interlocking unit, a rising edge trigger unit and a fuse burning and writing execution unit. The application reuses the general SPI communication protocol, can temporarily reuse the SPI channel to burn and write the fuse according to a special method, can burn and break the end flag fuse after burning and writing the fuse, permanently closes the burning and writing path, is safe and reliable, will not appear misoperation, and saves a large amount of interface resources.

The utility model relates to an engine rotating speed processing device, which belongs to the technical field of rotating speed acquisition and processing and comprises a frequency division amplifier, the frequency division amplifier amplifies and shapes rotating speed signals into square waves, simultaneously can divide the signals in proportion, divides the rotating speed signals into two parts after processing, and outputs the two parts to a controller for use. According to the utility model, the digital logic circuit is adopted to collect the input rotating speed and divide the collected rotating speed into two parts, so that different control systems can obtain the same rotating speed signal, and the redundancy control is more reliable; and meanwhile, the collected rotating speed signal is processed into a 4-20mA signal for on-site display or upper computer display.

The dynamic memory array of a DRAM device operates using at least two voltages. A first voltage is the operating (i.e., switching) voltage of most of the digital logic circuitry of the DRAM device, which is used to power sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write). A second voltage is greater than the operating (i.e., switching) voltage of most of the digital logic circuitry of the DRAM device, which determines the voltage written to the capacitor of a DRAM cell (i.e., the bit line voltage). The digital logic circuitry operates using a supply voltage, which is lower than the voltage written to the capacitor of the DRAM array. This allows lower voltage swing digital logic to be used for most of the logic on the DRAM device, while a larger voltage is written to the DRAM cell.

The present invention discloses a method for fabricating a driver chip based on hybrid bonding and heterogeneous integration. First, a first wafer is provided, and multiple first chips, each containing a high-voltage analog driver circuit and / or a medium-voltage analog driver circuit, are fabricated on the first wafer using a first process node. Then, a second wafer is provided, and multiple second chips, each containing digital logic circuits and memory cells, are fabricated on the second wafer using a second process node. The first process node is a more mature process node than the second process node. Finally, the first and second wafers are bonded together using a wafer-level hybrid bonding process to form the driver chip, and electrical interconnects are formed at the bonding interface. This achieves an optimal combination of the high-voltage / medium-voltage driver portion and the logic / memory portion at different process nodes.

The invention discloses a method, a device and a system for fault detection of a connection to a reset line. The device includes an open drain driver, a comparator, and a digital logic circuit. The drain open driver is operable to pull down and release a reset voltage in the reset line in response to the drain open enable signal. The comparator is operable to generate a comparison result signal by comparing the reset voltage with an effective threshold voltage. The digital logic circuit is operable to test a connection to the reset line. The testing includes validating a drain open enable signal to pull down a reset voltage in a reset line, releasing the drain open enable signal to float the reset voltage, and determining whether the connection is a good connection or a faulty connection in response to the reset voltage changing relative to an effective threshold voltage.

The application discloses a relaxation oscillator based on a switched capacitor array and a peak feedback structure and a stabilizing method, the oscillator comprising a reference source, a switched capacitor array, a peak voltage feedback module, a comparator and a digital logic circuit, the switched capacitor array comprising two symmetric charge-discharge branches, each branch having a main charging capacitor and a tracking holding capacitor, and the peak voltage feedback module being composed of an operational amplifier, a feedback capacitor and a sampling switch. In operation, the capacitor voltage of one branch charged alternately is compared with a dynamic threshold, and the peak voltage on the tracking holding capacitor of the other branch is sampled to the feedback module at the switching moment, the comparator threshold is dynamically adjusted through the integral action, and finally the capacitor peak voltage is locked to the fixed reference voltage, so that the influence of non-ideal factors such as comparator delay on the oscillation period is systematically offset. The application also adopts a chopping comparator to eliminate the offset. The architecture significantly improves the stability of the oscillation frequency to the power supply voltage and temperature, and helps to realize low phase noise, and is suitable for high-precision on-chip clock sources.

The invention discloses a low-power-consumption remote wake-up circuit of a CAN FD transceiver. The low-power-consumption remote wake-up circuit comprises a comparator, a filtering time detection module and a wake-up circuit module. The comparator is used for comparing the level of the CANH and the level of the CANL, when the CANH is larger than the CANL, a high level is output and marked as a dominant state, and when the CANH is smaller than the CANL, a low level is output and marked as an implicit state. The filtering time detection module is composed of a phase inverter and a capacitor; the wake-up circuit module is composed of a digital logic circuit so as to achieve the function of multi-filtering dominant wake-up. When the CAN FD transceiver enters a low-power-consumption mode, the CAN FD transceiver receives CANH and CANL signals, the comparator compares the levels of the CANH and CANL signals and outputs the signals to the filtering time detection module, and the signals with dominant or implicit signal pulse width time smaller than tFilter are filtered out; through the wake-up circuit module, when an input signal satisfies an ''explicit-implicit-explicit'' signal sequence, the signal received by the CAN FD transceiver is output, and the low-power-consumption mode is not quitted, so that remote wake-up of the CAN FD transceiver is realized.

The utility model discloses a circuit structure of an ultrasonic flowmeter, which comprises a digital logic circuit, a digital-analog mixed signal circuit and an analog signal circuit, the digital-analog mixed signal circuit is connected with the digital logic circuit and the analog signal circuit, the digital logic circuit is connected with an ultrasonic transmitting transducer, and the analog signal circuit is connected with an ultrasonic receiving transducer; power line cathodes of the digital logic circuit, the digital-analog mixed signal circuit and the analog signal circuit are gathered in the PCB and are connected to the same grounding node to form a star-shaped grounding structure; the grounding node is electrically connected with a ground wire. According to the utility model, power supplies and ground wires of different functional modules are subjected to single-point grounding, so that the noise of the digital logic circuit can be limited within a specific circuit range, and the quality of ultrasonic echo signals can be remarkably improved.

The present invention discloses a digital gain error compensation system and method for a closed-loop fiber optic gyroscope (FOG), belonging to the technical field of FOGs. The system includes a FOG closed-loop system and a signal processing circuit. In the signal processing circuit, the photocurrent signal detected by the photodetector is amplified and converted into a digital signal. In the FPGA digital logic circuit, the digital gain error and angular velocity in the digital signal are demodulated through digital operations to generate a feedback signal containing angular velocity compensation information and gain error compensation information. The signal is converted into an analog signal by a single D / A module and fed back to the FOG closed-loop system through a drive circuit, thereby achieving real-time gain error compensation for the FOG. The static and dynamic performance of the present invention are substantially consistent with those of a traditional closed-loop FOG using two D / A modules, reducing the cost of the FOG and enhancing the stability of the gain error feedback.

An adaptive following capacitive sensor chip circuit, comprising: a CDAC circuit connected to an external load capacitor, a sample and hold circuit and a digital logic circuit respectively, for tracking the external load capacitor to keep consistent with the size of the external load capacitor; a RDAC circuit connected to the digital logic circuit and a comparator circuit group respectively, for generating a reference value that can be automatically adjusted to adapt to different degrees of external triggering action; an input end of the sample and hold circuit is connected between the external load capacitor and the CDAC circuit, and an output end is connected to the comparator circuit group, for controlling the acquisition of the external load capacitor size according to the signal sent by the digital logic circuit to the CDAC circuit, and outputting it to the comparator circuit group for comparison and judgment; the digital logic circuit is connected to the comparator circuit group and the sample and hold circuit, for providing the sample and hold circuit with a control timing signal, and providing the CDAC circuit and the RDAC circuit with an excitation voltage signal according to the output result of the comparator circuit group.

In some examples, a circuit includes a first transistor (312), a second transistor (314), a first resistor (318), and a digital logic circuit (106). The first transistor has a control terminal and first and second terminals. The second transistor has a control terminal and first and second terminals, the first terminal of the second transistor coupled to the second terminal of the first transistor. The first resistor has first and second terminals, the first terminal of the first resistor coupled to the control terminal of the second transistor, and the second terminal of the first resistor coupled to the first terminal of the second transistor. The digital logic circuit has an output terminal and first and second input terminals, the output terminal of the digital logic circuit coupled to the control terminal of the second transistor, the first input terminal of the digital logic circuit coupled to a data transmit input terminal (TXD) of the circuit, and the second input terminal of the digital logic circuit coupled to a data receive output terminal (RXD) of the circuit.

The invention provides an inrush current limiting system supporting a full PD type. The system comprises a comparison delay circuit which is configured to generate a delay signal when a system state represented by a load voltage is changed from current limiting to inrush current limiting; an RS latch configured to output 1 or 0 for characterizing a signal type according to a signal input by the comparison delay circuit; a current sampling resistor configured to obtain a sampling current in the circuit loop; the surge current detection circuit is configured to input a corresponding limit threshold value into the positive end of the comparator according to the type of the signal output by the RS latch and input a sampling current into the negative end of the comparator; the comparator is configured to perform comparison according to a limit threshold and the sampling current and generate a corresponding driving signal; the driving signal is used for controlling the conduction condition of the hot plug transistor together with the digital logic circuit. According to the system, the problem that an existing surge current limiting circuit lacks compatibility is solved.