63 results about "Serial transfer" patented technology

The invention provides a core particle and a test method thereof, and the core particle comprises a home terminal generator which is used for generating and sending a test code to a sending channel for transmission; wherein one test code is transmitted through one sending channel, and the number of the test codes is the same as that of the sending channels; the home terminal multiplexer is used for receiving the detection code through the receiving channel; wherein one detection code is received through one receiving channel, and the number of the detection codes is consistent with the number of the receiving channels; and the home terminal checker is used for generating a corresponding check code according to the received detection code and checking the corresponding detection code through the check code, if the check is successful, the transmission channel corresponding to the detection code is unobstructed, otherwise, the transmission channel corresponding to the detection code is transmission fault. According to the core particle and the test method thereof provided by the invention, the requirements of a serial transmission test of a single channel and a parallel transmission test of a plurality of transmission channels can be met.

High Bandwidth IJTAG Through High Speed Parallel Bus A system in a circuit comprises: a first network (710) configurable to transmit data in parallel in the circuit, the first network (710) comprising circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of circuit blocks in the circuit; a plurality of second networks (720, 725, 727), each of the plurality of second networks (720, 725, 727) configurable to transmit data in serial in one of the circuit blocks in the circuit; a third network (730) configurable to transmit data in serial in the circuit when being coupled to the plurality of second networks (720, 725, 727); and a plurality of network switching interface devices (740, 745, 747), each of the plurality of network switching interface devices (740, 745, 747) configurable to couple either the first network (710) or the third network (730) to one of the plurality of second networks (720, 725, 727) based on a control signal stored in the each of the plurality of interface devices (740, 745, 747).

The invention relates to a low-pin I2C serial transmission method and a low-pin I2C transmission system using the same. The low-pin I2C serial transmission method comprises the steps that a plurality of I2C serial transmission slave devices and an I2C serial transmission master device are provided, and the I2C serial transmission slave devices and the I2C serial transmission master device are electrically connected to an I2C serial transmission flat cable; coupling an interrupt request pin of each I2C serial transmission slave device to an interrupt input pin of the I2C serial transmission master device; when a specific I2C serial transmission slave device in each I2C serial transmission slave device proposes an interrupt request, the interrupt request pin of the specific I2C serial transmission slave device outputs a voltage corresponding to the specification of the specific I2C serial transmission slave device; and according to the voltage of the interrupt input pin of the I2C serial transmission master device, judging whether each of the I2C serial transmission slave devices meets the interrupt requirement or not.

The invention discloses a microwave measurement and control device, and relates to the technical field of particle acceleration. The antenna comprises a backboard, a radio frequency unit and a tuning unit. The backboard is provided with a high-speed serial transmission channel; the radio frequency unit is connected with the backboard to collect radio frequency field state data of the accelerator cavity; the tuning unit is connected with the backboard to output a driving signal to adjust the resonant frequency of the cavity. Wherein the radio frequency unit and the tuning unit establish a direct connection link through a high-speed serial transmission channel, and the tuning unit cooperatively adjusts the resonant frequency of the cavity according to radio frequency field state data. A traditional CPCI architecture is optimized through the backboard, the high-speed serial transmission channel comprises the first communication channel, radio frequency field state data does not need to be transferred and is directly transmitted to the tuning unit through the high-broadband and high-performance first communication channel, the problems of large transmission delay and cooperative lagging caused by bandwidth sharing of an existing CPCI architecture are effectively solved, and the communication performance of the CPCI architecture is improved. Tuning can be rapidly carried out through closed-loop control, and the stability of the accelerator beam is remarkably improved.

The transmitter device includes a configurable timer circuit that adjusts the timing of the input data for serial transmission of the input data. The configurable timer circuit may be configured according to a configured data rate of the transmitter device. In one embodiment, a configurable timer circuit includes a plurality of configurable retimers that retime input data, where at least a portion of one of the plurality of configurable retimers is enabled based on a configured data rate.

This invention discloses an in-vehicle video redundancy system. The system includes: an intelligent driving acquisition device for acquiring multiple video streams transmitted in parallel by a target vehicle under different vehicle states; an in-vehicle serializer for converting the parallel-transmitted multiple video streams into serial transmission; an in-vehicle dual-channel deserializer for converting the serially transmitted multiple video streams into target multiple video streams transmitted in parallel, and synchronously transmitting the target multiple video streams to an intelligent driving driving SOC chip and an intelligent driving parking SOC chip respectively; the intelligent driving driving SOC chip and the intelligent driving parking SOC chip are used to process the target multiple video streams according to the vehicle state of the target vehicle and the video stream type of the target multiple video streams, store the processed target multiple video streams, and display them on a display screen. This invention considers the redundancy design and safety backup control of the acquisition device, solving the problem of intelligent driving function loss due to the failure of one SOC, and ensuring the safety of the driver and passengers.

The invention discloses an improved low-peak-to-average-ratio imitation radio frequency division multiplexing signal transmission method based on a chaotic sequence. Acquiring a signal to be transmitted, and performing serial-parallel processing on the signal to be transmitted to obtain a plurality of subcarriers of the signal to be transmitted; generating an initial chaotic sequence, and mapping the initial chaotic sequence to generate a random phase sequence vector; performing modulation processing on the plurality of subcarriers based on the random phase sequence to obtain a candidate transmission signal group; selecting a signal with the minimum signal peak-to-average ratio from the candidate transmission signal group as a second signal to be transmitted; adding a linear frequency modulation period prefix to the second signal to be transmitted, and performing parallel-serial conversion processing to obtain a first serial transmission signal; and transmitting the first serial transmission signal to a doubly selective channel to obtain a receiving end signal. The transmission method has the characteristic of high spectrum utilization rate.

The utility model belongs to the technical field of vehicle-mounted 4D millimeter wave radars, and particularly discloses a vehicle-mounted 4D millimeter wave radar data acquisition circuit, which comprises an MMIC millimeter wave radio frequency chip and an FPGA chip. The MMIC millimeter wave radio frequency chip is electrically connected with the plurality of 4D millimeter wave receiving antennas and the plurality of 4D millimeter wave transmitting antennas; the MMIC millimeter wave radio frequency chip is electrically connected with the FPGA chip; one path of output of the FPGA chip is electrically connected with the radar signal processing chip, and the other path of output of the FPGA chip is electrically connected with the serial chip. According to the utility model, the FPGA chip is adopted to carry out one-to-two MIPI processing on an MIPI signal of the MMIC millimeter wave radio frequency chip, one path is transmitted to the radar signal processing chip SOC, the other path is provided for the serial chip Serdes to carry out serial transmission on the MIPI signal, and the transmission distance can reach more than 15 meters, so that a radar data algorithm processing function is realized, real-time acquisition is also carried out, and the real-time acquisition is realized. And transmitting to a far end for storage.

The invention discloses a parallel remote upgrading method based on expressway port communication, and belongs to the field of avionics. The method is based on an upper computer, a loading board and a loaded board, wherein the loading board is realized based on an FPGA (Field Programmable Gate Array). The upper computer communicates with the loading plate through a high-speed port, the loading plate communicates with the loaded plates through various serial interfaces, the upper computer can read upgrading files of the loaded plates at the same time and then send the upgrading files to the loading plate in a subpackage mode, and the loading plate receives the upgrading files and caches the upgrading files to different DDR spaces. And when the loading board detects that a certain upgrading file is cached, the upgrading file in the DDR space is read in a segmented manner, and serial transmission upgrading is carried out on the board card main control chip. Due to the fact that the communication bandwidth of the high-speed port is far larger than the bandwidth of the serial port, the upper computer can quickly complete transmission of a plurality of upgrading files to the loading board DDR, the upgrading process of a plurality of loaded boards is started in sequence, and the parallel upgrading effect is presented.

To provide a semiconductor device having a self-detection function which is capable of detecting abnormality of a serial data value after format conversion from parallel data to serial data.SOLUTION: A semiconductor device includes: a parallel-serial conversion circuit 13 having parallel data input 25 and parallel data output 23, the parallel-serial conversion circuit 13 configured to generate a serial data signal including each data value in a set of serial data converted from a set of parallel data in a parallel data signal received with the parallel data input 25 and to provide the serial data signal to the parallel data output 23; a regeneration circuit 15 configured to generate a regeneration signal indicating a set of regenerated parallel data from the serial data signal from the parallel data output 23; and a determination circuit 17 for determining match / mismatch between at least a part of the regeneration signal and at least a part of the set of parallel data signals.SELECTED DRAWING: Figure 1

The invention discloses a readout circuit for time-sharing readout quantization, an analog-to-digital converter and electronic equipment, and relates to the field of integrated circuits. Comprising a plurality of sampling units and a plurality of quantization units which are arranged in a column-level circuit. Each sampling unit in the plurality of sampling units is connected with each wide row in the pixel array in a one-to-one correspondence manner; each column in the column-level circuit is correspondingly provided with a quantization unit and a plurality of sampling units, and the number of the sampling units correspondingly arranged in each column is the same as the row number in the wide row; wherein in each wide row time, pixel signals of each row corresponding to a wide row on a column are read into the sampling unit of the column in a time-sharing manner, and then the quantization unit arranged in the column is used for quantization in the next quantization time. According to the invention, serial transfer of a plurality of analog voltages and parallel conversion of the analog-to-digital converter are adopted, so that the quantization time of each row is greatly extended, the condition that the quantization time is limited is well relieved, and the purpose that the infrared detector completes high-speed accurate reading with relatively low power consumption is achieved.

The invention is suitable for the technical field of display, and particularly relates to a driver, a serial-parallel compatible communication method under serial connection of the driver and a display system. The driver comprises a data serial input port, a data serial output port, a parallel path, a serial path and a multiplexer, the first ends of the parallel path and the serial path are connected with the data serial input port, and the second ends of the parallel path and the serial path are connected with the first end of the multiplexer. The second end of the multiplexer is connected with the data serial output port, and the multiplexer is used for obtaining a current instruction received by the data serial input port in the current data transmission of the controller, and sending the current instruction to the controller according to the path type expected by the instruction corresponding to the next data transmission carried in the current instruction; after the data transmission is completed, the parallel path or the serial path is controlled to be conducted, parallel and serial transmission instructions can be taken into account under the serial-connected driver link without configuring other ports, and the working efficiency is improved.

The embodiment of the invention provides a full-matrix lamp string system and method and a control circuit of a functional device, a lamp string comprises a controller, a plurality of light-emitting units, a main circuit and M branches, M is greater than or equal to 2, the main circuit is connected with the controller and supplies power to at least one branch, any branch is provided with at least one light-emitting unit, and M is greater than or equal to 2. The M branches comprise a first branch and a second branch; the controller is used for outputting a serial data packet, the serial data packet sent by the controller is input to the first branch, and an output signal of at least one light-emitting unit in the first branch serves as an input signal of the head-end light-emitting unit in the second branch. According to the embodiment of the invention, the light-emitting units in the branches can transmit the control data in series, the control data can be transmitted between the branches in series, the light-emitting units of the lamp string can extract data streams belonging to the light-emitting units, and independent control of the light-emitting units in the lamp string can be realized without an address code and a hub.

The application relates to the technical field of lamp effect control, and discloses an A- RGB lamp effect control method and device, the method comprising the following steps: sending device query instructions to an external A- RGB device connected with a first channel and a second channel in sequence, receiving response codes returned by the external A- RGB device, and comparing the response codes with brand protocol characteristic codes stored in a flash in byte by byte, so as to obtain serial transmission code stream data; configuring a first PDMA channel and a second PDMA channel to read the serial transmission code stream data from the first channel and the second channel respectively, and outputting parallel lamp effect data of a double-path 1-wire port; calculating a timestamp difference value based on the parallel lamp effect data, and starting a delay timer to delay the PDMA enabling operation of a channel with an earlier timestamp when the timestamp difference value exceeds a preset synchronization threshold value, so that the application realizes synchronous lamp effect output of double-path channel timestamp alignment, and solves the problem of lamp effect asynchronization caused by conversion time difference of cross-brand device protocols.

The invention belongs to the technical field of distribution network operation, and particularly relates to a power distribution network load transfer method. Comprising the following steps: presetting a load transfer condition, and obtaining distribution network operation data; according to a preset load transfer condition, screening the line standing book table and the inter-line contact relation table, and forming a network topology table; based on the network topology table, single radiation lines are removed, and an undirected graph is generated with the lines as nodes and connection between the lines as edges; dividing the undirected graph into a plurality of connected sub-graphs, generating a set of all wheeling modes of each connected sub-graph, and calculating an optimal wheeling mode and a global optimal series supply mode of each connected sub-graph; and if the preset load transfer condition contains the back-carrying bus, calculating a global optimal transfer mode of the back-carrying bus on the basis of the global optimal series supply mode.

The invention provides a high-robustness high-speed serial transmission data sampling method, which is used for solving the technical problem that a sampling point is not an optimal sampling point or even an error sampling point when the existing high-speed serial transmission data is sampled. According to the high-robustness high-speed serial transmission data sampling method provided by the invention, the delay range of the delay module is fully utilized, all delay tap numbers of the delay module are traversed to obtain n + 1 indication bits, then the n + 1 indication bits are traversed to determine the maximum number of continuous 1 and the end position of the maximum continuous 1, and finally, the number of the continuous 1 is determined. The optimal sampling point in the maximum effective sampling window is found through parity, the optimal delay tap number needed by phase alignment is obtained, the sampling method is simple and efficient, the alignment precision is high, and high robustness of data transmission is guaranteed.

Disclosed are a wideband frequency multiplier matching device and method. The method of matching a wideband frequency multiplier comprises the steps of: for sequential loadpull matching from an output port, setting an output port (Y) to 50 Ω and then connecting an open stub (TL4) to the output port; connecting a serial transmission line (TL3) to the output port (Y); and connecting a dual short stub (TL2) to the front end of the serial transmission line (TL3).

The invention discloses a data transmission system and method based on an off-chip internet, and relates to the technical field of data transmission outside a chip. The data transmission system based on the off-chip internet comprises a data sending chip, a data receiving chip and the off-chip internet, the data sending chip is used for sending data to the off-chip internet; the off-chip internet is used for generating a packet header and representation information corresponding to each piece of data; a protocol message is generated according to the data, the packet header and the representation information, and the protocol message is sent to the data receiving chip; the representation information comprises the length of the corresponding data and the offset of the address of the corresponding data relative to the address of the protocol message. According to the invention, data serial transmission resources of the off-chip internet can be saved, the transmission utilization rate is improved, the overall performance of the system is improved, and bandwidth waste caused by transmission of non-data messages by a serial transmission channel is greatly reduced.

A tool holder (200) is attached to a machine tool body (100) and is capable of holding a tool. The tool holder (200) comprises: a sensor and / or an actuator (381); a substrate (410) having mounted thereon an electronic circuit (721) capable of converting an electrical signal from the sensor and / or the actuator (381) into a digital signal that can be serially transmitted; a serial terminal (220A) that forms an electrical contact with the machine tool body (100) and is for performing serial transmission of the digital signal; and a power supply terminal (220B) that forms an electrical contact with the machine tool body (100) and is for supplying power to the sensor and / or the actuator (381).

A filecoin cluster data transmission method and system based on RDMA, including: providing a RDMA interface; receiving and encapsulating sector data by a first node, invoking the RDMA interface to transmit the sector data, serially transmitting the sector data to a next encapsulation node; when receiving the sector data from a previous node, invoking the RDMA interface to directly transmit the sector data to a user mode memory of the node for encapsulation; invoking the RDMA interface to serially transmit the sector data back to the HCA card, and transmitting the sector data to a next node; receiving, by a last node, the sector data, invoking the RDMA interface to directly transmit the sector data to the user mode memory of the last node; invoking the RDMA interface to serially transmit the sector data back to the HCA card of the last node, and transmitting the sector data to distributed storage.

Systems and methods for using memory-mapped memories in a microcontroller-based instrument are provided herein. The method includes operating the microcontroller-based instrument using a complex application or protocol and operating a highly integrated, low-power microcontroller unit (MCU). The MCU is configured to use memory mapping for accessing at least one off-MCU memory connected to the MCU by at least one interface. The MCU's memory-mapping configuration enables the off-MCU memory(ies) to behave as an extension of at least one on-MCU memory that is connected directly to the CPU to effectively extend a range of the at least one on-MCU memory, wherein the effective extended range of the at least one on-MCU memory enables the microcontroller-based instrument to utilize the complex application or protocol. The method further includes writing addresses and / or data to and / or reading addresses and / or data from the off-MCU memory using serial transmission during a memory mapped transaction.

An apparatus for processing a serialized video stream and related aspects are disclosed. For example, the apparatus (302) may comprise: a receiver (304) configured to receive a serialized video stream comprising a plurality of serially transmitted video frames from a video source (102), each video frame comprising a plurality of frames, each frame comprising a plurality of frame lines, each frame line comprising a set of active pixels and blanking pixels; at least one buffer (305) arranged to buffer at least effective pixels of the received serialized video stream until pixels of a complete frame line are received; one or more processors or processing circuitry (308) configured to, for pixels of each buffered complete frame row, assign a frame row position indicator to an effective pixel group comprising effective pixels of the buffered complete frame row, and generate a data structure comprising the effective pixel group and the frame row position indicator assigned to the effective pixel group, each data structure comprises a set of effective pixels from the received frame line, and at least one blanking pixel of the received frame line is omitted; and a transmitter (310) configured to forward transmit an outgoing serialized video stream comprising the generated data structure; and after transmitting a data structure comprising a set of valid pixels and the assigned frame line position indicator, suspending forward transmission of the outgoing serialized video stream between the data structures until a next data structure comprising a different set of valid pixels and a different frame line position indicator is ready for transmission.

The invention provides an integrated three-way DA conversion circuit control system for laser marking control, comprising a simple horn socket J1, a detection signal unit, an optical coupling isolation unit, a DA conversion unit and an operational amplifier unit; the simple horn socket J1 is connected with the detection signal unit and the optical coupling isolation unit; the detection signal unit and the optical coupling isolation unit are respectively connected with the DA conversion unit, and the DA conversion unit is connected with the operational amplifier unit; the simple horn socket J1 is configured to receive a control signal and output a differential serial transmission signal to the detection signal unit and the optical coupling isolation unit; the differential serial transmission signal comprises a clock signal, a synchronization signal, an X-axis control signal, a Y-axis control signal and a Z-axis control signal; the system is provided with a detection signal unit, which can prejudge the control signal, thereby avoiding the problem of laser random marking caused by the deflection of each motor to the maximum or minimum position and the instantaneous reaching of the limit position by the laser.

The invention discloses a data transmission chip and electronic equipment, and belongs to the technical field of electronics. Wherein the low-speed interface of the data transmission chip is used for receiving multiple paths of first signals, and the high-speed serial interface of the data transmission chip is used for serially transmitting the multiple paths of first signals to another data transmission chip in a data frame manner. As the plurality of paths of signals can be serially transmitted between the data transmission chips in a data frame manner, the number of signal lines required to be arranged between the data transmission chips can be effectively reduced, and the structure of the electronic equipment is further simplified. And the data transmission rate of the high-speed serial interface is relatively high, so that the transmission efficiency of the multiple paths of first signals can be effectively ensured.

This provides an auxiliary circuit for serial transmission and reception that stably receives signals from the received data line. [Solution] In the master device 101, the user circuit 301 operates with the system clock CLK and communicates with an external slave device via the synchronous serial bus transmit / receive circuit 302. The received data delay circuit 303 further delays the received data synchronized by the synchronization circuit 304 in units of the system clock using a shift register, and outputs one of the signals of the shift register via the selector 308 based on RXSEL specified by the user circuit. The synchronization circuit 304 synchronizes the received data RX input from outside the master device with the system clock. The synchronous serial bus transmit / receive circuit 302 serializes TXpara using the serialization circuit 305, synchronizes it with the transfer clock, and outputs the signal RXd received with the transfer clock by deserializing it using the deserialization circuit 306.

The utility model discloses a signal receiving device and a chip. The signal receiving device is used for receiving and processing at least two paths of data signals, the data signals comprise effective data carrying to-be-transmitted information and a synchronization head used for marking the starting position of the effective data, and the signal receiving device comprises a physical layer interface used for receiving the serial transmission data signals, a cache module arranged in the physical layer interface is used for storing the data signals which are transmitted in parallel and providing interface output signals which are transmitted in parallel, so that synchronous heads of all paths of data signals in the interface output signals are aligned with one another; and the analysis unit is connected with the physical layer interface and is used for receiving and analyzing the interface output signal. By aligning the synchronization head in each path of data signal, a data analysis error caused by data dislocation is avoided.

A method for near field communication with a serial transmission microcontroller and an NFC tag device using the same are provided in the present invention. The method includes: providing a serial interface microcontroller; capturing an NFC carrier signal from an NFC LC resonant circuit; performing a frequency division to the NFC carrier signal to obtain a NFC clock signal; filtering the NFC carrier signal from the NFC LC resonant circuit to obtain an envelope signal; sequentially receiving a digital sequence of the envelope signal according to triggering of the NFC clock signal based on a serial transmission protocol; and decoding an NFC data from the digital sequence based on an NFC transmission protocol rule.

The invention relates, inter alia, to a measurement data transmission device for transmitting measurement data from at least two measuring tools to an evaluation unit, wherein the measurement data transmission device has a communication device, wherein the communication device is designed and configured to communicate wirelessly with the measuring tools and to communicate with the evaluation unit by cable, in particular via USB, wherein the measurement data transmission device is designed and configured to receive measurement data from at least one of the measuring tools by means of the communication device and to transmit received measurement data serially to the evaluation unit by means of the communication device, which is further developed in that the measurement data transmission device has a mass storage device for storing configuration files, wherein the measurement data transmission device is designed and configured,to read out and process at least one configuration file stored in the mass storage device with communication settings stored therein, wherein the communication device is designed and configured to receive measurement data from at least one of the measuring tools according to the communication settings and / or to transmit received measurement data serially to the evaluation unit.

The invention provides a high-speed serial data transmission method and system, electronic equipment and a medium. Effective data and training codes are alternately set for any LVDS link data in a specific period; the serially transmitted LVDS link data is serial link data, and the serial link data is converted into parallel link data after being subjected to serial-parallel conversion. The method comprises the following steps: a receiving end receives and outputs effective data of each parallel link data to complete effective data receiving; the receiving end receives the training code of each piece of parallel link data; based on the training code, judging a bit alignment state of the valid data; if the effective data and the training codes are not aligned, bit shifting is adopted, so that the effective data and the training codes are in a bit alignment state, and all LVDS link data receiving is completed. According to the method, bit alignment errors are dynamically corrected under the condition that ESD interference exists in high-speed serial data transmission, it is guaranteed that data transmission is automatically recovered after external interference disappears, and the stability of data transmission is improved.

The application provides a parallel-serial conversion circuit, comprising an output clock generation circuit and an output circuit, the output clock generation circuit is used for outputting N output signals and N inverted output signals, the output signals and the inverted output signals are inverse signals of each other, the N output signals are sequentially delayed by one clock cycle, the N inverted output signals are sequentially delayed by one clock cycle, N is a natural number greater than 0, the output circuit is connected with the output clock generation circuit, used for receiving N parallel transmission transmission data, the N output signals and the N inverted output signals, sequentially outputting the N transmission data according to the N output signals and the N inverted output signals, so as to convert the N parallel transmission transmission data into N serial transmission transmission data, without a selector, reducing the number of flip-flop flips, thereby reducing power consumption and reducing the occupied area.