502 results about "Serial transfer" patented technology

According to a display device of the present invention, a frame memory is integrally formed on a substrate (pixel substrate) on which a pixel portion is formed. With this construction, one row of data can be simultaneously read from the frame memory and can be input to a drive circuit for pixels in parallel. As a result, a need for transferring image data in serial is eliminated. Then, a parallel/serial converting circuit and a serial output circuit, and a serial/parallel converting circuit and a parallel input circuit are not necessary. Therefore, a display device having a frame memory and a pixel portion can be constructed in a simpler construction and with an easier circuit. As a result, the noise can be reduced, and the low power consumption can be achieved.

A serial transmission protocol and architecture are provided that can be used to forward remote control data between sink (e.g., DTV) and source (e.g., DVD player) devices, in addition to other data such as video and/or audio or other payload. The target device need not be in the line of sight of the remote control beam. Daisy-chained devices will pass the remote control signal to the appropriate target device, so that the user can point any remote control at the DTV or other conveniently located device in the system, and still control the actual target device. The communication channel that carries payload, processing control, and remote control data can be implemented with wired or wireless of technology (or a combination thereof). In one particular embodiment, the communication channel is implemented with a single fiber. A number of presentation and entertainment system applications that employ remote control technology (e.g., home theater, audio, and computer implemented systems) can benefit from embodiments of the present invention.

An apparatus and method for improving the communication capabilities of computer systems is disclosed. The most preferred embodiments of the present invention use a series of data buffers and data registers to process an incoming high speed data signal. By using the buffers and registers, the incoming signal can be reformatted and manipulated at a much lower frequency than the original transmission frequency. The deserializer of the present invention also samples a greater portion of the incoming data signal than usual to further increase reliability. These various features of the invention provide for a more stable and reliable communication link and will also provide a less expensive solution for serialization/deserialization. The present invention includes a serializer that receives parallel data input from a computer and serializes the data for transmission over a high-speed serial communication link. On the receiving end, the present invention provides a deserializer that can quickly and efficiently transform the serial data back into parallel form for use within the computer system on the receiving end. By utilizing two related clock signals, one clock signal being an integer multiple of the other, a self-synchronizing serializer/deserializer can be created. In addition, by increasing the size of the data sample on the receiving end, the comparisons necessary to retrieve a parallel signal from a serial transmission can occur at a much lower frequency than the frequency of the serial transmission. In the most preferred embodiment, the invention is provided as a integrated solution manufactured on a Peripheral Component Interconnect (PCI) card, thereby allowing the present invention to be easy installed into existing computer systems.

A storage device control apparatus includes a channel control unit for outputting an I/O request for a storage device, having a CPU for receiving a data input/output request in a file unit, an I/O processor for outputting the I/O request corresponding to the data input/output request in the file unit in response to an instruction from the CPU, and a memory system for temporarily storing information required for a file access process of the CPU. The memory system includes a plurality of memory modules and a memory controller for controlling memory access to the plurality of memory modules, a command, an address and data being serially transmitted from the memory controller to each of the memory modules. Each of the memory modules has a plurality of memory elements and a plurality of buffer units. The memory controller and the memory system are connected by duplicated serial interfaces.

The invention discloses a data processing and transmitting system of high-speed multichannel CCD (charge-coupled device), which comprises a CCD analog front end, a data processing unit, a high-speed serial transmission unit and a high-speed image data collection system which are sequentially connected. The CCD analog front end is used for converting an analog signal output by a CCD detector and subjected to sampling and pulse control into n channels of digital image data via n A/D (analog/digital) converters, transmitting the digital image data to the data processing unit, and acquiring data of each channel at the same time. The data processing unit is used for transmitting single-channel high-speed data streams, a data transmitter clock and a horizontal synchronizing signal acquired from integration of the digital image data to the high-speed serial transmission unit. The high-speed serial transmission unit is used for converting single-channel high-speed data streams via LVDS (low-voltage differential signaling) serial chips into high-speed LVDS data streams for transmitting. The high-speed image data collection system is used for collecting the high-speed serial LVDS data streams and realizing real-time storing and displaying of the image data.

Network switching and/or routing devices can use multiple priority data streams and queues to support prioritized serial transmission of data from line cards (or the like) through a fabric switch to other line cards (or the like). Preemption logic is used to insert within a data stream commands indicating a switch from one priority level data to another. Delimiter commands and combination switch/delimiter commands can also be used. Multiple crossbars are implemented in the fabric switch to support the various data stream priority levels.

A data communication system includes a transmitter unit and a receiver unit. The transmission unit has a transmission characteristic that is adjustable in accordance with equalization information. The transmission unit is operable to transmit a predetermined signal and the receiver unit is operable to receive the predetermined signal. The receiver unit is further operable to generate the equalization information by examining the eye opening of the received signal, and to transmit the equalization information to the transmitter unit.

In order to transmit a large amount of data in series at a time with a MIMO communication scheme while avoiding deterioration of decoding characteristics due to change over time by a channel matrix, a wireless communication system uses an open-loop type and a closed-loop type of MIMO communication modes in combination and switches to the open-loop MIMO communication mode in response to the information that the amount of data to be transmitted at a time has exceeded a predetermined amount of bits or a predetermined transmission time during data transmission under the closed-loop MIMO communication mode. By discontinuing useless closed-loop MIMO communication and switching to the open-loop MIMO communication mode that is better than Zero-forcing, the decoding characteristics are prevented from simply becoming deteriorated.

A circuit to synchronize with a data transmission includes a comparator to read a set of data within a serialized data transmission, compare the set of data to a predetermined data pattern and output a comparison result. For a serialized data transmission, the comparator receives the serialized transmission and a shift register serially coupled to the comparator to hold the data pattern. A synchronization detector receives a comparison hit vector based on the comparison result from the comparator and aligns a boundary of a data frame according to the comparison hit vector if the comparison hit vector indicates a match between the data pattern in the set of data and the predetermined data pattern. For a deserialized data transmission, each stage of a multistage shift register read a set of data from the deserialized data transmission and selectively outputs the set of data to a comparator which compares each set to a predetermined data pattern and output a comparison result. A synchronization detector receives the comparison result from the comparator and aligns a boundary of a data frame according to the comparison result if the comparison result indicates a match between a data pattern sub-set within a combined data pattern and the predetermined data pattern, where the sets of deserialized data comprise the combined data pattern.

The cable for a medical device is an optically isolated serial transmission cable, used to connect a base device with a serial port, or the like, to a medical device. In an alternate embodiment of the invention, the invention enables auto detection of the cable. The base device is used to power the cable electronics. In another embodiment of the present invention, the interface cable is also supported by graphical and text message display that assists users in connecting the cable to both the medical device and a base device.

A non-volatile memory device capable of reading and writing a large number of memory cells in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. In one aspect, data latches associated with the multiple read/write circuits are I/O enabled and coupled in a compact manner for storage and serial transfer. They are implemented by one or more chain of link modules, which can selectively behave as inverters or latches. A method enables the use of a minimum number of link modules by cycling data between a set of master link modules and a substantially smaller set of slave link modules.

An infrared encoder/decoder selects the data rate of a serial transmission of data by changing an input clock speed, setting the operating characteristics of a clock divider circuit by hardware inputs or selecting a clock speed by software commands that program the operating characteristics of a clock divider circuit. Having three alternate ways, two hardware and one software, of selecting the data rate of the serial transmission allows greater flexibility in the application and interfacing of a single integrated circuit package infrared encoder/decoder with all types of digital logic circuits and systems. An encoder/decoder having standard pulse width output and input compatibility with infrared industry standards, e.g., IrDA, and infrared transceivers is achieved in a flexible and cost effective low power integrated circuit package.

A transmission line driver and a serial interface data transmission device including the same are provided. The transmission line driver includes a pre-driver configured to generate and output differential input data signals based on a serial transmission data signal, a differential amplifier configured to receive the differential input data signals and to output differential output data signals, and a common mode controller configured to drive the differential output data signals to a predetermined common mode voltage in an idle mode. Accordingly, power consumption can be reduced and a common mode specification can be supported.

An image capturing system includes an image-capturing unit and a main unit, capable of serial communication therebetween. The main unit generates a first clock signal, converts data to be transmitted to the image-capturing unit into serial data using the first clock signal, and transmits the serial data to the image-capturing unit. The image-capturing unit detects a serial transfer frequency from the received serial signal, reproduces the first clock signal, generates a second clock signal from the reproduced first clock signal, converts a taken image into serial data using the second clock signal, and transmits this data to the main unit. The main unit then reproduces the second clock signal from the serial data transmitted from the image-capturing unit, and utilizes the second clock signal to generate the first clock signal, thereby synchronizing the image-capturing unit and the main unit.

A semiconductor integrated circuit includes a target circuit configured to operate in a normal mode, to form a scan chain to serially transfer a test data through the scan chain, in a scan path test mode, and to form a plurality of sub scan chains to save an internal node data in a memory in a save mode; and a backup control circuit configured to supply to the target circuit, a system clock signal in the normal mode, a test clock signal in the scan path test mode, and a save/recover clock signal in the save mode, and to control the target circuit and the memory such operations in the normal mode, the scan path test mode, and the save mode are performed. The test clock signal is slower than the system clock signal, and the save/recover clock signal is slower than the system clock signal and faster than the test clock signal.

The invention provides a method and system for operating a switch, in which incoming data cells are converted from parallel to serial for synchronous input to a switch interconnect, converted from serial to parallel for parallel switching, converted from parallel to serial for synchronous output from the switch interconnect, and converted from serial to parallel for output. The switch interconnect and its input and output interfaces are controlled by a single frequency source, so that all serial data communication paths into and out of the switch interconnect are phase synchronized to within one clock cycle. A single frequency source for the switch system is coupled to the input interfaces, to output interfaces, and to the switch interconnect. The input interfaces each include a PLL which synchronizes to the single frequency source once for all serial communication to the switch interconnect. The switch interconnect includes one PLL for each input interface which synchronizes to the serial input from that input interface, and one PLL for each output interface which synchronizes to the single frequency source once for all serial communication to the output interface. Similarly, the output interfaces each include a PLL which synchronizes to the serial output from the switch interconnect. The switch interconnect is coupled to the single frequency source and operates in phase therewith.

The present invention provides a memory device with the serial transmission interface and an error correction method for the serial transmission interface. The memory device comprises an error correction mechanism to detect or automatically correct the error earlier to make sure the correctness of the data transmission while the serial transmission interface accesses the memory. Further, the action of error corrections and data re-transmissions performed by the master device can be reduced.

An optical apparatus consisting of a transmitter, receiver, or transceiver, utilizing a multiple level special electrical layer modulation and/or demodulation scheme to significantly lower the bandwidth required for high speed communication and/or parallel interconnect systems. It can be used either to enhance the transmission performance of the transceiver, or to eliminate the need for bulky and/or expensive optical components to lower the cost. It can be used in the design of transponders, transceivers, and active cabling systems, for 10 Gb/s, 40 Gb/s, 100 Gb/s and other high bit rate transmission systems that utilize single mode or multi-mode fibers for serial or parallel transmission of high speed optical signals.

According to the present invention, there is provided a semiconductor integrated circuit having a receiver which receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmission processing on the basis of the clock signal, and having a loop back function of supplying data output from the transmitter to the receiver for test, the receiver, as a CDR circuit, executing control so as to make the phase of the input data coincide with that of the recovery clock by a negative feedback loop having a phase comparator which receives input data and a recovery clock, compares a phase of the input data with that of the recovery clock, and outputs recovery data and a phase comparison result in a serial form, a serial/parallel conversion circuit which receives the phase comparison result, or the phase comparison result and the recovery data from the phase comparator, executes serial/parallel conversion, and outputs the phase comparison result in a parallel form, a digital filer which receives the phase comparison result from the serial/parallel conversion circuit, executes averaging processing for the phase comparison result in a predetermined period, and outputs the phase comparison result, a control circuit which receives the phase comparison result from the digital filer and outputs a control signal to control the phase of the recovery clock, and a phase interpolator which receives the clock signal and generates the recovery clock on the basis of the control signal, and the CDR circuit including a signal output circuit which inputs, to one of the control circuit and the digital filer, a signal to forcibly shift the phase of the recovery data in the negative feedback loop by a predetermined amount, a first counter which counts the number of pulses of the signal output from the signal output circuit in a predetermined period and outputs a first count value, a second counter which counts the number of pulses of the phase comparison result, which has undergone the averaging processing and is output from the digital filer, and outputs a second count value, and a signal processing circuit which receives the first count value and the second count value and compares the first count value with the second count value to determine presence/absence of a capability for absorbing the phase shift generated by the signal.