245 results about "Scan chain" patented technology

An array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

The invention provides a scan chain reordering method, computer equipment and a storage medium. The method comprises the following steps: acquiring a chip design layout; determining a plurality of first scanning chains according to the chip design layout, and combining the plurality of first scanning chains into a second scanning chain; reordering the second scan chain to generate a third scan chain; and determining the number of elements of each first scanning chain, segmenting the third scanning chain according to the number of the elements, and generating a plurality of reordered fourth scanning chains with the same number as the plurality of first scanning chains.

According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

A scan island for automated data retrieval from an integrated circuit (IC) includes a data extraction module configured to extract data from multiple scan chains and random-access memory (RAM) modules in response to a trigger event, storing the data in an external non-volatile storage medium. The scan island further comprises a clock and reset module, which includes a free-running independent clock to enable continuous operation of the scan island upon occurrence of the trigger event, and a local reset module that re-initializes the scan island in a known state following the trigger event without external intervention. The scan island operates as an isolated partition within the IC, ensuring secure and autonomous data retrieval and recovery processes.

Systems, computer program products, and methods are described herein for automated data retrieval from an integrated circuit (IC). An example system extracts, using a scan island (e.g., a partition of the IC that is isolated for data retrieval), data from a plurality of scan chains and a plurality of random-access memories (RAMs) associated with the IC in response to a trigger event associated with the IC; determines, using a data security module associated with the scan island, whether the one or more users are authorized to access the respective portions of the data; and transmits the one or more portions of the data to the one or more users upon verification of their authorization.

Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

The invention provides a scan chain reordering method, computer equipment and a storage medium. The method comprises the following steps: acquiring a chip design layout; determining a scan chain and a plurality of elements contained in the scan chain according to the chip design layout; grouping according to the number of the plurality of elements to generate at least one group of element sets; reordering the at least one group of element sets, and generating at least one sub-chain corresponding to the at least one group of element sets; and splicing the at least one sub-chain so as to complete the reordering of the scanning chain.

A circuit includes a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit. The circuit includes a second plural number (S) of multiplexers operatively coupled to the scan chain, wherein the S is determined asNM,where the M represents a diagnostic resolution. The multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages.

One example includes a circuit. The circuit includes a circuit core configured to perform an operational function and scan-chain registers configured to propagate a set of system-on-chip (SoC) scan data that is input to the circuit generated from an automatic test pattern generator (ATPG) to set a different device state of the circuit core at each shift of the SoC scan data. The circuit further includes a plurality of bidirectional input / output (I / O) circuits each comprising a bidirectional I / O control and testing logic, the testing logic being configured to alternately facilitate input parametric testing and output parametric testing of an I / O pad of the respective bidirectional I / O control at each shift of the set of SoC scan data via a pin parametric measurement unit (PPMU).

The chain vector results are analyzed to identify a faulty scan chain in the circuit and a fault associated with the faulty scan chain. The scan vector results are analyzed to identify one or more faulty scan element candidates on the faulty scan chain. An analog simulation is then performed to identify a faulty component candidate of the one or more faulty scan element candidates. During the process, a component of each of the one or more faulty scan element candidates that is sensitive to a change in signal at an input of each of the one or more faulty scan element candidates may be determined. Physical failure analysis may be performed on the circuit to locate one or more defective components in the faulty component candidates.

Embodiments disclosed herein relate to device testing using scan chains including various flip-flop devices in a multi-bit flip-flop configuration. A circuit device included herein includes a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit is coupled to receive a clock signal and an input, and the second flip-flop circuit is coupled to the first flip-flop sub-circuit. The first flip-flop sub-circuit includes an input sub-circuit, a first latch sub-circuit, a first latch tristate, a second latch sub-circuit, and a first output inverter. The second latch sub-circuit includes a first transmission gate, a first inverter, and a second inverter. The second flip-flop sub-circuit includes a second transmission gate, a first clock tristate, a third latch sub-circuit, a second latch tristate, a fourth latch sub-circuit, and a second output inverter. The fourth latch sub-circuit includes a third transmission gate, a third inverter, and a fourth inverter.

The invention relates to the field of boundary scanning test of laminated chips, in particular to a laminated chip boundary scanning test structure combining IEEE 1838 and IEEE 1149.4 standards, and mainly relates to fault and defect detection of TSV (Through Silicon Via) of a laminated chip connecting part. Chip package registers (DWR) are embedded into the two ends of a through silicon via (TSV) connected with the laminated chip in the laminated chip, a simulation test bus and a corresponding interface circuit are added into the chip to form a scanning chain, and the mixed signal boundary scanning test structure of the laminated chip is formed. When the chip works normally, the test structure does not influence the logic function of the chip; in the testing process, the testing upper computer sends different control instructions, and full-coverage online fault and defect detection of the connectivity of the laminated chips is achieved.

The invention provides a scan chain optimization method, computer equipment, a storage medium and a program product. The method comprises the following steps: determining a plurality of initial scan chains to be optimized; mixing the scan registers of the plurality of initial scan chains to obtain a scan register set; sorting the scan registers in the scan register set based on a scan chain wiring length to obtain a long-chain scan chain; cutting the long-chain scanning chain to obtain a plurality of scanning chain segments in one-to-one correspondence with the plurality of initial scanning chains; sorting the plurality of scanning chain segments according to the cutting sequence, and determining whether the scanning chain bit width corresponding to each scanning chain segment meets the bit width requirement or not; in response to the situation that the scanning chain bit width corresponding to any scanning chain segment does not meet the bit width requirement, the scanning register is moved between the adjacent scanning chain segments until the scanning chain bit widths corresponding to all the scanning chain segments meet the bit width requirement, and multiple optimized target scanning chains are obtained.

Provided are a logic built-in self-test (BIST) circuit that performs a scan test improving test coverage for each clock domain and a semiconductor device including the logic BIST circuit. The logic BIST circuit includes an OR gate configured to receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to output an enable clock irrespective of a function enable signal when the register setting signal has a first logic value, and a scan chain configured to capture an output of a first logic circuit connected to flip-flops according to the enable clock.

Systems, computer program products, and methods are described herein for automated data retrieval from an integrated circuit (IC). An example system receives an alert indicating a trigger event associated with the IC; extracts, using a scan island (e.g., a partition of the IC that is isolated for data retrieval), data from a plurality of scan chains and a plurality of random-access memories (RAMs) associated with the IC in response to receiving the alert; stores the data in an external non-volatile storage media; and reboots the IC upon storing the data in the external non-volatile storage media. In this way, embodiments of the present invention offer a scalable and secure method for real-time data extraction and processing in the event of an integrated circuit malfunction, improving diagnostics while ensuring cost-effectiveness and data security.

The present application discloses a system and a method for performing a scan chain ECO, the method includes: receiving an original netlist input by a user as first input information, the original netlist contains original scan chain information; receiving a register modification list and a scan DEF file input by the user as second input information, wherein the register modification list is configured to indicate register information to be up-chained and / or register information to be down-chained; modifying the original netlist based on the first input information and the second input information, to complete up-chaining and / or down-chaining of a list of registers in the second input information to obtain a modified scan chain netlist; and receiving the modified scan chain netlist and returning the modified scan chain netlist to the user.

A first set of features may be extracted from a first integrated circuit (IC) design. A trained machine learning (ML) model may predict a set of ranked test-case configurations for the first IC design based on the first set of features. A test-case configuration may correspond to a count of scan chain input and output ports and a scan chain length value.

The invention provides a test vector generation method and device in circuit design, and the method comprises the steps: obtaining a scanning chain group in the circuit design, the scanning chain group comprises N scanning chains, and each scanning chain in the N scanning chains comprises at least one register; value constraint is carried out on at least one register of each scanning chain in the N scanning chains according to a preset code pattern, the value constraint is used for limiting the value of the at least one register to be 0 or 1, the length of continuous 0 or the length of continuous 1 in the preset code pattern does not exceed Q, and Q is larger than or equal to 1; and according to the register subjected to value constraint, solving to obtain a test vector corresponding to the scan chain group. The method provided by the invention can realize high-precision diagnosis.

The embodiment of the invention provides a detection method and device for a storage unit of a chip, and the method comprises the steps: generating a scanning mode entering instruction, and calling a joint test behavior organization interface to control the chip to enter a scanning mode based on the scanning mode entering instruction; in a scan mode, generating a scan chain for the storage unit through the register; the scan chain comprises a first storage built-in self-test scan chain which is generated for the register and aims at the native storage unit, and a second storage built-in self-test scan chain which aims at the customized storage unit; when it is judged that the storage unit has a fault, scanning data aiming at the storage unit is obtained through the first storage built-in self-test scanning chain and the second storage built-in self-test scanning chain, and a first count value is obtained by resetting a counter; the storage unit is detected based on the scanning data and the first count value, multiple diagnosis modes can be provided for detecting the storage unit, and therefore the detection efficiency of the on-chip storage unit is improved.

The present disclosure describes systems and methods for forming scan chains. The system includes a memory and a processor communicatively coupled to the memory. The processor receives a circuit design that includes a plurality of scan cells. The plurality of scan cells includes a first scan cell and a first set of scan cells coupled logically to the first scan cell. The processor forms the plurality of scan cells into a first scan chain such that the first set of scan cells are placed outside an extended neighborhood of the first scan cell. The extended neighborhood of the first scan cell includes (i) scan cells that are downstream of the first scan cell in the first scan chain and (ii) a scan cell that is adjacent to and upstream of the first scan cell in the first scan chain.

An integrated circuit device includes scan chains and path margin monitor units (PMUs) on a single die. The scan chains test signal paths in the integrated circuit device. The PMUs include path monitor circuitry and self-test circuitry. The path monitor circuitry monitor delays of signals propagating along the signal paths. The self-test circuitry test the path monitor circuitry and report the test results via a communications path other than the scan chains.

According to an embodiment, a method for testing using scan chains, without an independent scan enable pin, is proposed. The method includes selectively indicating a capture phase and a load / unload phase for the scan chain based on an encoding of a scan enable signal in an expected signal and a masking signal; loading test parameters to the scan chain during the load / unload phase; operating the scan chain under functional mode during the capture phase; and generating an error signal based on comparing an output of the scan chain during an unload phase with the expected signal, wherein the masking signal is used to mask the output of the scan chain for cycles with invalid results.

A semiconductor device includes a scan data output and a scan chain having length n. Scan data bits appear sequentially at the scan data output responsive to a scan clock when the device is in a scan mode. Initial masking circuitry is operable to obscure, responsive to the device transitioning from a non-scan mode to the scan mode, a first n bits of the scan data appearing at the scan data output and not to obscure n+1st and subsequent bits of the scan data appearing at the scan data output. Infinite masking circuitry is operable to obscure, responsive to an infinite masking trigger, all scan data bits appearing at the scan data output until a reset of the device occurs. Monitoring and security enforcement circuitry is operable to detect a configuration change and to generate the infinite masking trigger if the detected change corresponds to a potential security risk.

A subsystem with an array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem.A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

The application provides a scan test method, comprising: constructing a single stuck-at fault scan forest, the scan forest comprising a plurality of scan inputs and a plurality of scan trees, each scan input being driven by an ATE; each pin of the ATE driving a plurality of demodulators, each demodulator driving a plurality of scan trees, each scan tree corresponding to each demodulator being controlled by different clock signals of a gate logic, each scan tree comprising a plurality of scan chains, and each scan chain comprising a plurality of scan flip-flops; and based on the constructed single stuck-at fault scan forest, placing a test. The method can effectively reduce the calculation time and memory overhead.

A scan flip-flop configured to generate physically unclonable function (PUF) data according to the present disclosure includes a multiplexer configured to provide an internal signal through an input switch, a first latch circuit configured to latch the internal signal, wherein the first latch circuit comprises a first inverter, a second inverter, a first switch connected in parallel with the first inverter, and a second switch connected in series with the second inverter. Additionally, a second latch circuit configured to latch an output of the first latch circuit and output a latched value, wherein the second latch circuit comprises a third inverter, a fourth inverter, an output inverter connected in series with the third inverter, and a fourth switch connected in series with the fourth inverter. A third switch is configured to switch between the first latch circuit and the second latch circuit.

The invention discloses a test evaluation model, method and system for a path planning algorithm, and belongs to the field of algorithm test. Comprising the following steps: connecting a plurality of functions and scenes into a plurality of test scan chains; and testing the intelligent iterative optimization algorithm through each scan chain. The test scan chain comprises three packaging function chains, a packaging function test chain with noise and a metamorphic test chain based on a path planning scene, and the three packaging function chains adopt a single-mode function, a multi-mode function and a composite function for packaging. A systematic method is provided to compare and analyze the performance of different algorithms in multiple dimensions by performing comprehensive test and evaluation on multiple intelligent iterative optimization algorithms.

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.