206 results about "Scan chain" patented technology

The invention provides a scan chain reordering method, computer equipment and a storage medium. The method comprises the following steps: acquiring a chip design layout; determining a plurality of first scanning chains according to the chip design layout, and combining the plurality of first scanning chains into a second scanning chain; reordering the second scan chain to generate a third scan chain; and determining the number of elements of each first scanning chain, segmenting the third scanning chain according to the number of the elements, and generating a plurality of reordered fourth scanning chains with the same number as the plurality of first scanning chains.

According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

The invention provides a scan chain reordering method, computer equipment and a storage medium. The method comprises the following steps: acquiring a chip design layout; determining a scan chain and a plurality of elements contained in the scan chain according to the chip design layout; grouping according to the number of the plurality of elements to generate at least one group of element sets; reordering the at least one group of element sets, and generating at least one sub-chain corresponding to the at least one group of element sets; and splicing the at least one sub-chain so as to complete the reordering of the scanning chain.

One example includes a circuit. The circuit includes a circuit core configured to perform an operational function and scan-chain registers configured to propagate a set of system-on-chip (SoC) scan data that is input to the circuit generated from an automatic test pattern generator (ATPG) to set a different device state of the circuit core at each shift of the SoC scan data. The circuit further includes a plurality of bidirectional input / output (I / O) circuits each comprising a bidirectional I / O control and testing logic, the testing logic being configured to alternately facilitate input parametric testing and output parametric testing of an I / O pad of the respective bidirectional I / O control at each shift of the set of SoC scan data via a pin parametric measurement unit (PPMU).

The chain vector results are analyzed to identify a faulty scan chain in the circuit and a fault associated with the faulty scan chain. The scan vector results are analyzed to identify one or more faulty scan element candidates on the faulty scan chain. An analog simulation is then performed to identify a faulty component candidate of the one or more faulty scan element candidates. During the process, a component of each of the one or more faulty scan element candidates that is sensitive to a change in signal at an input of each of the one or more faulty scan element candidates may be determined. Physical failure analysis may be performed on the circuit to locate one or more defective components in the faulty component candidates.

Embodiments disclosed herein relate to device testing using scan chains including various flip-flop devices in a multi-bit flip-flop configuration. A circuit device included herein includes a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit is coupled to receive a clock signal and an input, and the second flip-flop circuit is coupled to the first flip-flop sub-circuit. The first flip-flop sub-circuit includes an input sub-circuit, a first latch sub-circuit, a first latch tristate, a second latch sub-circuit, and a first output inverter. The second latch sub-circuit includes a first transmission gate, a first inverter, and a second inverter. The second flip-flop sub-circuit includes a second transmission gate, a first clock tristate, a third latch sub-circuit, a second latch tristate, a fourth latch sub-circuit, and a second output inverter. The fourth latch sub-circuit includes a third transmission gate, a third inverter, and a fourth inverter.

The invention provides a scan chain optimization method, computer equipment, a storage medium and a program product. The method comprises the following steps: determining a plurality of initial scan chains to be optimized; mixing the scan registers of the plurality of initial scan chains to obtain a scan register set; sorting the scan registers in the scan register set based on a scan chain wiring length to obtain a long-chain scan chain; cutting the long-chain scanning chain to obtain a plurality of scanning chain segments in one-to-one correspondence with the plurality of initial scanning chains; sorting the plurality of scanning chain segments according to the cutting sequence, and determining whether the scanning chain bit width corresponding to each scanning chain segment meets the bit width requirement or not; in response to the situation that the scanning chain bit width corresponding to any scanning chain segment does not meet the bit width requirement, the scanning register is moved between the adjacent scanning chain segments until the scanning chain bit widths corresponding to all the scanning chain segments meet the bit width requirement, and multiple optimized target scanning chains are obtained.

Provided are a logic built-in self-test (BIST) circuit that performs a scan test improving test coverage for each clock domain and a semiconductor device including the logic BIST circuit. The logic BIST circuit includes an OR gate configured to receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to output an enable clock irrespective of a function enable signal when the register setting signal has a first logic value, and a scan chain configured to capture an output of a first logic circuit connected to flip-flops according to the enable clock.

The present application discloses a system and a method for performing a scan chain ECO, the method includes: receiving an original netlist input by a user as first input information, the original netlist contains original scan chain information; receiving a register modification list and a scan DEF file input by the user as second input information, wherein the register modification list is configured to indicate register information to be up-chained and / or register information to be down-chained; modifying the original netlist based on the first input information and the second input information, to complete up-chaining and / or down-chaining of a list of registers in the second input information to obtain a modified scan chain netlist; and receiving the modified scan chain netlist and returning the modified scan chain netlist to the user.

A first set of features may be extracted from a first integrated circuit (IC) design. A trained machine learning (ML) model may predict a set of ranked test-case configurations for the first IC design based on the first set of features. A test-case configuration may correspond to a count of scan chain input and output ports and a scan chain length value.

The invention provides a test vector generation method and device in circuit design, and the method comprises the steps: obtaining a scanning chain group in the circuit design, the scanning chain group comprises N scanning chains, and each scanning chain in the N scanning chains comprises at least one register; value constraint is carried out on at least one register of each scanning chain in the N scanning chains according to a preset code pattern, the value constraint is used for limiting the value of the at least one register to be 0 or 1, the length of continuous 0 or the length of continuous 1 in the preset code pattern does not exceed Q, and Q is larger than or equal to 1; and according to the register subjected to value constraint, solving to obtain a test vector corresponding to the scan chain group. The method provided by the invention can realize high-precision diagnosis.

According to an embodiment, a method for testing using scan chains, without an independent scan enable pin, is proposed. The method includes selectively indicating a capture phase and a load / unload phase for the scan chain based on an encoding of a scan enable signal in an expected signal and a masking signal; loading test parameters to the scan chain during the load / unload phase; operating the scan chain under functional mode during the capture phase; and generating an error signal based on comparing an output of the scan chain during an unload phase with the expected signal, wherein the masking signal is used to mask the output of the scan chain for cycles with invalid results.

A semiconductor device includes a scan data output and a scan chain having length n. Scan data bits appear sequentially at the scan data output responsive to a scan clock when the device is in a scan mode. Initial masking circuitry is operable to obscure, responsive to the device transitioning from a non-scan mode to the scan mode, a first n bits of the scan data appearing at the scan data output and not to obscure n+1st and subsequent bits of the scan data appearing at the scan data output. Infinite masking circuitry is operable to obscure, responsive to an infinite masking trigger, all scan data bits appearing at the scan data output until a reset of the device occurs. Monitoring and security enforcement circuitry is operable to detect a configuration change and to generate the infinite masking trigger if the detected change corresponds to a potential security risk.

A subsystem with an array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem.A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

The application provides a scan test method, comprising: constructing a single stuck-at fault scan forest, the scan forest comprising a plurality of scan inputs and a plurality of scan trees, each scan input being driven by an ATE; each pin of the ATE driving a plurality of demodulators, each demodulator driving a plurality of scan trees, each scan tree corresponding to each demodulator being controlled by different clock signals of a gate logic, each scan tree comprising a plurality of scan chains, and each scan chain comprising a plurality of scan flip-flops; and based on the constructed single stuck-at fault scan forest, placing a test. The method can effectively reduce the calculation time and memory overhead.

A scan flip-flop configured to generate physically unclonable function (PUF) data according to the present disclosure includes a multiplexer configured to provide an internal signal through an input switch, a first latch circuit configured to latch the internal signal, wherein the first latch circuit comprises a first inverter, a second inverter, a first switch connected in parallel with the first inverter, and a second switch connected in series with the second inverter. Additionally, a second latch circuit configured to latch an output of the first latch circuit and output a latched value, wherein the second latch circuit comprises a third inverter, a fourth inverter, an output inverter connected in series with the third inverter, and a fourth switch connected in series with the fourth inverter. A third switch is configured to switch between the first latch circuit and the second latch circuit.

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.

The invention discloses a multi-bit trigger design method for a standard cell library and a scan chain, and belongs to the technical field of integrated circuits, the multi-bit trigger design method for the standard cell library comprises the following steps: providing a plurality of single-bit triggers, and setting the flipping rate of each single-bit trigger; arranging the single-bit triggers, and placing the single-bit trigger with the lowest flipping rate at the last position; the single-bit triggers are serially connected into a scan chain according to the sequence, the first single-bit trigger is used for accessing input data and a scan chain control signal, and the output end of the last single-bit trigger is used for outputting data. By arranging the triggers with the lowest flipping rate at the output end, the DFT dynamic power consumption can be reduced, and the Power signoff can be optimized.

The embodiment of the utility model relates to a scan chain circuit and a control circuit for loading a repetitive sequence to a trigger. The scan chain circuit is used for inputting a repetitive bit sequence to a trigger sequence comprising a multi-bit trigger and a unit trigger. One example includes a control circuit including a bit counter, a multiplexer, a first set of control circuits, and a second set of control circuits.

An apparatus includes a test controller and a scan chain coupled to the test controller. The scan chain includes a first segment and a second segment. The apparatus further includes circuitry coupled to the test controller and the scan chain. The circuitry is configured to provide, to the second segment, an output of the first segment in connection with a first test. The circuitry is further configured to provide, to the second segment, a test pattern in connection with a second test.

Methods and systems for positioning a welding head with respect to a groove in a rotating circular workpiece during an arc welding process, wherein a chain or other flexible measuring device is coupled about the workpiece. First and second scanners are respectively used to scan the groove and a link of the chain at a first rotational position of the workpiece. A third scanner is used to scan the chain link at a second rotational position of the workpiece that corresponds to the welding location. The scanners are collectively used to determine a profile of the groove and a change in position of the chain link between the first and second rotational positions of the workpiece. Data acquired through the scanning processes are used to generate instructions deliverable to a positioning system of the welding head to position the welding head so that arc welding properly occurs inside the groove.

The present application discloses a fault scan chain shielding method based on a compression environment, which relates to the field of EDA detection. The method determines the total number of chip scan chains and the maximum number of fault scan chains, generates a vector set to be tested and a shielding signal; selects test vectors in sequence, performs fault shielding diagnosis on the scan chain according to the shielding signal and the fault arrangement combination, and determines the target scan chain; updates the shielding signal, and generates a target test vector set and a target shielding signal set when the detection fault coverage meets the system-set threshold; the shielding signal decoder performs a shielding test on the target scan chain according to the target test vector and the target shielding signal, and diagnoses and analyzes the scan chain fault according to the compression response output of the scan chain compressor. The test vector and shielding signal are determined in accordance with the principle that the scan chain with higher fault detection weight needs to be observed first, and the scan chain with higher occurrence frequency in the combination with lower shielding weight value needs to be shielded more, which can greatly improve the diagnostic efficiency and diagnostic accuracy.

The invention discloses a circuit structure for a semiconductor wafer process authentication test. The circuit structure comprises an input stage circuit, an output stage circuit and a plurality of scanning chains connected between the input stage circuit and the output stage circuit, the scanning chain comprises a plurality of scanning units connected in series and a tail selector, each scanning unit comprises an alternative transverse selector and a D trigger, and each scanning unit further comprises an alternative longitudinal selector and a tested unit; the input stage circuit is used for selecting one path of input scanning signal in each scanning chain for scanning; and the output stage circuit is used for selecting and outputting one path of scanned signal in each scanning chain. The invention also discloses a semiconductor silicon wafer failure analysis test method. The method not only can be used for analyzing and positioning the circuit yield problem of a fault chip caused by defects in semiconductor process steps, but also can be used for analyzing and positioning the low yield problem of a logic gate standard cell and a layout pattern in a standard cell library.

An integrated circuit includes first and second data storage circuits, first, second, and third shadow storage circuits, and first, second, and third multiplexer circuits. The first multiplexer circuit is configurable to provide a state of a data signal from the first data storage circuit to the first shadow storage circuit in a snapshot mode. The second multiplexer circuit is coupled between an output of the second data storage circuit and an input of the second shadow storage circuit. The third multiplexer circuit is coupled to the second multiplexer circuit. The third multiplexer circuit is configurable to provide a state of an output signal of the first shadow storage circuit to an input of the third shadow storage circuit in a scan mode bypassing the second shadow storage circuit.

Embodiments of the present disclosure are directed to scan chain systems and methods for inputting repeated sequences of bits to a sequence of flip flops that include multi-bit flip flops and single bit flip flops. One example includes a control circuit that includes a bit counter, a multiplexer, a first group control circuit, and a second group control circuit.

This invention discloses a low-scan-power scanning unit and scanning chain, belonging to the field of integrated circuit design-for-test (DTBT). The invention uses a low-scan-power scanning unit, adding an OR gate to control the switching activity of two tri-state gates in the secondary latch unit during the scanning phase, and using a high-threshold PMOS as a power supply gating to control the power supply VDD of the two inverters inside the secondary latch unit, thus reducing the dynamic power consumption of the secondary latch and unnecessary dynamic power consumption of the combinational logic during the scanning phase. Additionally, a test vector output port P is added, whose signal originates from the output of the primary latch unit inside the scanning unit, reducing the transmission path delay during the scanning phase. This invention is applicable to the DTBT stage of digital circuits; by simply adding an OR gate and a high-threshold PMOS, without affecting the original logic circuit function, it achieves the goal of reducing dynamic power consumption during the shift phase.

The invention discloses a programmable online kernel self-diagnosis implementation method and a storage medium. The method comprises the following steps: S1, constructing a hardware architecture; s2, test excitation and signature pre-generation; s3, software programmable configuration is carried out; the CPU sets a test mode, the number of execution SEEDs, test granularity, clock distribution and start / stop through the configuration register; s4, preparing before testing; s5, executing an online test; reading SEED from the ROM, generating excitation by a Pattern generator, loading the excitation to a kernel scan chain, capturing output, generating an MISR, and comparing the MISR with a GOLDEN MISR; s6, fault processing and a safety mechanism; and S7, recovering after testing. The storage medium is realized based on the method. The method has the advantages of simple principle, wide application range, good flexibility, high coverage rate and the like.

In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.