86 results about "Scan chain" patented technology

The present application discloses a system and a method for performing a scan chain ECO, the method includes: receiving an original netlist input by a user as first input information, the original netlist contains original scan chain information; receiving a register modification list and a scan DEF file input by the user as second input information, wherein the register modification list is configured to indicate register information to be up-chained and / or register information to be down-chained; modifying the original netlist based on the first input information and the second input information, to complete up-chaining and / or down-chaining of a list of registers in the second input information to obtain a modified scan chain netlist; and receiving the modified scan chain netlist and returning the modified scan chain netlist to the user.

A semiconductor device includes a scan data output and a scan chain having length n. Scan data bits appear sequentially at the scan data output responsive to a scan clock when the device is in a scan mode. Initial masking circuitry is operable to obscure, responsive to the device transitioning from a non-scan mode to the scan mode, a first n bits of the scan data appearing at the scan data output and not to obscure n+1st and subsequent bits of the scan data appearing at the scan data output. Infinite masking circuitry is operable to obscure, responsive to an infinite masking trigger, all scan data bits appearing at the scan data output until a reset of the device occurs. Monitoring and security enforcement circuitry is operable to detect a configuration change and to generate the infinite masking trigger if the detected change corresponds to a potential security risk.

A subsystem with an array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem.A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.

The invention discloses a multi-bit trigger design method for a standard cell library and a scan chain, and belongs to the technical field of integrated circuits, the multi-bit trigger design method for the standard cell library comprises the following steps: providing a plurality of single-bit triggers, and setting the flipping rate of each single-bit trigger; arranging the single-bit triggers, and placing the single-bit trigger with the lowest flipping rate at the last position; the single-bit triggers are serially connected into a scan chain according to the sequence, the first single-bit trigger is used for accessing input data and a scan chain control signal, and the output end of the last single-bit trigger is used for outputting data. By arranging the triggers with the lowest flipping rate at the output end, the DFT dynamic power consumption can be reduced, and the Power signoff can be optimized.

The embodiment of the utility model relates to a scan chain circuit and a control circuit for loading a repetitive sequence to a trigger. The scan chain circuit is used for inputting a repetitive bit sequence to a trigger sequence comprising a multi-bit trigger and a unit trigger. One example includes a control circuit including a bit counter, a multiplexer, a first set of control circuits, and a second set of control circuits.

An apparatus includes a test controller and a scan chain coupled to the test controller. The scan chain includes a first segment and a second segment. The apparatus further includes circuitry coupled to the test controller and the scan chain. The circuitry is configured to provide, to the second segment, an output of the first segment in connection with a first test. The circuitry is further configured to provide, to the second segment, a test pattern in connection with a second test.

Methods and systems for positioning a welding head with respect to a groove in a rotating circular workpiece during an arc welding process, wherein a chain or other flexible measuring device is coupled about the workpiece. First and second scanners are respectively used to scan the groove and a link of the chain at a first rotational position of the workpiece. A third scanner is used to scan the chain link at a second rotational position of the workpiece that corresponds to the welding location. The scanners are collectively used to determine a profile of the groove and a change in position of the chain link between the first and second rotational positions of the workpiece. Data acquired through the scanning processes are used to generate instructions deliverable to a positioning system of the welding head to position the welding head so that arc welding properly occurs inside the groove.

Embodiments of the present disclosure are directed to scan chain systems and methods for inputting repeated sequences of bits to a sequence of flip flops that include multi-bit flip flops and single bit flip flops. One example includes a control circuit that includes a bit counter, a multiplexer, a first group control circuit, and a second group control circuit.

This invention discloses a low-scan-power scanning unit and scanning chain, belonging to the field of integrated circuit design-for-test (DTBT). The invention uses a low-scan-power scanning unit, adding an OR gate to control the switching activity of two tri-state gates in the secondary latch unit during the scanning phase, and using a high-threshold PMOS as a power supply gating to control the power supply VDD of the two inverters inside the secondary latch unit, thus reducing the dynamic power consumption of the secondary latch and unnecessary dynamic power consumption of the combinational logic during the scanning phase. Additionally, a test vector output port P is added, whose signal originates from the output of the primary latch unit inside the scanning unit, reducing the transmission path delay during the scanning phase. This invention is applicable to the DTBT stage of digital circuits; by simply adding an OR gate and a high-threshold PMOS, without affecting the original logic circuit function, it achieves the goal of reducing dynamic power consumption during the shift phase.

The invention discloses a programmable online kernel self-diagnosis implementation method and a storage medium. The method comprises the following steps: S1, constructing a hardware architecture; s2, test excitation and signature pre-generation; s3, software programmable configuration is carried out; the CPU sets a test mode, the number of execution SEEDs, test granularity, clock distribution and start / stop through the configuration register; s4, preparing before testing; s5, executing an online test; reading SEED from the ROM, generating excitation by a Pattern generator, loading the excitation to a kernel scan chain, capturing output, generating an MISR, and comparing the MISR with a GOLDEN MISR; s6, fault processing and a safety mechanism; and S7, recovering after testing. The storage medium is realized based on the method. The method has the advantages of simple principle, wide application range, good flexibility, high coverage rate and the like.

A device comprises a scan chain and a device circuit. The scan chain includes a plurality of sequential elements and a diagnostic hardware circuit. The sequential elements are connected serially and grouped into a plurality of segments. The diagnostic hardware circuit includes a plurality of circuit components, each connected to a sequential element of a respective segment. The diagnostic hardware circuit identifies a faulty segment of the scan chain during a diagnostic mode. Test pattern data is serially shifted through the scan chain to isolate the faulty sequential element of the defective segment during the diagnostic mode. The device circuit is connected to the scan chain, performs one or more circuit functions, and generates functional data that is sequentially shifted through the scan chain during a functional mode.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

An integrated-circuit chip comprises a plurality of scan flip-flops and a retention cell. The chip is configured to have a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip, and to have a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain for use during scan-chain testing of the integrated-circuit chip. The chip further comprises on-chip test circuitry arranged to generate and output a save signal, a clock signal, and a restore signal to the retention cell, for testing the retention cell during scan-chain testing of the integrated-circuit chip.

The invention belongs to the technical field of integrated circuit testing, and discloses an in-memory computing chip testing device and method based on a scan chain architecture, and the method comprises the steps: employing three groups of independent scan chains (input, weight and partial sum) to cooperate with an on-chip configurable controller (Config Regs + FSM), and achieving the automatic testing of a memory Mode and a computing Mode of an in-memory computing macro cell (CIM Macro). According to the technical scheme provided by the invention, the storage and calculation functions of the CIM chip can be comprehensively verified with lower hardware overhead and lower external IO rate.

Embodiments of the present disclosure relate to scan circuits and methods. In one embodiment, a method of performing a scan includes entering a scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and de-asserting a scan enable signal to perform a shift and a capture operation, respectively, on the first scan chain; controlling a further scan flip-flop with the first scan chain while applying the test pattern through the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect a fault.

A system includes a memory that stores instructions and a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a circuit layout module that generates an initial circuit layout in response to a circuit netlist. The circuit netlist includes functional logic, the test-point nodes interconnecting portions of the functional logic, and a plurality of test-point flops associated with scan-chains. The EDA application also includes a test-point flop allocation module that divides the test-point nodes into test-point sharing groups based on a physical location of the test-point nodes and based on a test-point allocation parameter. The module relocates each of the test-point flops proximal to a test-point sharing group to generate an adjusted circuit layout associated with the circuit design. The adjusted circuit layout is employable to fabricate an integrated circuit (IC) chip.

An example device described herein includes first functional circuitry, second functional circuitry, and a shift register coupled to the first functional circuitry. The shift register of the example device includes a flip-flop, the flip-flop including a scan-in input coupled to the second functional circuitry, a scan-enable input, and an output. The example device also includes first test circuitry coupled to the scan-enable input and configured to cause the flip-flop to output a first value received by the flip-flop at the scan-in input from the second functional circuitry.

The invention provides a test circuit and a circuit test method, the test circuit and the circuit test method are applied to a to-be-tested circuit, the to-be-tested circuit comprises a pseudo-random vector generator and K scan chains, the test circuit comprises a random constant generator, a low power consumption controller and a first multiplexer, and the random constant generator is used for generating a first test vector; the low-power-consumption controller is used for generating a low-power-consumption control signal, and the low-power-consumption control signal is used for setting each scanning chain as a low-power-consumption scanning chain or a non-low-power-consumption scanning chain according to the correlation degree between each scanning chain in the K scanning chains and a fault in the circuit to be tested; the first multiplexer is used for inputting a first test vector for the first scan chain under the condition that the first scan chain is a low-power-consumption scan chain, or inputting a second test vector for the first scan chain under the condition that the first scan chain is a non-low-power-consumption scan chain, and the second test vector is a random binary sequence. The test circuit provided by the invention can reduce the power consumption of circuit test.

A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.

The application provides a scan chain design method, comprising: obtaining a plurality of test points according to a gate level netlist; determining positive integers M and N, wherein M and N are not greater than the number X of the test points; taking out M and N test points as first and second groups of test points respectively from the test points according to a priority condition; obtaining a first test coverage and a first test pattern number according to the first group of test points, and obtaining a second test coverage and a second test pattern number according to the second group of test points; obtaining a predicted test coverage curve according to the first and second test coverages; determining an optimized number O according to the predicted test coverage curve, the first and second test pattern numbers, wherein O is not greater than the number X; and selecting O test points from the test points according to the priority condition and the optimized number O, and configuring a scan chain in this way.

The invention discloses an internal scan chain generation method and device for an integrated chip in a 2.5 D / 3D circuit, a storage medium and equipment. The integrated chip comprises a plurality of cores, and each core is connected to each test bus through a controllable unit; the method comprises the following steps: receiving scan chain demand information; based on the received test demand information, by taking minimization of the overall test duration of the integrated chip as a target, utilizing a preset scan chain configuration model to obtain scan chain configuration information; and based on the obtained scan chain configuration information, controlling a corresponding controllable unit to generate a corresponding scan chain. By adopting the scheme, the configuration flexibility of the scan chain in the integrated chip can be improved so as to meet a dynamically changing integrated environment in a 2.5 D / 3D circuit.

The application relates to the field of integrated circuit design and test technology, and discloses a scan chain port layout optimization method, device and electronic equipment. The core of the method comprises the following steps: an intelligent nearest matching step of a scan chain port and a scan chain, in which a nearest unassigned scan chain is searched as a candidate by sequentially selecting a scan chain port, and it is judged whether the scan chain is matched according to a preset distance constraint threshold, so that a first matching relationship is established; and a step of performing dynamic port rearrangement on the unassigned ports and scan chains that are not successfully matched to generate a second matching relationship. Through a two-stage adaptive matching mechanism, physical perception optimization of the scan chain connection relationship is realized, wiring congestion and interconnection delay are significantly reduced, and the robustness of the design process and the convergence of the test timing are improved.

A memory is provided with a read data latch that latches a read data signal during a read operation to the memory responsive to a first binary value of a bypass signal. During a design-for-test bypass mode for the memory, a write data latch latches a data in signal from a scan chain to provide a write data signal. The read data latch responds to a second binary value of the bypass signal by latching the write data signal.

The present disclosure relates to a data dump circuit, a sensing and latching circuit, and a debug circuit. A data dump circuit is coupled to a combinational logic circuit and includes a sensing and latching circuit and a scan chain circuit. The sensing and latching circuit senses a characteristic value of the combinational logic circuit and generates a scan enable signal upon determining that the characteristic value changes. The scan chain circuit is coupled to a plurality of flip-flops and operates in a scan mode in response to the scan enable signal. In the scan mode, the scan chain circuit sequentially outputs values stored in the flip-flops as dump data.

The invention relates to the technical field of integrated circuit design and testing, and discloses a scan chain port layout optimization method and device and electronic equipment. The method comprises the following steps: sequentially selecting scan chain ports, searching an unallocated scan chain with the shortest physical distance as a candidate, and judging whether the unallocated scan chain is matched or not according to a preset distance constraint threshold value, so as to establish a first matching relationship; and executing dynamic port rearrangement on the ports which are not successfully matched and the scan chain to generate a second matching relationship. Through a two-stage adaptive matching mechanism, physical perception optimization of a scan chain connection relationship is realized, wiring congestion and interconnection delay are significantly reduced, and robustness of a design process and convergence of a test time sequence are improved.

The embodiment of the application provides an engineering modified device and method, relates to the chip design field, and the device comprises: the device comprises: a searching unit and a first operation unit, the searching unit performs first search processing to search for a similar register based on the lowest level of a second register in a second SYN netlist instantiation hierarchy; when the first search processing result is that the similar register searched is chained in the first scan chain, the first operation unit connects the port for DFT of the second register with the port for DFT of the similar register in the first scan chain. Based on the scheme, the second register is inserted into the scan chain through the device, and the DFT controllable signal point with consistent function logic is selected for the second register, the time sequence impact on the original circuit is small, the device is strong in universality, high in efficiency, and suitable for the chip under different design templates and the scene with a large number of newly added registers.

The present application relates to multi-mode redundancy reinforced circuit, specifically relates to a method for verifying the function of multi-mode redundancy reinforced circuit by using scan chain structure, constructing scan chain structure for original function register; performing multi-mode redundancy replacement operation on original function register step by step, forming a plurality of redundancy reinforced units with scan chain structure; when verifying the function, automatically generating test excitation sequence and inputting the first group of redundancy reinforced units, transmitting data on the plurality of redundancy reinforced units, and outputting test response sequence from the last group of redundancy reinforced units; verifying the function of multi-mode redundancy reinforced circuit by comparing test excitation sequence with test response sequence; the technical scheme provided by the present application can effectively overcome the defects of the prior art that it is difficult to effectively and conveniently verify the functionality of multi-mode redundancy reinforced circuit.