142 results about "Scan chain" patented technology

The invention provides a scan chain optimization method, computer equipment, a storage medium and a program product. The method comprises the following steps: determining a plurality of initial scan chains to be optimized; mixing the scan registers of the plurality of initial scan chains to obtain a scan register set; sorting the scan registers in the scan register set based on a scan chain wiring length to obtain a long-chain scan chain; cutting the long-chain scanning chain to obtain a plurality of scanning chain segments in one-to-one correspondence with the plurality of initial scanning chains; sorting the plurality of scanning chain segments according to the cutting sequence, and determining whether the scanning chain bit width corresponding to each scanning chain segment meets the bit width requirement or not; in response to the situation that the scanning chain bit width corresponding to any scanning chain segment does not meet the bit width requirement, the scanning register is moved between the adjacent scanning chain segments until the scanning chain bit widths corresponding to all the scanning chain segments meet the bit width requirement, and multiple optimized target scanning chains are obtained.

Provided are a logic built-in self-test (BIST) circuit that performs a scan test improving test coverage for each clock domain and a semiconductor device including the logic BIST circuit. The logic BIST circuit includes an OR gate configured to receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to output an enable clock irrespective of a function enable signal when the register setting signal has a first logic value, and a scan chain configured to capture an output of a first logic circuit connected to flip-flops according to the enable clock.

The present application discloses a system and a method for performing a scan chain ECO, the method includes: receiving an original netlist input by a user as first input information, the original netlist contains original scan chain information; receiving a register modification list and a scan DEF file input by the user as second input information, wherein the register modification list is configured to indicate register information to be up-chained and / or register information to be down-chained; modifying the original netlist based on the first input information and the second input information, to complete up-chaining and / or down-chaining of a list of registers in the second input information to obtain a modified scan chain netlist; and receiving the modified scan chain netlist and returning the modified scan chain netlist to the user.

According to an embodiment, a method for testing using scan chains, without an independent scan enable pin, is proposed. The method includes selectively indicating a capture phase and a load / unload phase for the scan chain based on an encoding of a scan enable signal in an expected signal and a masking signal; loading test parameters to the scan chain during the load / unload phase; operating the scan chain under functional mode during the capture phase; and generating an error signal based on comparing an output of the scan chain during an unload phase with the expected signal, wherein the masking signal is used to mask the output of the scan chain for cycles with invalid results.

A semiconductor device includes a scan data output and a scan chain having length n. Scan data bits appear sequentially at the scan data output responsive to a scan clock when the device is in a scan mode. Initial masking circuitry is operable to obscure, responsive to the device transitioning from a non-scan mode to the scan mode, a first n bits of the scan data appearing at the scan data output and not to obscure n+1st and subsequent bits of the scan data appearing at the scan data output. Infinite masking circuitry is operable to obscure, responsive to an infinite masking trigger, all scan data bits appearing at the scan data output until a reset of the device occurs. Monitoring and security enforcement circuitry is operable to detect a configuration change and to generate the infinite masking trigger if the detected change corresponds to a potential security risk.

A subsystem with an array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem.A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

The application provides a scan test method, comprising: constructing a single stuck-at fault scan forest, the scan forest comprising a plurality of scan inputs and a plurality of scan trees, each scan input being driven by an ATE; each pin of the ATE driving a plurality of demodulators, each demodulator driving a plurality of scan trees, each scan tree corresponding to each demodulator being controlled by different clock signals of a gate logic, each scan tree comprising a plurality of scan chains, and each scan chain comprising a plurality of scan flip-flops; and based on the constructed single stuck-at fault scan forest, placing a test. The method can effectively reduce the calculation time and memory overhead.

A scan flip-flop configured to generate physically unclonable function (PUF) data according to the present disclosure includes a multiplexer configured to provide an internal signal through an input switch, a first latch circuit configured to latch the internal signal, wherein the first latch circuit comprises a first inverter, a second inverter, a first switch connected in parallel with the first inverter, and a second switch connected in series with the second inverter. Additionally, a second latch circuit configured to latch an output of the first latch circuit and output a latched value, wherein the second latch circuit comprises a third inverter, a fourth inverter, an output inverter connected in series with the third inverter, and a fourth switch connected in series with the fourth inverter. A third switch is configured to switch between the first latch circuit and the second latch circuit.

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.

The invention discloses a multi-bit trigger design method for a standard cell library and a scan chain, and belongs to the technical field of integrated circuits, the multi-bit trigger design method for the standard cell library comprises the following steps: providing a plurality of single-bit triggers, and setting the flipping rate of each single-bit trigger; arranging the single-bit triggers, and placing the single-bit trigger with the lowest flipping rate at the last position; the single-bit triggers are serially connected into a scan chain according to the sequence, the first single-bit trigger is used for accessing input data and a scan chain control signal, and the output end of the last single-bit trigger is used for outputting data. By arranging the triggers with the lowest flipping rate at the output end, the DFT dynamic power consumption can be reduced, and the Power signoff can be optimized.

The embodiment of the utility model relates to a scan chain circuit and a control circuit for loading a repetitive sequence to a trigger. The scan chain circuit is used for inputting a repetitive bit sequence to a trigger sequence comprising a multi-bit trigger and a unit trigger. One example includes a control circuit including a bit counter, a multiplexer, a first set of control circuits, and a second set of control circuits.

An apparatus includes a test controller and a scan chain coupled to the test controller. The scan chain includes a first segment and a second segment. The apparatus further includes circuitry coupled to the test controller and the scan chain. The circuitry is configured to provide, to the second segment, an output of the first segment in connection with a first test. The circuitry is further configured to provide, to the second segment, a test pattern in connection with a second test.

Methods and systems for positioning a welding head with respect to a groove in a rotating circular workpiece during an arc welding process, wherein a chain or other flexible measuring device is coupled about the workpiece. First and second scanners are respectively used to scan the groove and a link of the chain at a first rotational position of the workpiece. A third scanner is used to scan the chain link at a second rotational position of the workpiece that corresponds to the welding location. The scanners are collectively used to determine a profile of the groove and a change in position of the chain link between the first and second rotational positions of the workpiece. Data acquired through the scanning processes are used to generate instructions deliverable to a positioning system of the welding head to position the welding head so that arc welding properly occurs inside the groove.

The invention discloses a circuit structure for a semiconductor wafer process authentication test. The circuit structure comprises an input stage circuit, an output stage circuit and a plurality of scanning chains connected between the input stage circuit and the output stage circuit, the scanning chain comprises a plurality of scanning units connected in series and a tail selector, each scanning unit comprises an alternative transverse selector and a D trigger, and each scanning unit further comprises an alternative longitudinal selector and a tested unit; the input stage circuit is used for selecting one path of input scanning signal in each scanning chain for scanning; and the output stage circuit is used for selecting and outputting one path of scanned signal in each scanning chain. The invention also discloses a semiconductor silicon wafer failure analysis test method. The method not only can be used for analyzing and positioning the circuit yield problem of a fault chip caused by defects in semiconductor process steps, but also can be used for analyzing and positioning the low yield problem of a logic gate standard cell and a layout pattern in a standard cell library.

Embodiments of the present disclosure are directed to scan chain systems and methods for inputting repeated sequences of bits to a sequence of flip flops that include multi-bit flip flops and single bit flip flops. One example includes a control circuit that includes a bit counter, a multiplexer, a first group control circuit, and a second group control circuit.

This invention discloses a low-scan-power scanning unit and scanning chain, belonging to the field of integrated circuit design-for-test (DTBT). The invention uses a low-scan-power scanning unit, adding an OR gate to control the switching activity of two tri-state gates in the secondary latch unit during the scanning phase, and using a high-threshold PMOS as a power supply gating to control the power supply VDD of the two inverters inside the secondary latch unit, thus reducing the dynamic power consumption of the secondary latch and unnecessary dynamic power consumption of the combinational logic during the scanning phase. Additionally, a test vector output port P is added, whose signal originates from the output of the primary latch unit inside the scanning unit, reducing the transmission path delay during the scanning phase. This invention is applicable to the DTBT stage of digital circuits; by simply adding an OR gate and a high-threshold PMOS, without affecting the original logic circuit function, it achieves the goal of reducing dynamic power consumption during the shift phase.

The invention discloses a programmable online kernel self-diagnosis implementation method and a storage medium. The method comprises the following steps: S1, constructing a hardware architecture; s2, test excitation and signature pre-generation; s3, software programmable configuration is carried out; the CPU sets a test mode, the number of execution SEEDs, test granularity, clock distribution and start / stop through the configuration register; s4, preparing before testing; s5, executing an online test; reading SEED from the ROM, generating excitation by a Pattern generator, loading the excitation to a kernel scan chain, capturing output, generating an MISR, and comparing the MISR with a GOLDEN MISR; s6, fault processing and a safety mechanism; and S7, recovering after testing. The storage medium is realized based on the method. The method has the advantages of simple principle, wide application range, good flexibility, high coverage rate and the like.

A device comprises a scan chain and a device circuit. The scan chain includes a plurality of sequential elements and a diagnostic hardware circuit. The sequential elements are connected serially and grouped into a plurality of segments. The diagnostic hardware circuit includes a plurality of circuit components, each connected to a sequential element of a respective segment. The diagnostic hardware circuit identifies a faulty segment of the scan chain during a diagnostic mode. Test pattern data is serially shifted through the scan chain to isolate the faulty sequential element of the defective segment during the diagnostic mode. The device circuit is connected to the scan chain, performs one or more circuit functions, and generates functional data that is sequentially shifted through the scan chain during a functional mode.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

The invention relates to a crystal oscillator chip testing method, which comprises the following steps of: constructing a digital twinborn model of a crystal oscillator chip, and inserting a scanning chain into the digital twinborn model; the scanning output of the scanning chain and the electric signal of the crystal oscillator are fused into a multi-dimensional crystal oscillator characteristic; normal samples are injected into the digital twin model through a scanning chain, the multi-dimensional crystal oscillator characteristics under the fault-free condition are obtained to serve as training data, and an over-complete dictionary is trained; injecting a fault sample into the digital twin model through a scanning chain to obtain multi-dimensional crystal oscillator characteristics under different fault types, and further calculating a reconstruction error corresponding to each fault type by using an over-complete dictionary to serve as a fault fingerprint; and carrying out scanning test on the crystal oscillator chip, calculating a reconstruction error by using an over-complete dictionary according to the multi-dimensional crystal oscillator characteristics obtained by the test, and comparing the actually measured reconstruction error with the fault fingerprint to obtain a chip test result. According to the invention, the detection precision and accuracy of the crystal oscillator chip can be improved.

An array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

An integrated-circuit chip comprises a plurality of scan flip-flops and a retention cell. The chip is configured to have a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip, and to have a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain for use during scan-chain testing of the integrated-circuit chip. The chip further comprises on-chip test circuitry arranged to generate and output a save signal, a clock signal, and a restore signal to the retention cell, for testing the retention cell during scan-chain testing of the integrated-circuit chip.

The invention belongs to the technical field of integrated circuit testing, and discloses an in-memory computing chip testing device and method based on a scan chain architecture, and the method comprises the steps: employing three groups of independent scan chains (input, weight and partial sum) to cooperate with an on-chip configurable controller (Config Regs + FSM), and achieving the automatic testing of a memory Mode and a computing Mode of an in-memory computing macro cell (CIM Macro). According to the technical scheme provided by the invention, the storage and calculation functions of the CIM chip can be comprehensively verified with lower hardware overhead and lower external IO rate.

The invention discloses a scan chain circuit and a scanning method thereof, a chip, electronic equipment and a storage medium. The scan chain circuit comprises at least two storage modules and switching circuits corresponding to the storage modules; the input end of the first storage module is connected with the output end of the second switching circuit; wherein the second switching circuit is a switching circuit corresponding to the second storage module; the first storage module is adjacent to the second storage module; the first input end of the first switching circuit is connected with the output end of the first storage module; the first switch circuit corresponds to the first storage module; the second input end of the first switching circuit is connected with the output end of the second switching circuit. According to the chip scanning shift-out method, whether the corresponding storage module shifts out the data of the register in the storage module or not is controlled through the switching circuit, the data value of the register in the target storage module on the output scanning chain is controlled, the flexibility of the chip scanning shift-out method is improved, the data volume shifted out by chip scanning is reduced, and the chip scanning efficiency is improved. And thus, the analysis efficiency of the data volume shifted out by chip scanning is improved.

This invention discloses a low-power ATPG method, apparatus, chip, chip module, and terminal device. The low-power ATPG method involves minimizing inverter insertion / deletion in the scan chain data path without altering the functional path. This maximizes the shutdown of the chip's integrated clock gating after Shift-0 vector loading, significantly reducing capture-to-flip rate and shift-to-flip rate. This method modifies only the scan chain data structure without affecting the functional path timing, offering advantages such as minimal hardware overhead, significantly reduced power consumption, fewer vectors, and high automation. It can be widely applied in low-power testing processes for various chips, chip modules, terminals, and base stations.

Embodiments of the present disclosure relate to scan circuits and methods. In one embodiment, a method of performing a scan includes entering a scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and de-asserting a scan enable signal to perform a shift and a capture operation, respectively, on the first scan chain; controlling a further scan flip-flop with the first scan chain while applying the test pattern through the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect a fault.

A scan chain circuit and an operation method thereof are provided. The scan chain circuit includes a plurality of scan chain units. Each of the scan chain units includes a plurality of input scan flip-flop (SFF) and a comparison circuit. After a plurality of input bit values are operated by a logic circuit, a plurality of actual operation result bit values are obtained. The comparison circuit is used to receive the actual operation result bit values and a plurality of predetermined operation result bit values. Each of the predetermined operation result bit values is each of a plurality of predetermined operation results after each of the input bit values is operated by the logic circuit. The comparison circuit compares the actual operation bit values and the predetermined operation result bit values, and then outputs a bits comparison result bit value.

In scan testing of semiconductor devices, instantaneous power consumption in both shift and capture modes is efficiently reduced. The scan chain is provided with circuit blocks 1 to 4. Each of the temporary storage flip-flops F1 to F3 is connected between one of the two circuit blocks. Clock generating circuit 10 outputs a clock signal CLK used for the scan test. The clock gating cells GC1 to GC4 takes the clock signal CLK and provides the clock signals CLK1 to CLK4 to circuit blocks 1 to 4 and the clock signals CLK1 to CLK3 to the temporary storage flip-flops F1 to F3. The control circuit 20 controls the clock gating cells GC1 to GC4 so as to operate the circuit blocks 1 to 4 at differing timings from the input-side one by one and simultaneously operate each circuit block and a temporary storage flip-flop connected to the output of each circuit block.