6 results about "Logic built-in self-test" patented technology

Aspects of the disclosure are directed to variable shift frequency implementation. In accordance with one aspect, the disclosure includes synthesizing a divided clock (511) from a shift clock (501) with a divided frequency equal to a reference frequency divided by a selected integer divisor in a logical built-in self-test (LBIST) mode; transitioning the LBIST mode from a shift state to a capture state by enabling a capture control enable signal (502) while pacing with the divided clock (511); generating a stretched capture control enable signal from the capture control enable signal using a slow cycle programmer (SCP, 530) with a plurality of quad stage pipelines; and transitioning the LBIST mode from the capture state to a subsequent shift state with the stretched capture control enable signal in a HIGH state to mitigate voltage droop.

A memory device comprises a storage component for Logic Built-In Self-Test (LBIST) pattern seed information and an In-System Test (IST) controller. The IST controller receives a host command to initiate self-test, loads pattern seed information, triggers test execution, and provides status information to the host. The storage component may be random access memory, allowing dynamic modification of test patterns. This on-demand LBIST architecture enables fault detection during device operation and allows flexible test pattern generation that can adapt to changing requirements.

Run-time logic built-in self-test (LBIST) may be performed, while ensuring operational continuity. The compute elements in a machine learning accelerator contain LBIST circuitry that performs logic testing of the functional circuitry in the compute element. The LBIST circuitry may be self-sufficient, meaning that it contains the data and instructions needed to run and evaluate these tests. An LBIST manager enables the logic testing during idle time of the functional circuitry between blocks of statically scheduled instructions. As a result, the LBIST circuitry can perform the logic tests without disrupting the computation of the machine learning network.

An example is a method. A query challenging authenticity is received at an intellectual property (IP) block in an integrated circuit (IC) die. The query may be a query of a query-response pair. A response to the query is generated, at the IP block, using a logic built-in self-test (LBIST) circuit. The response is transmitted from the IP block. The response may be received and compared to an expected response of the query-response pair. Authenticity may be validated when the response matches the expected response.

The invention relates to a random test vector generation device and method and a logic built-in self-test structure and method, and the device comprises a random vector generation module which is used for generating a random vector corresponding to each domain in all domains of an X86 instruction; the random instruction generation module is used for generating a random instruction aiming at the X86 instruction by utilizing the generated random vector aiming at each domain of the X86 instruction; the instruction selection module is used for obtaining the length of a random instruction and selecting target random instructions according to the length of the random instruction and the generated random instruction, the selected multiple target random instructions can be randomly combined into the random test vector, and the random test vector is output to the X86 instruction decoding module. Therefore, logic built-in self-testing can be effectively carried out on the X86 instruction decoding module.

Aspects of the disclosure are directed to variable shift frequency implementation. In accordance with one aspect, the disclosure includes synthesizing a divided clock from a shift clock with a divided frequency equal to a reference frequency divided by a selected integer divisor in a logical built-in self-test (LBIST) mode; transitioning the LBIST mode from a shift state to a capture state by enabling a capture control enable signal while pacing with the divided clock; generating a stretched capture control enable signal from the capture control enable signal using a slow cycle programmer (SCP) with a plurality of quad stage pipelines; and transitioning the LBIST mode from the capture state to a subsequent shift state with the stretched capture control enable signal in a HIGH state to mitigate voltage droop.