95 results about "Logic built-in self-test" patented technology

A scheme for multi-frequency at-speed logic Built-In Self Test (BIST) is provided. This scheme allows at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. The scheme is also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. Scanable memory elements of the digital circuit are connected to define plurality of scan chains. The loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. The BIST controller, Pseudo-Random Pattern Generator (PRPG) and Multi-Input Signature Register (MISR) work at slower frequency than the fastest clock domain. After loading of a new test pattern, a clock suppression circuit allows a scan enable signal to propagate for more that one clock cycle before multiple capture clock is applied. This feature relaxes the speed and skew constraints on scan enable signal design. Only the capture cycle is performed at the corresponding system timing. A programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.

Systems and methods for controlling test conditions using logic built-in self-test (LBIST) components to affect test conditions. In one embodiment, an LBIST controller is coupled to LBIST circuitry that is incorporated into the design of a device under test, and also to a thermal sensor that is in thermal communication with the device under test. The LBIST controller is configured to receive device temperature information from the thermal sensor and to modify control signals that are provided to the LBIST circuitry in order to cause the LBIST circuitry to operate in a manner that drives the device temperature to a desired level. In one embodiment, the LBIST controller adjusts the speed with which the LBIST circuitry scans data into and out of a plurality of scan chains, thereby adjusting the amount of heat generated by this operation, which in turn affects the temperature of the device.

Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled / decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed to determine whether any of the processor cores is malfunctioning. If none of the processor cores malfunctions, the processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor is fully functional. If one or more processor cores malfunctions, these processor cores are isolated and the remaining processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor operates properly with reduced functionality.

Systems and methods for performing logic built-in self-tests (LBISTs) to detect “at-speed” errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target logic of the digital circuit and captured in scan chains at a normal operating speed to produce a first output bit pattern. This is repeated with the first input bit pattern at a lower test speed to produce a second output bit pattern. Differences between the first and second output bit patterns are then detected to determine whether operation of the digital circuit at the normal operating speed causes errors that are not generated at the lower test speed.

A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to locate a first latch that fails the test. Particularly, latches on the chip are arranged in a plurality of scan chains wherein each latch holds data for a logical cone. The LBIST is performed on one scan chain at a time. Once the first latch is located, a first limiting cone (i.e., the cone for which the first latch is holding data) may be isolated. After isolating the first limiting cone, the data from the first latch is masked out and the LBIST is repeated on the scan chain. The data is masked out in order to facilitate the identification of any other latch that may fail the test. Again, if another latch fails the test a corresponding limiting cone may be isolated.

A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input / output (I / O) circuit of an integrated circuit of the electronic package environment with a logic built-in self-test (LBIST) of the integrated circuit, wherein the external signal path being verified is electrically coupled to the tested I / O circuit. A result of verifying of the at least one external signal path is manifested in the integrated circuit's signature, which characterizes a response of the I / O circuit to the LBIST. In another aspect, the verifying of the at least one external signal path includes concurrently testing another I / O circuit of another integrated circuit, which is also electrically coupled to the external signal path.

Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where the LBIST circuitry is configured to propagate data through different portions of the functional logic of the circuits at different times. In one embodiment, a logic circuit incorporates LBIST components including a set of scan chains interposed between portions of the functional logic. Pseudorandom bit patterns are scanned into the scan chains so that they can be propagated through the functional logic following the scan chains. The resulting bit patterns are captured in scan chains following the functional logic and then scanned out of these scan chains. An LBIST controller causes functional operations in different portions of the functional logic to be performed at different times during a functional phase of a test cycle. The functional operations may be performed at a normal operating speed, while scan shift operations may be performed at a lower speed.

A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built-in self-test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.

A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test. The smart memory control may include bit error rate controller logic configured to control the bit error rate built-in self test. A write error rate test pattern generator may generate a write error test pattern for the bit error rate built-in self test. A read error rate test pattern generator may generate a read error test pattern for the built-in self test. The smart memory controller may internally generate an error rate timing pattern, perform built-in self test, measure the resulting error rate, automatically adjust one or more test parameters based on the measured error rate, and repeat the built-in self test using the adjusted parameters.

A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.