Aspects of the disclosure are directed to variable shift frequency implementation. In accordance with one aspect, the disclosure includes synthesizing a divided
clock (511) from a shift
clock (501) with a divided frequency equal to a reference frequency divided by a selected integer divisor in a logical built-in self-test (LBIST) mode; transitioning the LBIST mode from a shift state to a capture state by enabling a capture control enable
signal (502) while pacing with the divided
clock (511); generating a stretched capture control enable
signal from the capture control enable
signal using a slow cycle
programmer (SCP, 530) with a plurality of quad stage pipelines; and transitioning the LBIST mode from the capture state to a subsequent shift state with the stretched capture control enable signal in a HIGH state to mitigate
voltage droop.