93 results about "Logic built-in self-test" patented technology

A computer implemented method, data processing system, and computer usable code are provided for testing multi-core microprocessors. A test process initiates testing on communication bus interfaces associated with a set of processor cores on the multiprocessor in which the communication bus interfaces are disabled and wherein the testing uses a set of isolation test sequences to obtain results. The process identifies a set of functional processor cores in the set of processor cores based upon the results. The process also initiates a ramp logic built-in self-test to test a ramp associated with a functional processor core in the set of functional processor cores, wherein the ramp logic built-in self-test determines if the communication bus interface associated with functional processor core in the set of functional processor cores is functional.

A method, system, and computer program product for identifying failures in multi-core processors, utilizing logic built-in self test (LBIST) technology. Multi-core processors, having LBIST and pseudo-random pattern generator (PRPG) circuitry, are tested. Controlled by the LBIST control logic, PRPG inputs a test pattern into scan chains within the cores of each device. A new test pattern is generated and executed during the scan shift phase of each LBIST loop. Logic output generated by each scan chain in the core is compared to other core logic output. Failures within the multi-core processors are determined by whether the logic output generated from a core, within a latch sequence, does not match the logic output of the other cores. If logic output, from a core within a latch sequence, does not match, then the latch number, loop number, and latch values are recorded as failed.

Systems and methods for performing logic built-in-self-tests (LBISTs) where data comparisons are performed in the MISR. In one embodiment, a STUMPS-type LBIST architecture includes scan chains interposed between portions of the functional logic of the logic circuit. Test bit patterns are scanned into the scan chains, propagated through the functional logic, and captured in scan chains following the functional logic. The bits are scanned out of the scan chains into a self-compare MISR that creates a signature from the computed bit patterns and then compares the signature of the computed bit patterns with an expected signature, giving a pass/fail result. This single bit result reduces the bandwidth required to communicate the result(s) of the LBIST testing to the test equipment. As a result, a larger number of devices can be tested by a given piece of test equipment.

An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches which also have a system port. The system port allows for simpler reading of the fuses as well as for the dynamic updates of the programmable fuses for wordline and other repairs.

Systems and methods for performing logic built-in self-tests (LBISTs) to detect “at-speed” errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target logic of the digital circuit and captured in scan chains at a normal operating speed to produce a first output bit pattern. This is repeated with the first input bit pattern at a lower test speed to produce a second output bit pattern. Differences between the first and second output bit patterns are then detected to determine whether operation of the digital circuit at the normal operating speed causes errors that are not generated at the lower test speed.

Resolving timing violations introduced by a logic built-in self test (LBIST) sub-circuit formed within an underlying integrated circuit includes analyzing a circuit path-list corresponding to the integrated circuit for timing violations and generating a circuit timing violations analysis output; generating a first LBIST/circuit path-list based on the circuit path-list and an LBIST path-list corresponding to the LBIST sub-circuit; analyzing the first LBIST/circuit path-list for timing violations and generating an LBIST/circuit timing violations analysis output; comparing the LBIST/circuit timing violations analysis output with the circuit timing violations analysis output; generating an LBIST/circuit constraint file based on the comparison and predetermined protocols; and generating a second LBIST/circuit path-list based on the circuit path-list, the LBIST path-list and the constraints file. In this way, timing problems are quickly and efficiently resolved.

A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

A logic built-in self test (LBIST) system comprises a device under test having a first plurality of first bistable multivibrator circuits an LBIST controller, and a second plurality of second bistable multivibrator circuits. Each second bistable multivibrator circuit is coupled to a corresponding first bistable multivibrator circuit to swap a second state value kept by the second bistable multivibrator circuit with a first state value kept by the corresponding first bistable multivibrator circuit depending on a first control signal from the LBIST controller and the second bistable multivibrator circuits are coupled to form one or more scan chains when receiving a second control signal from the LBIST controller.

A method and apparatus for performing a built-in self-test (“BIST”) on an integrated circuit device are disclosed. A BIST controller comprises a logic built-in self-test (“LBIST”) engine capable of executing a LBIST and storing the results thereof and a multiple input signature register (“MISR”). The LBIST engine includes a LBIST state machine; and a pattern generator seeded with a first primitive polynomial. The MISR is capable of storing the results of an executed LBIST, the contents thereof being stored per a second primitive polynomial. A method for performing a LBIST comprises seeding a pattern generator in a LBIST engine with a first polynomial; executing a LBIST using the contents of the pattern generator; and storing the results of an executed LBIST in a MISR utilizing a second primitive polynomial.

Systems and methods for controlling test conditions using logic built-in self-test (LBIST) components to affect test conditions. In one embodiment, an LBIST controller is coupled to LBIST circuitry that is incorporated into the design of a device under test, and also to a thermal sensor that is in thermal communication with the device under test. The LBIST controller is configured to receive device temperature information from the thermal sensor and to modify control signals that are provided to the LBIST circuitry in order to cause the LBIST circuitry to operate in a manner that drives the device temperature to a desired level. In one embodiment, the LBIST controller adjusts the speed with which the LBIST circuitry scans data into and out of a plurality of scan chains, thereby adjusting the amount of heat generated by this operation, which in turn affects the temperature of the device.

A controller executes a first LBIST test on a device at a first shift frequency on a plurality of partitions and detects any voltage drop at sense points in each partition during the test. If a voltage drop is detected, then the test is re-run for those partitions that failed the first test. If failures are detected during the re-execution, then a further test at a lower shift frequency is performed. The partitions can be tested sequentially or in parallel and invention has the advantage of reducing the time taken for executing LBIST when the device is booted.

Systems and methods for performing logic built-in self-tests (LBISTs) in which an LBIST controller provides control signals to multiple LBIST satellites that are co-located with different functional blocks of the device under test, such as processor cores in a multiprocessor integrated circuit. Because the data paths for each satellite are shorter than data paths in conventional LBIST architectures, fewer latches are needed to synchronize the delivery of data to scan chains in the satellites. In one embodiment, each satellite includes a pseudorandom bit pattern generator (PRPG,) scan chains and a multiple-input signature register (MISR). In one embodiment, the LBIST circuitry also includes a control scan chain that is coupled to each of the LBIST satellites and configured to scan data into and out of the LBIST satellites.

A design supporting apparatus is disclosed, including: an inputting part; a syntactic analyzing part; and a scanning and searching part. The inputting part inputs functional description data of a register transfer level. The syntactic analyzing part conducts a syntactic analysis for the functional description data and develops a parse tree. The scanning and searching part scans and searches for the parse tree being developed by the syntactic analyzing part and searches for a description representing a comparison operator having multiple bits, the comparison operator being difficult to detect a fault by test data formed by pseudo-random numbers, which are applied from a pseudo-random number generator of a logic built-in self-test.

A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.