127results about How to "Improve fault coverage" patented technology

A microcontroller unit (MCU) having a primary, or main, processing unit, a secondary processing unit coupled to the primary processing unit, and a common memory coupled to the primary and secondary processing units is disclosed. A functional compare module is coupled to the primary processing unit and the secondary processing unit for comparing a primary output of the primary processing unit and a secondary output of the secondary processing units to detect a fault if the primary output and the secondary output are not the same. The invention provides a method for detecting a fault in the MCU including the steps of reading a control algorithm stored in the common memory by the primary processing unit, reading the control algorithm stored in the common memory by the secondary processing unit, comparing the primary output and the secondary output and responsively detecting a fault, if the primary output does not match the second output.

The invention relates to a testing method for a field programmable gate array (FPGA). The method comprises the following steps: obtaining an initial design netlist and an initial design configuration of the FPGA; replacing a look-up table function of the initial design netlist and the initial design configuration with an exclusive or function of a logic function to obtain an initial testing netlist and an initial testing configuration; selecting an observation node of the initial testing netlist based on a preset rule of a testability analysis method, and obtaining a testing netlist and a corresponding testing vector; configuring an output terminal of an output and input unit from the observation node to the initial testing configuration to obtain a testing configuration; connecting the testing configuration to an configuration device according to an excitation signal of the configuration device to obtain an output logic value of the testing vector; and analyzing the output logic value and a response value of the testing vector to obtain the testing result. The method can effectively detect permanent faults of interconnection lines used in the application design of FPGA chips.

A logic circuit comprising at least one input, one output and a delay fault circuit. The delay fault circuit includes a first standard scan cell, a combinational test point positioned immediately after the first standard scan cell in a scan chain and a second standard scan cell positioned immediately after the combinational test point in the scan chain.

The invention discloses a testing method which comprises the following steps: acquiring the testing procedure from automatic test equipment (ATE) by using a device under test (DUT) and initializing according to the testing procedure; receiving test signals by using the DUT, and testing according the test signals, and outputting test results; and reading the test results by using the ATE and determining whether the DUT conforms to the requirements according to the test results. The invention simultaneously discloses a testing system. By applying the method and the system, the test cost can be reduced, the fault coverage can be improved, and the invention can be implemented easily.

The invention relates to a system for testing a system internuclear wiring fault on an integrated circuit chip and a method thereof. The system comprises a circuit structure which is added for perfecting the IP internuclear wiring fault test and the IP intranuclear fault test in a system on the integrated circuit chip and a test inquiring mechanism which runs on the basis of the circuit structure. The invention can test the IP internuclear wiring of the system on the integrated circuit chip. The fault types of the test comprises the solid-zero fault, the solid-solid fault, the open circuit fault, the short circuit fault, the delaying fault and the noise fault. By adding a hardware structure, the invention decomposes a scanning chain of edge packing units, thereby making the best of a test buss and shortening the test time; with the output type edge packing unit, the invention automatically generates a test vector; with the input type edge packing unit, the invention further shortens the test time. The structure is compatible with the intranuclear test structure, thereby realizing the higher flexibility, making the best of the test resource, and further improving the fault coverage rate of the system of the whole integrated circuit chip. The invention is simple in circuit structure, convenient in test inquiring mechanism, and suitable for the various systems on the integrated circuit chips which are designed and built with the IP multiplexing technology.

A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns. Because a test pattern generator is provided independently of the circuit to be tested, the problem of a prolonged design period can be eliminated, a loss in the operating speed of the circuit under test is minimized and a high fault coverage can be achieved with less hardware overhead and a smaller volume of test data.

A system and method is provided for scan control and observation of a logical circuit that does not halt the operation of the system clock. Thus, all dynamic circuits within the system continue to evaluate and precharge normally. Moreover, the traditional method of placing a multiplexer before the data input of a clocked storage element to perform scan control and observation is no longer required. Consequently, the system and method provide a more efficient manner in which to perform scan control and observation of a logical circuit.

The invention discloses a built-in self-test structure and method for an on-chip network resource node storage device. The built-in self-test structure comprises a built-in self-test (BIST) controller arranged on a field programmable gate array (FPGA) chip, a resource network interface and a BIST interface which are embedded into corresponding routers, a test pattern generator and a test response analyzer, wherein the BIST controller is connected with external test equipment through an external interface. The built-in self-test method comprises the following steps that: the external test equipment sends an instruction start test program to the BIST controller; the BIST controller sends an enabling signal and a state selection signal to each test module according to a March C+ test algorithm program, performs read-write operation on each address of a static random access memory (SRAM) under each test state, and stops sending the signals if failures are found out. A test result is sent to the external test equipment. According to the built-in self-test structure and method, the test time is reduced by 50 percent; a routing network of a network operation center (NoC) is reused as a test data route; data transmission is reliable and safe; a chip area is low in expense; the failure coverage rate is high.

The invention provides a scan test latch macrocell and a scan test method. According to the scan test method, through a customized scan test macrocell, an ATPG test vector, based on a structure, used for a latch unit can be generated with a common scan test design method for a D trigger according to a special design process, the problems that testability design development cannot be easily performed on an existing digital special integrated circuit based on latch design, the fault coverage rate of the test vector is low, and time sequence analysis is complex are solved, the fault coverage rate of chip tests is substantially increased, the effectiveness and the completeness of the chip tests are guaranteed, and the method is mainly applied to the test vector development of the digital special integrated circuit based on latch design.

The invention relates to the field of an integrated circuit test, and discloses a test graphic generator of an integrated circuit and a test method thereof. The test graphic generator comprises a reconfigurable linear feedback shift register of cyclic code with single bit change, a liner feedback shift register based on a primitive polynomial and a two-dimensional exclusive or gate array; compared with the traditional test graphic generator, the test graphic generator has less hardware overhead, few quantity of repeated test graphics, short test time, uniform distribution of generated test graphics, and can obtain higher fault coverage rate; and the generated single jump test sequence reduces the conversion times of a tested circuit input end, thus greatly reducing the test power consumption of the tested integrated circuit.

The invention discloses a compression method for test data of an irrational number storage test vector and relates to a fault coverage guided compression method for the test data of the irrational number storage test vector. The compression method comprises the following steps of firstly, generating a fault list according to a circuit structure of an integrated circuit to be tested; secondly, running an automatic test vector generation tool for faults to generate test vectors of corresponding faults; thirdly, counting the lengths of runs; fourthly, performing preliminary estimation on corresponding ranges of irrational numbers; fifthly, dichotomising the ranges of the irrational numbers, and successively approximating; sixthly, filling independent bits; seventhly, performing random test; eighthly, judging whether the fault list in the seventh step is empty or not, if the fault list is empty, turning to the ninth step, and otherwise, turning to the second step; ninthly, ending, and returning all records such as integers m and l corresponding to all the irrational numbers. According to the compression method disclosed by the invention, the coding of the irrational numbers and the generation of the automatic test vectors are combined, so that on one hand, coding numbers, corresponding to the test vectors, of easily-detected fault points are reduced, and on the other hand, the fault coverage is improved.

A reconfigurable switched-capacitor input circuit with digital-stimulus acceptability for analog tests disclosed in the present invention provides the digital input interfaces, which are comprised of capacitors, analog switches and digital circuits, for the usage of testing the mixed-signal circuits. The present invention provides a low-priced testing platform to accomplish the testing of circuits and to solve the problems of high-cost mixed mode tester and of utmost restrictions against the surrounding condition. Therefore, the present invention improves the testability, reduces the test cost, shorten the processes of designation and efficiently seize on the time-to-market.

The invention discloses an integrated DC solid state power controller and a fault decision-making diagnosis method. The controller comprises a power board and a digital control board, wherein the power board is mainly responsible for system state detecting, conditioning, signal uploading and SSPC (Solid State Power Controller) driving and protection control; and the digital control board integrates related circuits for arc fault detection and cable fault detection and location, detects a conditioned system state signal based on multiple sensors, completes local fault diagnosis for the conventional SSPC such as fixed-time-lag power supply overvoltage-undervoltage fault protection, BIT self-checking of the SSPC, inverse-time-lag overload protection and additional local fault diagnosis such as system arc fault detection and cable fault detection and location in a concurrent manner in an FPGA main control module, and finally realizes decision-making diagnosis and health management for thesystem state based on a multi-source technology integration technology. The integrated DC solid state power controller can realize the enhanced system fault detection and health management ability, and improves the system safety, reliability, testability and maintenance.

A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) which ensure testing of specific logic by forcing specific values into scan latches that contain otherwise pseudorandom test bit patterns. In one embodiment, an LBIST system comprises a plurality of scan latches and forcing logic coupled to a first set of the scan latches which provide inputs to selected target logic. The forcing logic is configured to overwrite values stored in the first set of scan latches with desired values. In one embodiment, the forcing logic includes a bypass path that enables shifting of unaltered bit patterns around the first set of scan latches. Bits in the bypass path may be inverted when the bypass path is not being used in order to help detect errors in the operation of the bypass path.

A method and apparatus for compacting test responses containing unknown values in a scan-based integrated circuit. The proposed X-driven compactor comprises a chain-switching matrix block and a space compaction logic block. The chain-switching matrix block switches the internal scan chain outputs before feeding them to the space compaction logic block for compaction so as to minimize X-induced masking and error masking. The X-driven compactor further selectively includes a finite-memory compaction logic block to further compact the outputs of the space compaction logic block.

To reduce the load of layout design and attain a high fault coverage while preventing increase in chip size in test point insertion for a semiconductor integrated circuit.

Controllability probabilities are calculated on the basis of information of a subject circuit (S002). Initial layout is performed on the basis of the circuit information (S003). Interconnection pairs are extracted from a layout result (S004). Test point insertion candidates are extracted on the basis of the controllability probabilities and the interconnection pairs (S005). Whether the test point insertion candidates exist is judged (S006). If test point insertion candidates exist, test point insertion positions are selected (S007). Circuit structures of test points to be inserted there are selected (S008). Test points having those circuit structures are inserted virtually (S009). Layout is performed again on the test-points-inserted circuit (S010). Whether the circuit overhead of a layout result is within a prescribed range is judged (S011). If the circuit overhead exceeds the prescribed range, the number of test points is reduced (S012).

The invention discloses a fault detection method of an analog circuit. The method includes a first step of carrying out complex cross wavelet transform on circuit output response sequences (Sn) under nominal parameters, extracting sensitive information (recorded as I), and obtaining relative amplitude/phase reference value sequences (Sr), a second step of obtaining normal circuit output response sequences through Monte-Carlo simulation, carrying out the complex cross wavelet transform with the Sn sequences respectively, extracting the sensitive information I, and obtaining relative amplitude/phase simulation value sequences (Ss), a third step of enabling the Ss sequences to be normalized with the Sr sequences respectively, and obtaining the scope (Ra-p) of the relative amplitude/phase values of normal circuit output response, a fourth step of carrying out the complex cross wavelet transform on unknown circuit actual measurement output response sequences and the Sn sequences, extracting the sensitive information I, and then obtaining actual measurement relative amplitude/phase value sequences (St), a fifth step of carrying out normalization on the Sr sequences and the St sequences, and obtaining unknown circuit output response relative amplitude/phase values (Va-p), and a sixth step of comparing the Va-p and the Ra-p, and determining whether the detected circuits have faults. Compared with the prior art, the fault detection method is high in detection precision, and high in fault coverage rate.

The invention discloses a black-box fault injection method, systems, a medium and equipment. The injection method includes the following steps: tracking service call paths of software under testing (SUT); generating or perfecting a corresponding service system structure graph according to the service call paths; obtaining a fault scene set, which is to be used for testing, by recursive reasoning according to the service system structure graph; and carrying out fault injection according to the fault scene set, if the software under testing can be destroyed, determining that an effective fault scene is found, and otherwise, returning to continuous tracking of all the call paths once it is found that a certain fault scene cannot destroy the software under testing. According to the method, fault tolerance evaluation can be highly efficiently carried out on a large-scale computer platform, and a set of all effective fault scenes can be found without missing.

The invention relates to a test method for a memory, comprising the following tests in sequence: control line test, Chinese numerals data input method test, 01 stepping technique test and March algorithm test. The method of the invention is supposed to have high timeliness at first; then the method is supposed to have high fault-coverage rate on line fault; in addition, the method is supposed to take into account detection of self fault of a memory chip; moreover the method of the invention covers self fault of the memory chip and circuit board line fault, strikes a good balance between test requirements and test consumption, thus enjoying good fault-coverage rate and timeliness and being applicable to on-board test of various memories.