Method and system for testing on site programmable gate array

Abstract

The invention relates to a testing method for a field programmable gate array (FPGA). The method comprises the following steps: obtaining an initial design netlist and an initial design configuration of the FPGA; replacing a look-up table function of the initial design netlist and the initial design configuration with an exclusive or function of a logic function to obtain an initial testing netlist and an initial testing configuration; selecting an observation node of the initial testing netlist based on a preset rule of a testability analysis method, and obtaining a testing netlist and a corresponding testing vector; configuring an output terminal of an output and input unit from the observation node to the initial testing configuration to obtain a testing configuration; connecting the testing configuration to an configuration device according to an excitation signal of the configuration device to obtain an output logic value of the testing vector; and analyzing the output logic value and a response value of the testing vector to obtain the testing result. The method can effectively detect permanent faults of interconnection lines used in the application design of FPGA chips.

Description

Technical field [0001] The invention relates to a chip testing technology, in particular, to a testing method of a field programmable gate array and a testing system of a field programmable gate array. Background technique [0002] The appearance of Field Programmable Gate Array (FPGA) devices is the result of the development of VLSI technology and computer-aided design technology. FPGA is an erasable programmable read-only memory, usually on a single board. During power-on initialization, load related programs and data to the FPGA hardware chip of the single board; after the FPGA chip is initialized, complex logic control can be completed. [0003] Such as figure 1 As shown, the FPGA structure generally includes three types of basic resources: Input / Output Block (IOB) 101, Configurable Logic Block (CLB) 102, and Interconnect Resources (IR) 103. Among them, IOB can provide a connection interface between FPGA internal logic and package pins, CLB can be used to implement logic and...

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Problems solved by technology

[0007] The ATPG technology that utilizes the scan chain is specifically to adopt a new configurable logic unit (Configurable Logic Block, CLB) structure to make FPGA have intrinsic scanning characteristics, and combined with FPGA timing design FPGA test (Test ofFPGA, TOF) process, simplify the FPGA initial test netlist to speed up the vector generation process and improve the coverage of the generated vectors, and effectively improve the testability of sequential circuits; however, this solution requires more hardware devices and consumes FPGA chips. test cost

[0008] Another type of FPGA test scheme is to use the form of LUT unit and register in the CLB configuration in the test configuration, and detect all interconnection fixed faults and bridge faults by loading the step 0 / 1 test vector, and then The test configuration is reduced to shorten the test time; the specific process is to configure all the look-up tables (Look UpTable, LUT) in the test configuration as AND / OR functions, or single-item functions based on Walsh coding, and load all 0 / 1 vectors or activate Vector can be detected; however, in practical applications, the above scheme uses an assumption in the actual test application, that is, the logic in the FPGA design is only realized by the LUT, which does not meet the actual situation, so the scope of application of the above scheme is limited

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