118 results about "Internal logic" patented technology

The invention discloses an intelligent question bank retrieval and recommendation system based on an artificial intelligence knowledge graph, and relates to the technical field of artificial intelligence education. Comprising a knowledge graph construction module which is used for processing original education data and constructing a neighborhood knowledge graph comprising a hard preposition relation and a soft incidence relation; the user knowledge state graph construction module is used for constructing a user personal knowledge state graph isomorphic to the domain knowledge graph, and dynamically calculating a mastery index of each knowledge node through a deep knowledge tracking model based on user historical answer data; according to the method, by constructing the domain knowledge graph containing the hard preposition relation and the soft incidence relation, discrete knowledge points are organized into the structured network conforming to the cognitive law, so that the system can understand and follow the internal logic between knowledge, and a learning path which is clear in organization, efficient and coherent is generated.

The invention belongs to the technical field of information security, and discloses an NLP verification method for a commercial password security assessment report based on an agent. The comprehensive consistency verification of the assessment report is realized by constructing a cryptographic term knowledge graph, generating a cross-chapter cryptographic parameter consistency verification matrix, identifying security statement conflict points and constructing a report internal logic conflict detection model. And adopting a multi-agent cooperation mechanism to carry out iterative optimization on a verification result, and outputting a structured verification report containing contradictory position indexes and type labels. According to the method, the consistency verification capability of the password evaluation report is improved, dominant parameter inconsistency and hidden semantic conflicts can be accurately identified, the auditing cost is reduced, and the wrong implementation risk caused by report inconsistency is prevented.

The invention provides a legal text generation proofreading method and system based on a large model, and relates to the technical field of computer information processing. The method comprises the following steps: firstly, acquiring an input case text, and matching a corresponding target legal instrument template based on a preset legal instrument template library; secondly, calling a pre-trained large language model according to a format requirement, and generating a first-edition legal document; based on a pre-stored legal knowledge graph, performing internal logic and legal basis consistency verification on the first-edition legal document to obtain a consistency verification result; and finally, according to a consistency verification result, locating conflicts and errors existing in the first-edition legal document so as to generate a proofreading report containing targeted modification suggestions. According to the technical scheme provided by the invention, the legal document with a standard format can be automatically generated, logic and legal reference errors in the legal document can be intelligently detected, and specific modification suggestions are provided, so that the document quality and the generation efficiency are improved.

The invention relates to a simulation result compression method and system based on semantic segmentation, equipment and a medium. The method comprises the following steps: performing feature extraction on a simulation result file to obtain semantic features; generating a segmentation point sequence according to the features by using a semantic segmentation model, and segmenting the file into a plurality of semantic blocks; extracting a compressibility feature vector for each block, and dynamically distributing an optimal compression strategy for the block through a prediction model; compressing each block by using the distributed strategy to generate a compressed data block; and finally, constructing a block sensing index based on the block type and the used strategy, and integrating the index and the data block to generate a compressed file. By adopting the method, the defects of limited compression ratio and incapability of supporting rapid random access caused by lack of semantic understanding of a general compression algorithm can be overcome, and by understanding the internal logic structure of the file and applying differential compression, the rapid retrieval and analysis capability of specific data is kept while the high compression ratio is realized.

The invention discloses an intelligent auditing method based on knowledge graph constraint, and relates to the technical field of natural language processing, and the method comprises the steps: constructing an auditing rule knowledge graph, carrying out the constraint training of an initial large language model, obtaining an auditing fact generation model, receiving a to-be-audited work document, inputting the to-be-audited work document into a pre-trained auditing fact generation model, and obtaining a to-be-audited work document. Generating a candidate fact triple path; calling a pre-constructed auditing hook knowledge graph, and calculating a hook matching degree; determining a target auditing event and a target auditing hook; based on the associated target question keyword, executing deep information verification through an auditing fact generation model, and generating a verification fact triple; and determining a risk type and a risk level through the auditing rule knowledge graph to generate an auditing conclusion report. The big language model is specially trained through the auditing rule knowledge graph, so that the internal logic and the output result of the model are guided by the domain rule in a structured manner when the auditing facts are generated by the model.

The invention relates to the field of internet security, and discloses a big data risk early warning and evaluation method based on artificial intelligence, comprising the following steps: step S1, collecting original security data from a heterogeneous data source; s2, constructing a global causal model; s3, constructing and evolving an event causal evolution diagram so as to establish directed edges with weights among the nodes; s4, dynamically evaluating the ability level of the attacker; s5, performing adversarial intention projection; s6, calculating a dynamic risk score; and generating an early warning when the score exceeds an early warning threshold. According to the method, asymmetric information flows among event types are quantified through transfer entropy, and a context evidence fusion mechanism is combined, so that a real causal relationship and a simple statistical correlation can be distinguished; the defect that a high false alarm rate is easily generated based on rule or simple threshold matching is overcome, so that the event causal evolution diagram can accurately reflect the internal logic and time sequence characteristics of an attack behavior, and the accuracy of complex threat perception is improved.

The invention provides an intelligent medical whole-process information management method based on a. NET platform and related equipment, and relates to the technical field of intelligent medical treatment. According to the method, firstly, a personalized user illness state portrait is constructed, historical similar treatment processes are matched, and key contact points are extracted, so that a planned starting point is ensured to be a reasonable process meeting individual requirements of a patient; on the basis, a graph attention network model is introduced to calculate the correlation degree weight between the contact points. And the internal logic and cooperation relationship among different diagnosis and treatment links are disclosed. And finally, carrying out fusion weighting on the static and deep logic weight and the dynamically changed real-time queuing data to generate a dynamic priority. Through the fusion, the finally reconstructed optimized treatment task flow does not simply pursue the shortest local queuing time, but realizes the balance between the medical logic importance and the instant efficiency, so that the preciseness and rationality of the path are realized, and the global treatment efficiency is improved.

The invention relates to the technical field of very large scale integrated circuit design verification, and discloses a hierarchical cross-clock domain signal verification method, device and equipment and a medium. According to the method, on the basis of the physical layout information file corresponding to each functional module, the target functional module to be verified is dynamically, intelligently and accurately determined from the plurality of functional modules. And performing cross-clock domain signal verification on the previous level of the target function module by extracting the target sign-off abstract model of the target function module, and performing cross-clock domain signal verification on the top system of the whole chip by analogy. As clock domain crossing signal verification does not need to be carried out on all functional modules, the efficiency of chip verification can be improved, clock domain crossing signal verification, module level focusing functional module internal logic integrity verification and top layer enhanced module crossing asynchronous path analysis are carried out on the chip layer by layer through the target sign-off abstract model, and the chip verification efficiency is improved. Therefore, the accuracy of chip verification can be improved.

The invention relates to the technical field of building self-control, and discloses a building self-control real-time data processing system based on a heterogeneous computing architecture. Aiming at the problems of single data processing architecture, weak parallel processing capability, low core algorithm execution efficiency, insufficient task scheduling flexibility and the like of the existing building automatic control controller, the system innovatively adopts a heterogeneous computing architecture of a master control core, a multi-task slave core and a special hardware accelerator; and in combination with a dynamic task scheduling mechanism, a three-level data caching strategy and a multi-source data synchronous acquisition module, parallel efficient processing of multi-type building equipment data is realized. The internal logic loop period of the system is shortened to be within 15 milliseconds, the PID operation time delay is as low as 0.4 microsecond / path, the data processing throughput is improved by more than 4 times, high-frequency cooperative control of 128-path equipment is supported, meanwhile, fault redundancy and load balancing capacity is achieved, the real-time performance, the control precision and the operation reliability of the building automatic control system are remarkably improved, and the building automatic control system is suitable for large-scale popularization and application. The method is suitable for complex control scenes such as large intelligent buildings, data centers and commercial complexes.

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

The application provides a simulation method of a memory. The simulation method is based on: an EDA platform of integrated circuit design is used to build a front simulation key path circuit of the memory, and a front simulation net list of the memory is extracted and expanded. In a memory design layout, each global signal line is segmented, and each segment is attached to a repeated unit above it, and a post-simulation net list is extracted. Each module of the post-simulation net list is used to replace the corresponding module in the expanded front simulation net list to obtain a simplified post-simulation key path net list. The memory is simulated based on the post-simulation key path net list. The technical scheme provided by the application greatly simplifies the simulation net list for verifying the memory design while retaining the internal logic of the repeated unit, and meanwhile, the coupling effect of the internal logic of the repeated unit on the global signal is retained. In the simulation process, the net list module corresponding to the repeated unit appears only once, and the simulation speed is effectively improved.

The invention discloses a method for testing NAND link reliability of a solid state disk, and belongs to the technical field of solid state disks. Comprising the steps that S1, an SSD master control sends a write command sequence to an NAND particle, and verification data is written into a cache unit; s2, the SSD master control polls the minimum encapsulated physical entities and the internal logic partitions of the NAND particles, sends a read command sequence, and switches data in a cache unit to a readable state; s3, the SSD master control sends a data reading time sequence, the data in the target cache unit is compared with the original test data, and if the data are inconsistent, it is judged that the link of the minimum capsulable physical entity and the link of the internal logic partition corresponding to the target cache unit are abnormal. According to the invention, the read-write test is directly carried out on the NAND cache unit, so that the interference of the inherent data jump of the Flash Array on the test result is effectively avoided.

This invention provides a method and system for incremental retrieval index update of heterogeneous data, relating to the field of data processing technology. The method includes the following steps: batch transferring newly added information representation values ​​from the real-time cache layer to the recently active layer and performing local index optimization; analyzing the information representation values ​​in the recently active layer and the information representation values ​​in the historically stable layer and establishing jump edges; identifying invalid pointers and duplicate information fragments in the index for quickly finding similar information, and deleting invalid pointers and merging duplicate information fragments. This invention aims to solve the problems of traditional incremental update methods failing to effectively integrate different types of data when intelligent question-answering systems process massive, heterogeneous data, leading to limited retrieval efficiency and accuracy, as well as inconsistencies in internal index logic, invalid pointers, and duplicate information fragments, effectively improving system response speed and query result confidence.

The invention belongs to the technical field of new energy power generation and grid connection, discloses a grid-side converter fault ride-through control structure modeling method, system and equipment and a medium, and aims to solve the problems of difficult modeling, high cost, poor extrapolation and lack of universality caused by dependence on manufacturer internal logic or massive experimental data in the prior art. According to the method, disturbance input and current output data under a limited working condition are acquired, a dimension raising mapping function is constructed to map the input to a high-dimensional feature space, a Koopman operator is solved based on ridge regression to establish a global linear mapping model, active and reactive current reference components are predicted, and the current reference components are optimized. And finally, inputting the current inner loop time domain model to generate a current transient response curve during the fault period. According to the method, high-precision modeling and prediction can be realized only by a small number of samples, and the method has good extrapolation and universality and can be adapted to various fault ride-through strategies.

The invention discloses a real-time torque determination method and device, a storage medium and a vehicle, and relates to the field of internal logic calculation of a diesel engine control unit.The real-time torque determination method comprises the steps that a basic torque value is determined according to real-time operation data of an engine, and current environment data, friction data and air inlet dynamic delay process data of the engine are obtained; determining an environment correction coefficient based on the environment data, and calculating a product of the environment correction coefficient and the basic torque value to obtain a first correction torque value; determining a friction torque loss value according to the friction data, and calculating a difference value between the first correction torque value and the friction torque loss value to obtain a second correction torque value; and a dynamic correction coefficient is determined according to the air inlet dynamic delay process data, the product of the dynamic correction coefficient and the second correction torque value is calculated, and a real-time output torque calculated value of the engine is determined. The driving performance, the economical efficiency and the emission level of the vehicle can be improved.

The application discloses a reusable delay-locked loop in a storage controller and relates to the technical field of delay-locked loops, comprising an input signal selection circuit, a delay-locked loop device and an output signal selection circuit, a first input end and a second input end of the input signal selection circuit are connected with Tx scene input nodes and Rx scene input nodes respectively, a third input end of the input signal selection circuit is connected with a scene type selection signal end, an output end of the input signal selection circuit is connected with an input end of the delay-locked loop device, an output end of the delay-locked loop device is connected with a first input end of the output signal selection circuit, a second input end of the output signal selection circuit is connected with the scene type selection signal end, a first output end and a second output end of the output signal selection circuit are connected with Tx scene output nodes and Rx scene output nodes respectively; the application reduces internal logic, avoids repeated instantiation, reduces logic area and power consumption and improves chip integration.

The present application relates to a kind of adaptive arctangent function computing system and method based on coprocessor, using coprocessor to complete data transmission and state control.The present application includes data write module, iteration register, iteration angle selection module, data iteration module and data write back module;Data write module reads input data from coprocessor interface and stores in iteration register;Iteration angle selection module selects optimal iteration angle according to the data characteristics in iteration register and sends to data iteration module;Data iteration module calculates iteration data according to the optimal iteration angle and iterates the state in iteration register;Data write back module sends the calculation completion signal to coprocessor and executes the calculation result write back through coprocessor interface.The present application can utilize coprocessor without changing the internal structure of processor, and also can utilize the internal logic calculation unit of processor to realize high-speed high-precision arctangent function calculation.

The application discloses a kind of state monitoring terminal and method, belong to distribution switch state monitoring technical field, including CPU module, AD sampling module, input module, output module, power module and database;AD sampling module is used to collect the electrical quantity of permanent magnet quick circuit breaker, input module is used to collect external telesignalling and is transmitted to CPU module, CPU module receives electrical quantity and external telesignalling and carries out internal logic processing and produces opening / closing control signal according to processing result, output module is used to output opening / closing control signal to permanent magnet quick circuit breaker, power module is used to provide DC for opening / closing control circuit, database is used to store historical data and current collected data, CPU module compares processing result and historical data, judges whether permanent magnet quick circuit breaker exists exception, to realize the state monitoring of permanent magnet quick circuit breaker;Through the state monitoring of permanent magnet component, improve reliability and safety.

The invention discloses a graph processor modeling and analyzing method and device, and belongs to the field of computer system structure aided design. The method comprises the following steps: establishing a unified calculation model decoupled from a storage architecture model; full-link micro-architecture behavior data is obtained through FPGA actual measurement, and a bandwidth constraint model is constructed to determine the optimal parallelism degree of a calculation unit; carrying out closed-loop calibration on bus delay and internal logic parameters of the simulation model by utilizing measured data; and on the calibrated reference model, keeping the optimal parallelism unchanged, and carrying out space evaluation and performance quantitative analysis on various storage architecture schemes. The device comprises an upper computer, an FPGA hardware platform and a communication interface assembly, wherein system-level simulation software and hardware control software are integrated on the upper computer. According to the method, by constructing a software and hardware closed-loop cooperation mechanism, the problems that the degree of parallelism is difficult to reasonably determine and the simulation precision of pure software is insufficient are solved, and high-precision and high-efficiency evaluation of the calculation subsystem and the storage subsystem of the graph processor is realized.

The application relates to the technical field of chip testing, and discloses a method and system for protecting and encrypting software error injection of a chip. The method comprises the following steps: encrypting storage information to generate data information register check information bits; decrypting the data information register check information bits; and comparing the decrypted information, and when the check is correct, injecting error storage information into the chip to perform software error injection. The application can provide security protection in the process of software error injection of the chip, so that input error information caused by malicious cracking is avoided, chip errors are processed by an upper layer of the chip, and malicious cracking causing exposure of internal logic functions of the chip is avoided, so that the security during chip operation is greatly improved.

The application relates to the technical field of food safety traceability, in particular to a food traceability method and system based on food safety, which comprises the following steps: synchronously collecting environment data and vehicle running state data in a carriage within a preset time interval on a cold-chain transport vehicle, and encapsulating the collected environment data and the vehicle running state data into a context snapshot data packet; using a pre-stored private key to digitally sign the context snapshot data packet; transmitting the signed context snapshot data packet to a food traceability distributed ledger through an encryption channel, verifying, and according to a preset logic judgment rule, cross-comparing the internal logic consistency between the environment data and the vehicle running state data in the context snapshot data packet; the application can verify the authenticity of data from the dual dimensions of the physical world and the digital world through the cross comparison of the environment data and the vehicle running state data and in combination with the digital signature technology.

The embodiment of the invention provides a webpage fingerprint collection and detection method, which belongs to the technical field of data processing, and specifically comprises the following steps: creating a proxy object for a to-be-monitored browser fingerprint collection related target object; calling a preset function which is injected into the V8 engine in advance through a JavaScript script, and transmitting a target host object, a target attribute name and a proxy object to the preset function; executing a preset function on a V8 engine level, bypassing the check on the original attribute descriptor of the target attribute name in the target host object through internal logic, and forcibly assigning the proxy object to the target attribute name; and after the replacement is completed, guiding any access request for the target attribute name through JavaScript to the proxy object, and intercepting, recording and analyzing by a trap function to complete the detection of the webpage fingerprint acquisition behavior. Through the scheme disclosed by the invention, the detection accuracy and reliability are improved.

Battery system (300) comprising: a first battery assembly (304-1) containing a first and a second terminal (332-1, 336-1) and configured to be selectively connected to (i) an output terminal of the battery system (300) and (ii) a DC fast charging (DCFC) socket (316); a first contactor (344-1) connected between the DCFC socket (316) and the first terminal (332-1) of the first battery assembly (304-1), the first contactor (344-1) having an open state in which the current from the DCFC socket (316) to the first battery assembly (304-1) is interrupted, and a closed state in which current flows from the DCFC socket (316) to the first battery assembly (304-1); and a first solid-state relay (SSR) (352-1) connected in series between the DCFC socket (316) and the first terminal (332-1) of the first battery assembly (304-1) with the first contactor (344-1),wherein the first SSR (352-1) has an open state in which the current from the DCFC socket (316) to the first battery assembly (304-1) is interrupted, and a closed state in which current flows from the DCFC socket (316) to the first battery assembly (304-1), wherein the first SSR (352-1) is configured to transition from the closed state to the open state before the first contactor (344-1), wherein current flows from the DCFC socket (316) to the first battery assembly (304-1) only when both the first contactor (344-1) and the first SSR (352-1) are in the closed state, wherein the first SSR (352-1) is configured with internal logic to automatically open in response to a current rising above a predetermined threshold, and wherein the first SSR (352-1) is configured to open at a lower current threshold than the first contactor (344-1).

The present application relates to the technical field of firewall authentication, and particularly relates to a firewall mobile client authentication method and system, which comprises the following steps: when a user accesses a firewall authentication interface, the firewall allows the client authentication domain name traffic to load SDK to generate a two-dimensional code; after the user scans the two-dimensional code by using a mobile client, the mobile client identifies an encrypted communication link generated by the authentication interface to automatically request communication with a cloud middleware server, and sends an authentication request to the cloud middleware server; the cloud middleware server checks encrypted data, and interacts with a client authentication server to confirm user authentication information; if the check and the confirmation are both successful, the cloud middleware server sends the user authentication information to the firewall, so that the firewall completes the authentication process after processing internal logic. The technical scheme shown in the present application realizes the interaction between the firewall and the authentication server through the cloud middleware server, which not only realizes the security and convenience of user authentication, but also increases the flexibility of firewall authentication.

The invention relates to an application program generation method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: collecting functional logic block information received through a graphical interactive interface, and generating a directed graph data model for protecting measurement and control logic according to the functional logic block information; performing serialization processing on the directed graph data model to obtain a structured logic description file; performing internal logic processing on the structured logic description file to obtain a source code and a configuration file; and compiling and linking according to the source code and the configuration file to generate an application program for protecting the measurement and control logic. By adopting the method, the technical threshold can be remarkably reduced, and the development efficiency and reliability are improved.

The invention relates to the technical field of low-code platform business processes, in particular to a business process platform based on low-code and process mining fusion, and the platform comprises an event receiving module which is used for receiving an initial business event; the instance reconstruction module is used for generating a complete business process instance to be detected; the custom event detection module is used for detecting whether a custom business event based on low codes exists in the instance or not; the logic consistency verification module is used for sequentially executing full composition verification, internal logic verification and logic verification before and after the event when the user-defined business event exists; and the executive evaluation module is used for performing executive evaluation on the custom business event and feeding back a result to the event receiving module. According to the method, through fusion of low-code development and process mining, automatic reconstruction of business process instances, intelligent detection of custom events, multi-layer logic consistency verification and executive automatic feedback are realized, and high efficiency and intelligence of process management are realized.

The invention provides a programming simulation operation question generation method, a display control method and a related product. The display control method comprises the following steps: acquiring a programming simulation operation question; the programming simulation operation question comprises question codes and questions for each investigable code block in the question codes; the investigable code block is a code block which generates actual operation in the title code; and displaying the programming simulation operation problem. Therefore, the user can know the sequential execution process of each code block of the title code on the basis of seeing the title code, so that the execution sequence of the code can be more intuitively known, and the internal logic of the code is understood.

The invention discloses a multi-source heterogeneous data element disassembling and comparing method and a related device, and relates to the technical field of data process.In the scheme, association rule extraction and confidence coefficient screening processing are conducted on a multi-source heterogeneous data set to be disassembled and compared, and a high-confidence-coefficient association rule is obtained; and performing disassembly comparison on the data element non-empty subset corresponding to the high-confidence association rule to obtain a disassembly comparison result. The association rules are used for indicating the internal logic connection strength among the data elements, the association rules with higher confidence indicate the internal logic connection strength among the data elements, and the association rules are of great significance for large model training, so that the high-confidence association rules are obtained through association rule extraction and confidence screening processing, and the data processing efficiency is improved. According to the method, the data elements with relatively high internal logic connection strength can be determined as the to-be-disassembled and compared object, so that the efficiency and the reliability of data element disassembly and comparison are greatly improved.

The invention relates to the technical field of semiconductor device in-memory logic calculation, and provides a bipolar ferroelectric field effect transistor in-memory logic operation method and a device preparation method, a ferroelectric layer is inserted into a gate dielectric layer in a bipolar ferroelectric field effect transistor, and a source electrode and a drain electrode adopt a metallization source-drain process; the method comprises the following steps: applying a gate-source voltage and a drain-source voltage to the bipolar ferroelectric field effect transistor, and completing operations of writing in a first signal A and writing in a second signal B and reading on the bipolar ferroelectric field effect transistor; and dynamically adjusting the gate-source voltage and the drain-source voltage, and performing various logical operations on the first signal A and the second signal B based on the bipolar characteristic of the bipolar ferroelectric field effect transistor to obtain a logical operation result. The bipolar ferroelectric field effect transistor is simple in structure, the nonvolatile characteristic and the bipolar characteristic are combined, logic operation can be executed while data storage is carried out, multiple different logic operations are executed by dynamically adjusting the gate-source voltage and the drain-source voltage, and operation is easy.

The present application relates to a kind of intelligent carbon accounting method and system based on large language model, for the automatic analysis of carbon accounting rule in multi-source heterogeneous text, logic conflict resolution and path self-consistent reconstruction problem, a kind of method based on large language model is extracted, accounting path atlas construction and dynamic weight applicability adjustment of logic anchor point.It includes heterogeneous text semantic deconstruction and accounting logic anchor point solidification, accounting dimension scene configuration, topological accounting path automatic generation, logic constraint direction annotation and bidirectional consistency check, conflict intelligent negotiation and path reconstruction and compensation correction based on weight, finally realize the data consistency of whole-process carbon accounting, traceability integrity and compliance delivery.The method effectively improves the degree of carbon accounting automation and result reliability, can dynamically respond to the rule conflict in actual scene of enterprise, guarantee the internal logic of multi-dimensional carbon accounting result Self-consistent and reliability.