197 results about "Internal logic" patented technology

The invention discloses an intelligent question bank retrieval and recommendation system based on an artificial intelligence knowledge graph, and relates to the technical field of artificial intelligence education. Comprising a knowledge graph construction module which is used for processing original education data and constructing a neighborhood knowledge graph comprising a hard preposition relation and a soft incidence relation; the user knowledge state graph construction module is used for constructing a user personal knowledge state graph isomorphic to the domain knowledge graph, and dynamically calculating a mastery index of each knowledge node through a deep knowledge tracking model based on user historical answer data; according to the method, by constructing the domain knowledge graph containing the hard preposition relation and the soft incidence relation, discrete knowledge points are organized into the structured network conforming to the cognitive law, so that the system can understand and follow the internal logic between knowledge, and a learning path which is clear in organization, efficient and coherent is generated.

The invention belongs to the technical field of information security, and discloses an NLP verification method for a commercial password security assessment report based on an agent. The comprehensive consistency verification of the assessment report is realized by constructing a cryptographic term knowledge graph, generating a cross-chapter cryptographic parameter consistency verification matrix, identifying security statement conflict points and constructing a report internal logic conflict detection model. And adopting a multi-agent cooperation mechanism to carry out iterative optimization on a verification result, and outputting a structured verification report containing contradictory position indexes and type labels. According to the method, the consistency verification capability of the password evaluation report is improved, dominant parameter inconsistency and hidden semantic conflicts can be accurately identified, the auditing cost is reduced, and the wrong implementation risk caused by report inconsistency is prevented.

The invention relates to the technical field of bidding and tendering information processing, in particular to a bidding and tendering template generation method based on a large language model, which comprises the following steps: receiving and analyzing bidding and tendering project demand information input by a user, extracting key elements through a named entity recognition model, and generating standardized demand data; inputting the standardized demand data into a pre-trained large language model to generate an initial bidding and tendering template text; based on a bidding and tendering clause logic rule base, internal logic consistency scanning is carried out on the initial template text, and potential conflict clauses are identified and marked; and generating an optimization instruction according to a conflict detection result, driving the large language model to complete directional revision of conflict terms, and finally outputting a target bidding and tendering template with a standard structure and consistent logic. The method has the capabilities of efficient generation, logic self-inspection and automatic repair, and the intelligent level and compliance control capability of bidding document compilation are remarkably improved.

The invention relates to the technical field of substation automatic testing, in particular to a substation automatic testing method and system, and the method comprises the following steps: constructing a digital test message for simulating the operation state of a power grid, the digital test message meeting the internal processing specification of an intelligent terminal; injecting the digital test message into an internal logic processing path of the intelligent terminal in a non-intrusive manner through a diagnosis interface reserved by the intelligent terminal or an internal communication network of the intelligent substation; performing time synchronization on the digital test message by using a time synchronization mechanism of the intelligent substation; receiving response data returned by the intelligent terminal through an internal communication network of the intelligent substation; wherein the test process is logically isolated from the main function of the intelligent terminal, and the test process comprises the steps of digital test message injection, time synchronization and response data acquisition. Through the scheme, the test efficiency and reliability are improved.

The invention provides a legal text generation proofreading method and system based on a large model, and relates to the technical field of computer information processing. The method comprises the following steps: firstly, acquiring an input case text, and matching a corresponding target legal instrument template based on a preset legal instrument template library; secondly, calling a pre-trained large language model according to a format requirement, and generating a first-edition legal document; based on a pre-stored legal knowledge graph, performing internal logic and legal basis consistency verification on the first-edition legal document to obtain a consistency verification result; and finally, according to a consistency verification result, locating conflicts and errors existing in the first-edition legal document so as to generate a proofreading report containing targeted modification suggestions. According to the technical scheme provided by the invention, the legal document with a standard format can be automatically generated, logic and legal reference errors in the legal document can be intelligently detected, and specific modification suggestions are provided, so that the document quality and the generation efficiency are improved.

The invention relates to a simulation result compression method and system based on semantic segmentation, equipment and a medium. The method comprises the following steps: performing feature extraction on a simulation result file to obtain semantic features; generating a segmentation point sequence according to the features by using a semantic segmentation model, and segmenting the file into a plurality of semantic blocks; extracting a compressibility feature vector for each block, and dynamically distributing an optimal compression strategy for the block through a prediction model; compressing each block by using the distributed strategy to generate a compressed data block; and finally, constructing a block sensing index based on the block type and the used strategy, and integrating the index and the data block to generate a compressed file. By adopting the method, the defects of limited compression ratio and incapability of supporting rapid random access caused by lack of semantic understanding of a general compression algorithm can be overcome, and by understanding the internal logic structure of the file and applying differential compression, the rapid retrieval and analysis capability of specific data is kept while the high compression ratio is realized.

The invention belongs to the technical field of combat document generation, and particularly relates to a combat document generation method and system based on a large language model, which is used for generating a supervised fine-tuning text of a large model, and comprises the following steps: randomly selecting a combat scene and description information thereof from a pre-established combat scene library, and generating a fine-tuning text based on the selected combat scene and description information; generating known key information; based on the known key information, the provided cue words are used, and key information conforming to logic is generated by utilizing a large language model; verifying the generated information to determine whether the information accords with the logic of the whole scene; inputting the key information passing the verification into a preset cue word template, and generating a complete combat document by using a large language model; the generated combat document is verified, and content consistency and language smoothness are checked; the generated key information is extracted and constructed into a character string in a JSON format; and outputting the combat document text and the corresponding JSON format character string. According to the method, the generation speed of combat document training corpora and the reasonability of internal logic are improved.

The invention discloses an intelligent auditing method based on knowledge graph constraint, and relates to the technical field of natural language processing, and the method comprises the steps: constructing an auditing rule knowledge graph, carrying out the constraint training of an initial large language model, obtaining an auditing fact generation model, receiving a to-be-audited work document, inputting the to-be-audited work document into a pre-trained auditing fact generation model, and obtaining a to-be-audited work document. Generating a candidate fact triple path; calling a pre-constructed auditing hook knowledge graph, and calculating a hook matching degree; determining a target auditing event and a target auditing hook; based on the associated target question keyword, executing deep information verification through an auditing fact generation model, and generating a verification fact triple; and determining a risk type and a risk level through the auditing rule knowledge graph to generate an auditing conclusion report. The big language model is specially trained through the auditing rule knowledge graph, so that the internal logic and the output result of the model are guided by the domain rule in a structured manner when the auditing facts are generated by the model.

The invention relates to the technical field of switching chip design, in particular to a high-speed network switching chip testability implementation method and system, and the method comprises the steps: constructing a chip function test environment, and configuring a to-be-tested high-speed network switching chip; generating function test data according to the test instruction, wherein the function test data comprises internal logic self-test data, chip exception test data, chip state test data and chip flow test data; and performing function test and verification on the high-speed network switching chip to be tested by using the function test data based on the chip function test environment. According to the method, a loopback mode, exception handling, state monitoring, flow statistics and the like penetrate through the chip front-end design process, testability of the high-speed network switching chip is achieved, rapid function testing and problem and defect positioning of the chip are supported, laboratory work performance testing efficiency after the chip is returned can be improved, and the working efficiency of a laboratory can be improved. And the screening test efficiency of the chip on an automatic machine is improved.

According to the data import configuration method and device, the storage medium and the computer equipment provided by the invention, when the data configuration is imported, the source data file is uploaded firstly, the target table configuration corresponding to the file is determined, and the import rule configuration is generated based on the template configuration and the target table configuration, so that automatic configuration of the file data import rule can be realized; because the import rule configuration comprises the corresponding relationship between the template column name and the plurality of field names, the field reading can be performed on the source data file according to the import rule configuration, and the data is imported according to the reading result to generate the temporary table; and finally, after a verification function of each column of data in the temporary table is determined based on the import rule configuration, data verification is carried out on the temporary table, so that the column data passing verification is migrated into the target table, and the verification function can visualize business internal logic into a rule and then build the rule in the import rule configuration. Automatic verification of the data in the temporary table is achieved, and the development efficiency of the data import function is further improved.

The invention discloses a chip verification method, a computer program product, equipment and a medium, and relates to the technical field of computers, the chip verification method is applied to a chip verification device, the device comprises a division module, a management module, a communication module and a test module, and the method comprises the following steps: dividing test cases into different test categories through the division module, and sending the test cases to the management module; determining a target test case through the management module; sending the target test case to a subsystem test unit in a test module through a communication module; different subsystem test units have different subsystem characteristics, and the subsystem characteristics comprise service correlation between the subsystem test units and chip core services and software and hardware coupling degrees of the subsystem test units; and executing the target test case through the subsystem test unit to verify internal logic of software and hardware interaction in the subsystem test unit. According to the method, the design problem of a hardware interaction bottom layer can be found, hidden dangers are eliminated before tape-out, and the risk of tape-out failure is remarkably reduced.

The invention provides an agent control instruction generation method and device, equipment, a medium and a product. The intelligent agent control instruction generation method comprises the following steps: splitting an obtained natural language according to a set rule to obtain splitting units; generating a function corresponding to each splitting unit based on the splitting units and a trained function model; constructing a capability logic expression corresponding to the obtained natural language based on the function corresponding to each splitting unit; and generating an agent control instruction based on the capability logic expression. By analyzing the natural language, the corresponding split unit is converted into the corresponding function, the natural language data is standardized through the function, then the agent control instruction is constructed based on the function, and semantic analysis is decoupled from the internal logic of the agent, so that the intelligent agent control instruction is obtained. Therefore, the instruction generation method can be flexibly and repeatedly used and is convenient to migrate.

The invention relates to the field of internet security, and discloses a big data risk early warning and evaluation method based on artificial intelligence, comprising the following steps: step S1, collecting original security data from a heterogeneous data source; s2, constructing a global causal model; s3, constructing and evolving an event causal evolution diagram so as to establish directed edges with weights among the nodes; s4, dynamically evaluating the ability level of the attacker; s5, performing adversarial intention projection; s6, calculating a dynamic risk score; and generating an early warning when the score exceeds an early warning threshold. According to the method, asymmetric information flows among event types are quantified through transfer entropy, and a context evidence fusion mechanism is combined, so that a real causal relationship and a simple statistical correlation can be distinguished; the defect that a high false alarm rate is easily generated based on rule or simple threshold matching is overcome, so that the event causal evolution diagram can accurately reflect the internal logic and time sequence characteristics of an attack behavior, and the accuracy of complex threat perception is improved.

The invention provides an intelligent medical whole-process information management method based on a. NET platform and related equipment, and relates to the technical field of intelligent medical treatment. According to the method, firstly, a personalized user illness state portrait is constructed, historical similar treatment processes are matched, and key contact points are extracted, so that a planned starting point is ensured to be a reasonable process meeting individual requirements of a patient; on the basis, a graph attention network model is introduced to calculate the correlation degree weight between the contact points. And the internal logic and cooperation relationship among different diagnosis and treatment links are disclosed. And finally, carrying out fusion weighting on the static and deep logic weight and the dynamically changed real-time queuing data to generate a dynamic priority. Through the fusion, the finally reconstructed optimized treatment task flow does not simply pursue the shortest local queuing time, but realizes the balance between the medical logic importance and the instant efficiency, so that the preciseness and rationality of the path are realized, and the global treatment efficiency is improved.

The invention provides a chip verification method and device, electronic equipment and a storage medium, and relates to the technical field of chip design verification, and the method comprises the steps: synchronously operating a to-be-verified chip design and a chip verification model to execute a preset cache line processing method; respectively acquiring a first output signal and first additional information of the to-be-verified chip design, and a second output signal and second additional information of the chip verification model; the first additional information is used for representing intermediate state information of a cache line in the design of the to-be-verified chip; the second additional information is used for representing intermediate state information of a cache line in the chip verification model; and determining a function verification result of the to-be-verified chip design. According to the method and the device provided by the invention, the output signal and the additional information are compared, so that the design defect can be found in time in the early stage of deviation of the internal logic state of the chip, the verification completeness and accuracy are greatly improved, and the overall verification efficiency is improved.

The invention relates to the technical field of very large scale integrated circuit design verification, and discloses a hierarchical cross-clock domain signal verification method, device and equipment and a medium. According to the method, on the basis of the physical layout information file corresponding to each functional module, the target functional module to be verified is dynamically, intelligently and accurately determined from the plurality of functional modules. And performing cross-clock domain signal verification on the previous level of the target function module by extracting the target sign-off abstract model of the target function module, and performing cross-clock domain signal verification on the top system of the whole chip by analogy. As clock domain crossing signal verification does not need to be carried out on all functional modules, the efficiency of chip verification can be improved, clock domain crossing signal verification, module level focusing functional module internal logic integrity verification and top layer enhanced module crossing asynchronous path analysis are carried out on the chip layer by layer through the target sign-off abstract model, and the chip verification efficiency is improved. Therefore, the accuracy of chip verification can be improved.

The invention discloses a communication network diagnosis and dynamic arrangement adaptation method and system oriented to a multi-source heterogeneous rule engine. The method comprises the following steps: acquiring logic circuit, environment and energy consumption data as initial data; and after feature extraction and fusion processing, a fusion fault diagnosis model is utilized to analyze the fault probability of each node and the environmental influence weight thereof, the fault is positioned, and the influence of the environment on the fault is evaluated. Comparing the equipment energy consumption data with an energy efficiency standard, identifying energy consumption abnormity, and determining an energy loss source by using a comprehensive energy loss analysis model based on a fault tree and a Bayesian network; comprehensively optimizing equipment parameters, layout, greening and software configuration according to a fault diagnosis result to formulate adjustment measures; the effectiveness of measures is verified through power devices, communication performance and greening environment simulation, the future performance trend is predicted, and a basis is provided for network optimization and greening planning; by implementing the method provided by the invention, the internal logic circuit and external environment factors of the equipment can be considered at the same time.

The invention relates to the technical field of building self-control, and discloses a building self-control real-time data processing system based on a heterogeneous computing architecture. Aiming at the problems of single data processing architecture, weak parallel processing capability, low core algorithm execution efficiency, insufficient task scheduling flexibility and the like of the existing building automatic control controller, the system innovatively adopts a heterogeneous computing architecture of a master control core, a multi-task slave core and a special hardware accelerator; and in combination with a dynamic task scheduling mechanism, a three-level data caching strategy and a multi-source data synchronous acquisition module, parallel efficient processing of multi-type building equipment data is realized. The internal logic loop period of the system is shortened to be within 15 milliseconds, the PID operation time delay is as low as 0.4 microsecond / path, the data processing throughput is improved by more than 4 times, high-frequency cooperative control of 128-path equipment is supported, meanwhile, fault redundancy and load balancing capacity is achieved, the real-time performance, the control precision and the operation reliability of the building automatic control system are remarkably improved, and the building automatic control system is suitable for large-scale popularization and application. The method is suitable for complex control scenes such as large intelligent buildings, data centers and commercial complexes.

The invention discloses a table analysis method and a table understanding model training method. The table analysis method comprises the following steps: receiving table data uploaded by a target object; according to a query request of a target object, a table understanding model is adopted to process table data to obtain a table analysis result, the table understanding model is used for analyzing a table structure and internal logic of the table data and is obtained through training of historical table data after multi-dimensional semantic enhancement and expression enhancement, and the table analysis result is obtained; semantic enhancement is used for enriching content diversity of the historical table data, and expression enhancement is used for enriching description diversity of the historical table data. According to the method and the device, the technical problems of insufficient understanding ability, relatively weak generalization ability and over-high dependence on a specific format when a large language model is used for processing structured table data in related technologies are solved.

The invention relates to an FPGA online updating implementation method based on a PCIe interface, and belongs to the technical field of embedding. On the basis of an original FPGA function module, a series of modules including the PCIe controller, the online updating module and the like are additionally added to achieve the online updating function. The mainboard sends a mirror image needing to be updated online to the FPGA through the PCIe interface, the FPGA writes the mirror image into the Flash chip through an online updating module achieved through internal logic, and online updating is achieved. Meanwhile, in the FPGA configuration mode, a multi-mirror-image scheme is adopted, that is, two or more mirror images exist in the Flash chip, only one mirror image is updated in online updating, and even if updating fails, the FPGA can be successfully configured through the other mirror image in the Flash chip. The method can be widely applied to computer products or similar scenes which are long in debugging period, difficult in structure disassembly and difficult in leading out special interfaces.

According to the product reliability analysis method and device, the electronic equipment and the storage medium, the functional parts of the product are decomposed according to the working stages, clear functional module division is formed, and the analysis precision is ensured. Through identification and combination of working state units of all the function modules, basic function units are constructed, and internal logic of product functions is further revealed. On the basis, the function transmission relation between basic function units is determined, a function implementation model of the product is constructed, an effective basis is provided for reliability simulation analysis, the effectiveness of reliability analysis work is ensured, reliability is considered in the product function design stage, and the reliability analysis efficiency is improved. The effectiveness of reliable work is guaranteed, potential quality risks can be effectively avoided, and the product quality is ensured.

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

The application provides a simulation method of a memory. The simulation method is based on: an EDA platform of integrated circuit design is used to build a front simulation key path circuit of the memory, and a front simulation net list of the memory is extracted and expanded. In a memory design layout, each global signal line is segmented, and each segment is attached to a repeated unit above it, and a post-simulation net list is extracted. Each module of the post-simulation net list is used to replace the corresponding module in the expanded front simulation net list to obtain a simplified post-simulation key path net list. The memory is simulated based on the post-simulation key path net list. The technical scheme provided by the application greatly simplifies the simulation net list for verifying the memory design while retaining the internal logic of the repeated unit, and meanwhile, the coupling effect of the internal logic of the repeated unit on the global signal is retained. In the simulation process, the net list module corresponding to the repeated unit appears only once, and the simulation speed is effectively improved.

This invention discloses a method for porting intelligent models based on domestically produced intelligent chips. The method involves using a porting tool provided by the domestically produced intelligent chip to rewrite the model, obtaining a model file corresponding to the version of the porting tool. If the internal logic of the original model has been changed, operators are added to the model file corresponding to the version of the porting tool, resulting in a model file with added operators, and proceeding to the next step. If no changes have been made, the method proceeds directly to the next step. The model file is then quantized to obtain a quantized model file. An offline model is generated based on the quantized model file. The original intelligent model and the offline model are loaded with the same computational example, and the results of the two models are compared. If the difference in the results meets the requirements, the porting process ends; otherwise, the porting problem is identified and the process restarts. This invention solves the compatibility problem of intelligent models without affecting the operating efficiency, response speed, and accuracy of the artificial intelligence model.

The invention discloses a method for testing NAND link reliability of a solid state disk, and belongs to the technical field of solid state disks. Comprising the steps that S1, an SSD master control sends a write command sequence to an NAND particle, and verification data is written into a cache unit; s2, the SSD master control polls the minimum encapsulated physical entities and the internal logic partitions of the NAND particles, sends a read command sequence, and switches data in a cache unit to a readable state; s3, the SSD master control sends a data reading time sequence, the data in the target cache unit is compared with the original test data, and if the data are inconsistent, it is judged that the link of the minimum capsulable physical entity and the link of the internal logic partition corresponding to the target cache unit are abnormal. According to the invention, the read-write test is directly carried out on the NAND cache unit, so that the interference of the inherent data jump of the Flash Array on the test result is effectively avoided.

The invention discloses a low-power-consumption short-wave portable antenna tuner and a working method thereof. The antenna tuner comprises a hardware module and a software module. The working method comprises the following steps: when the short-wave radio station works normally, all circuits are in a normal working state; after tuning of the short-wave portable antenna tuner is finished, the FPGA performs zero clearing processing on the control pin of the magnetic latching relay, so that the control pin is in a state of lowest power consumption; when the short-wave portable antenna tuner is in a normal working state, the short-wave portable antenna tuner works normally if receiving a radio station action instruction within a set time, otherwise, the hardware module and the software module enter a dormant state, the FPGA internal logic only keeps a dormant awakening module, and a trigger mechanism of a falling edge is started; and when a radio station sends data to the short-wave portable antenna tuner, the FPGA quickly awakens all hardware modules and software modules in a dormant state, so that the short-wave portable antenna tuner enters a normal working state. The invention has the advantages of low power consumption, simple circuit structure, few discrete components, low cost and 100% localization.

This invention provides a method and system for incremental retrieval index update of heterogeneous data, relating to the field of data processing technology. The method includes the following steps: batch transferring newly added information representation values ​​from the real-time cache layer to the recently active layer and performing local index optimization; analyzing the information representation values ​​in the recently active layer and the information representation values ​​in the historically stable layer and establishing jump edges; identifying invalid pointers and duplicate information fragments in the index for quickly finding similar information, and deleting invalid pointers and merging duplicate information fragments. This invention aims to solve the problems of traditional incremental update methods failing to effectively integrate different types of data when intelligent question-answering systems process massive, heterogeneous data, leading to limited retrieval efficiency and accuracy, as well as inconsistencies in internal index logic, invalid pointers, and duplicate information fragments, effectively improving system response speed and query result confidence.

The invention belongs to the technical field of new energy power generation and grid connection, discloses a grid-side converter fault ride-through control structure modeling method, system and equipment and a medium, and aims to solve the problems of difficult modeling, high cost, poor extrapolation and lack of universality caused by dependence on manufacturer internal logic or massive experimental data in the prior art. According to the method, disturbance input and current output data under a limited working condition are acquired, a dimension raising mapping function is constructed to map the input to a high-dimensional feature space, a Koopman operator is solved based on ridge regression to establish a global linear mapping model, active and reactive current reference components are predicted, and the current reference components are optimized. And finally, inputting the current inner loop time domain model to generate a current transient response curve during the fault period. According to the method, high-precision modeling and prediction can be realized only by a small number of samples, and the method has good extrapolation and universality and can be adapted to various fault ride-through strategies.

The application provides an API calling method, system, device and medium based on a meta model, which comprises the following steps: obtaining an external request based on an API interface of the meta model, performing internal protocol conversion on the external request to obtain internal logic parameters; mapping a specified model based on the internal logic parameters and executing corresponding services to obtain return parameters; performing return protocol conversion on the return parameters based on a preconfigured out-parameter template to obtain return values in a specified format, and returning the return values through the API interface. The application can meet the differentiated needs of different systems for different request addresses, request formats, return formats and exception processing formats of the same interface, and achieve cost reduction and efficiency increase in interface opening scene development.

The invention relates to the technical field of integrated circuits, and discloses a multi-FPGA global clock synchronization device and method, and the device comprises an inter-board clock synchronization circuit and an in-board clock synchronization circuit. The inter-board clock synchronization circuit comprises an inter-board clock expansion circuit and an inter-board feedback clock circuit, the input end of the inter-board clock expansion circuit is connected with an external clock and a crystal oscillator signal, and the inter-board feedback clock circuit is connected between the output end and the input end of the inter-board clock expansion circuit; the in-board clock synchronization circuit comprises an in-board clock expansion circuit and an in-board feedback clock circuit, the input end of the in-board clock expansion circuit is connected with a clock signal output by the inter-board clock synchronization circuit, and the in-board feedback clock circuit is connected between the output end and the input end of the in-board clock expansion circuit; the output end of the in-board clock expansion circuit is connected with the internal logic module. Through an inter-board / internal clock expansion circuit and a dynamic feedback compensation mechanism, clock skew between board levels and boards is eliminated, and clock synchronization of a large-scale prototype verification system is supported.