256 results about "Clock gating" patented technology

The invention provides a PCIe clock gating circuit and a PCIe clock control method. The PCIe clock gating circuit comprises a link width control circuit, a link rate control circuit and a link state control circuit, the link width control circuit is used for outputting a control signal for closing a clock of a module not related to the current width when the current link width is smaller than the maximum width; the link rate control circuit is used for outputting a control signal for closing a clock of a non-current rate related module, and the link state control circuit is used for outputting a control signal for closing a clock of an abnormal working state related module when the current link state is an abnormal working state. The abnormal working state related modules comprise related modules corresponding to other link states except the current link state; and the link state control circuit is also used for outputting a control signal for closing clocks of the training code stream sending module, the training code stream receiving module and the link training related module in a normal working state.

A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing a selected one of the set of clocks for frequency measurement through one or more clock routing subsystems. The method further includes adjusting a frequency of the selected clock after the selected clock is routed through the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.

The embodiment of the invention provides a clock gating circuit conversion method and device and related equipment, and the method comprises the steps: obtaining target circuit design data of a clock gating circuit before conversion, the target circuit design data being part of data in the circuit design data of the clock gating circuit before conversion; predicting the power consumption income of the clock gating circuit before conversion based on the target circuit design data by using a pre-established power consumption income prediction model to obtain a power consumption income prediction result; wherein the power consumption income prediction model is used for predicting a power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion so as to form a power consumption income prediction result; if it is determined that the power consumption income prediction result is the forward power consumption income, the clock gating circuit before conversion is converted into the clock gating circuit after conversion. According to the technical scheme provided by the embodiment of the invention, the efficiency of determining the switching effectiveness of the clock gating circuit can be improved.

The invention discloses a power consumption prediction and optimization method in chip design, and relates to the technical field of chip design and energy efficiency optimizing.The method comprises the steps that a circuit netlist is analyzed, functional blocks are divided, and an association diagram is constructed; generating a typical working load containing a transient peak value and a steady-state interval based on actual application; calculating dynamic and static power consumption, and considering temperature sensitive leakage current; constructing a three-dimensional thermal model, gridding a chip, solving a heat conduction equation, and outputting temperature field distribution; three-level optimization of clock gating, DVFS and data flow reconstruction is carried out on the overtemperature area; the optimized parameters are imported into a simulation tool to verify the effect, and robustness is confirmed through Monte Carlo simulation. According to the method, the power consumption prediction precision and optimization pertinence are improved, the temperature distribution uniformity is improved, the power consumption and performance are balanced, the number of design iterations is reduced, and the chip reliability and energy efficiency ratio are enhanced.

The invention provides an intelligent clock gating NoC system based on AXI interconnection and a dynamic power consumption management method, and belongs to the technical field of integrated circuit design, the system is characterized in that an AXI interconnection matrix module is provided with a crossbar switch, a master port and a slave port, and the master port and the slave port are connected with the crossbar switch through an AXI bus; each router node in the 2D Mesh network module is provided with a local port and a peripheral port, and each router node is connected with an adjacent router node through the peripheral port; the intelligent clock gating module monitors the channel flow of the AXI interconnection matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls a clock signal; and the dynamic power management module adjusts the power consumption state according to the global power optimization signal and the local optimization signal. The overall power consumption of the system-on-chip is reduced, and the stability and efficiency of data transmission are enhanced.

The invention relates to the technical field of intelligent terminals, in particular to an intelligent terminal power consumption optimization method based on active and passive identification, which comprises the following steps: passive identification acquires a first signal data set by means of a low-power-consumption wireless communication unit and based on a low-power-consumption wake-up mechanism, active identification period and passive cooperative on-demand wake-up are carried out, and cooperative data acquisition is carried out; carrying out standardized preprocessing on the data, and carrying out weighted fusion on passive electromagnetic and active characteristics according to scene priorities to generate a comprehensive scene vector; querying a predefined strategy mapping table based on the current scene category, obtaining a strategy identifier uniquely associated with the category, and loading a corresponding strategy execution parameter set from a strategy library according to the strategy identifier; analyzing the strategy parameter, generating a time sequence instruction, executing clock gating on the target hardware unit in sequence, and sending instructions by the power supply and the bus arbiter to complete power consumption state switching. The accuracy of scene judgment is improved through an active and passive fusion mechanism, and power consumption regulation and control deviation caused by scene misjudgment is effectively avoided.

An OCC synchronization control system for cross-clock domain path scan testing is disclosed. The system comprises a first OCC and a second OCC, the first OCC is used for controlling test clock output of a first clock domain before frequency division, the second OCC is used for controlling test clock output of a second clock domain after frequency division, the first OCC receives a first high-speed clock signal, and the second OCC receives a second high-speed clock signal; the first OCC and the second OCC share the same group of trigger synchronization logic and are used for processing the synchronous trigger signal crossing the clock domain and providing synchronous control input for respective clock gating units, so that the first OCC and the second OCC generate respective test clock output under the same trigger reference. According to the OCC synchronous control system disclosed by the invention, in a circuit with a clock frequency divider, at least two OCCs are fused to share the same capture to trigger synchronous logic, so that synchronous clock pulse generation of clock domains before and after frequency division is realized, and the test coverage rate of a cross-clock path is improved.

The invention relates to the technical field of chips, in particular to a chip clock frequency control system based on voltage change, which comprises a delay digital converter, a judgment module, a phase-locked loop and a clock gating module, the judgment module comprises a lookup table, and the lookup table comprises a first DDC output value range [a, b], a first adjustment mode corresponding to the first DDC output value range, a second DDC output value range [b, c], a second adjustment mode corresponding to the second DDC output value range, a third DDC output value range [c, + infinity] and a third adjustment mode corresponding to the third DDC output value range; the clock frequency adjustment amplitudes of the first adjustment mode, the second adjustment mode and the third adjustment mode are sequentially increased; the delay digital converter is connected with the judgment module, the judgment module is respectively connected with the phase-locked loop and the clock gating module, and the phase-locked loop is connected with the clock gating module. According to the invention, the clock frequency of the chip is smoothly and effectively adjusted based on voltage change.

The invention discloses an ultra-low power consumption LoRa backscatter communication system based on an FPGA (Field Programmable Gate Array) and a design method thereof. Comprising a LoRa transmitter, a LoRa receiver, an upper computer and a LoRa backscattering terminal. The LoRa transmitter transmits a sine wave signal with a certain frequency. And the LoRa receiver receives and demodulates the backscattering signal, and then sends the demodulated signal to the upper computer. And the upper computer receives the demodulated signal, completes audio decompression and plays the audio. According to the backscattering terminal, an FPGA serves as a master control, and the FPGA completes the functions of audio compression, LoRa physical layer protocol processing and a LoRa backscattering algorithm. According to the invention, a LoRa backscattering algorithm based on table look-up is designed, then a multi-clock design method and a clock gating technology are provided to optimize system power consumption and communication performance, and outdoor testing is carried out on a scattering terminal. According to the invention, the performance advantages of the FPGA are exerted, and the ultra-low power consumption of the terminal is maintained.

A receive clock generated at a receiver coupled to a single wire bus is synchronized in each clock cycle, allowing for receiving infinite length data frames without clock overflow or underload. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in the output of the clock gating circuit. The clock gating circuit is disabled when the output of the counter indicates a pre-configured maximum count value. An edge synchronization circuit that synchronizes an edge in the basic clock signal with an edge in a data signal received through the single wire bus ignores the edge in the data signal when the counter output has a value less than the maximum count value, and resetting the counter in response to an edge detected in the data signal received through the single wire bus.

To reduce power consumption, data bits or a portion of a data register that is not expected to toggle frequently can be grouped together, and be clock-gated independently from the rest of the data register. The grouping of the data bits can be determined based on the data types of the workload being operated on. For a data register configured to store a numeric value that supports multiple data types, the portion of the data register being clock-gated may store a group of data bits that are unused for one or more data types of the multiple data types supported by the data register. The portion of the data register being clock-gated can also be a group of data bits that remain unchanged or have a constant value for numeric values within a certain numeric range that is frequently operated on.

The invention provides a satellite communication SoC chip power consumption control method and device, and the method comprises the steps: monitoring the comprehensive operation parameters of all function modules in real time, calculating the power consumption demand through combining the characteristics of a satellite orbit, generating a power consumption control instruction, carrying out the intelligent clock gating and frequency adjustment operation of the function modules, and achieving the power consumption control of the function modules. And finally, accurate distribution control of power consumption is realized. According to the method, real-time optimization management of power consumption can be realized according to dynamic changes of satellite communication services and orbit periodicity characteristics, the in-orbit service life of a satellite is effectively prolonged, and the overall power consumption level is reduced.

The invention relates to the technical field of chips, and provides a time sequence optimization method and device for a clock control path, a medium and a program product, and the method comprises the steps: inserting a multi-stage register on the clock control path of a target circuit module according to the physical size and target frequency of the target circuit module, and constructing to obtain an assembly line chain; fixing a last-stage register of the assembly line chain at a target position; constructing a clock network on the premise of keeping the position of the last-stage register fixed, and in the process of constructing the clock network, shielding a time sequence constraint from the last-stage register to a clock gating unit controlled by the last-stage register; and after the clock network is constructed, physical connection between the clock gating unit and the last-stage register is established, and time sequence optimization is performed on a clock control path between the last-stage register and the clock gating unit. According to the method, power consumption surge, wiring congestion and violation risks caused by an overlong path are avoided, and the time sequence convergence rate and the resource utilization rate of the high-performance chip in the sign-off stage are remarkably improved.

The invention provides a low-power-consumption feed-forward equalizer circuit which comprises a grouping processing module which divides tap values of tap coefficients of the feed-forward equalizer circuit into a plurality of groups, each group comprises a plurality of tap values, and a tap combination value needing to be processed by each lookup table module is calculated; the lookup table module is used for storing the tap combination value which is calculated in advance and performing lookup operation according to the bit combination of the input data to generate an intermediate result; the clock gating trigger module is used for enabling a signal tapdata to be equal to 1 when a tap value is updated, completing updating of the tap value output by a register DFF, and closing an input clock of the DFF when the tap value is kept unchanged and the tapdata is equal to 0; the shift accumulation module performs weight shift operation on the intermediate results output by the lookup table module and then accumulates the intermediate results to generate a plurality of groups of tap value processing results; and the result output module outputs a final equalization signal of the feed-forward equalizer circuit. The FFE circuit is realized by converting the multiplier into the LUT table and the adder, and the power consumption of the FFE circuit is greatly reduced while the signal processing performance of the FFE circuit is ensured.

Disclosed embodiments relate to predicting when a fetch address will hit in a trace cache, e.g., to reduce power consumption when a hit is not predicted. In some embodiments, a processor caches instructions sequentially in a given cache line of instruction cache circuitry. The processor may identify traces of instructions that satisfy one or more criteria and store identified traces in a trace cache. The processor may predict whether a fetch address will hit in the trace cache circuitry. The processor may read in response to a prediction that the fetch address will not hit in the trace cache, instruction data from the instruction cache circuitry and not the trace cache circuitry for the fetch address. The processor may reduce power to (e.g., clock gate) portions of the trace cache circuitry in this scenario.

An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate / pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate / pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

The invention provides a wireless mouse low-power-consumption intelligent optimization method based on deep learning, and the method comprises the steps: achieving the real-time collection of the operation state data of a wireless mouse through a multi-sensor fusion technology, building a power consumption prediction model based on a long and short-term memory network, so as to learn the time sequence relation between the user behavior and the mouse power consumption change, based on a prediction result, an intelligent power consumption control strategy optimization model is constructed, an optimal power consumption control strategy is generated through a strategy iterative optimization method in combination with parameter configuration of power management, clock gating, sensor sampling and the like, power consumption control parameters are analyzed, and a control instruction is generated. The CPU dominant frequency of the mouse, the voltage of a power management unit, the sampling rate of a sensor and a peripheral working mode are dynamically adjusted, and a power consumption control strategy is optimized by adopting a negative feedback mechanism. According to the wireless mouse, the energy consumption of the wireless mouse can be effectively reduced, meanwhile, the operation smoothness is guaranteed, and the cruising ability and the user experience are improved.

The name of the invention is' early exit of RELU-based activation '. One embodiment provides a graphics processor comprising a memory interface and a processing resource coupled with the memory interface. The processing resources include circuit modules configured to perform operations fused with rectified linear unit operations. The circuit module is configured to detect a negative output of the operation prior to completion of the operation, clock-gate a portion of the circuit module, and operate an output zero for the rectified linear unit.

The embodiment of the invention discloses an integrated circuit device and an internal data transmission control method of the integrated circuit device, which are invented for reducing the power consumption of the integrated circuit device. The integrated circuit device includes: a data forwarding unit connected to an upstream unit that transmits or forwards data and to a downstream unit that receives or forwards data; the first input end of the clock gating unit is connected with the normally open clock, and the second input end of the clock gating unit is used for inputting a clock control signal; and the output end of the clock gating unit is connected with the clock input end of the data forwarding unit, so that the clock input end of the data forwarding unit is controlled to have or have no normally open clock signal input according to a clock control signal input by the second input end of the clock gating unit. The method is suitable for data transmission in the chip.

Provided are a logic built-in self-test (BIST) circuit that performs a scan test improving test coverage for each clock domain and a semiconductor device including the logic BIST circuit. The logic BIST circuit includes an OR gate configured to receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to output an enable clock irrespective of a function enable signal when the register setting signal has a first logic value, and a scan chain configured to capture an output of a first logic circuit connected to flip-flops according to the enable clock.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

A flip-flop with clock gating based on data comparison is disclosed. The flip-flop unit includes an edge-triggered flip-flop and a clock gating circuit. The clock gating circuit enables or disables a first clock signal to generate a second clock signal according to a data comparison result of input data and output data. The second clock signal provides a triggering edge of the edge-triggered flip-flop. The clock gating circuit copies the first clock signal as the second clock signal in a clock cycle during which the input data is flipped, and maintains the second clock signal at a predetermined level in clock cycles during which the input data remains unchanged. The flip-flop unit enables the clock flip of the edge-triggered flip-flop only in a clock cycle during which the input data is flipped, thereby improving the circuit performance and reducing the power consumption.

A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.

The invention relates to a linear frequency digit generation method and system. The method comprises the following steps: determining a total cycle period, a maximum frequency coefficient, minimum frequency division precision, a frequency coefficient and a linear frequency range based on an application scene; acquiring a current frequency division clock corresponding to the current application scene, and calculating control parameters required during current frequency division control; waiting for completion of control parameter calculation and taking effect; performing frequency division control based on the control parameter, and when the falling edge of the original clock arrives, generating a clock gating signal according to the value of the counter in the period; and the steps are sequentially alternated until the total cycle period is reached. According to the invention, linear frequency generation and application scenes are combined, frequency division control is realized by adopting a digital logic mode, different requirements of different application scenes can be adapted, and EMC performance can be effectively improved.

One embodiment provides a graphics processor comprising a memory interface and a processing resource coupled with the memory interface. The processing resource including circuitry configured to perform an operation fused with a rectified linear unit operation. The circuitry is configured to detect a negative output of the operation before completion of the operation, clock gate a portion of the circuitry, and output a zero value for the rectified linear unit operation.

The invention discloses clock gating of an idle index flip-flop array, and specifically describes a system comprising: a first storage element having a plurality of data storage locations; a second storage element having a bit array indicating availability of a corresponding data storage location of the plurality of data storage locations; and a control circuit. The control circuit may include at least a first switching element coupled to a first set of bits in the bit array and at least a second switching element coupled to a second set of bits in the bit array, the at least first switching element selectively enabling the first set of bits to be read or written in response to activation by a first clock gating signal; the at least second switching element selectively enables a second set of bits to be read or written in response to activation by a second clock gating signal.

The invention discloses a dynamic multi-domain power consumption regulation-based ultra-low power consumption design method for an AI voice chip. The method comprises the following steps of 1, designing a chip power supply scheme and a clock scheme according to an application scene of a system; 2, designing a multi-level layered clock gating architecture control system; step 3, dividing the power supply network into a dynamic power supply domain and a normally open power supply domain; step 4, cache compression design of voice data is carried out; step 5, minimum addressable unit grouping optimization is carried out on a memory, and minimum addressable units with different granularities are supported to implement selective turn-off; and step 6, completing the design after the simulation is passed and an expected target is reached. Through a hierarchical gating layer design method, bidirectional optimization of dynamic energy efficiency management and time sequence precision is realized, and the overall clock power consumption is reduced.

A micro-light emitting diode (micro-LED) display backplane includes a plurality of macro-pixels. Each macro-pixel includes: a contiguous two-dimensional (2-D) array of bitcells storing display data bits for driving a set of micro-LEDs of a 2-D array of micro-LEDs; and drive circuits configured to generate, based on the display data bits stored in the contiguous 2-D array of bitcells, pulse-width modulated (PWM) drive signals for driving the set of micro-LEDs of the 2-D array of micro-LEDs. In one example, the plurality of macro-pixels is grouped into a plurality of sub-arrays, where each sub-array of the plurality of sub-arrays includes a set of macro-pixels and a local periphery circuit next to the set of macro-pixels. The local periphery circuit includes, for example, a buffer, a repeater, a clock gating circuit for gating an input clock signal to the sub-array, and / or a sub-array decoder for selecting the sub-array.