159 results about "Clock gating" patented technology

The invention discloses a power consumption prediction and optimization method in chip design, and relates to the technical field of chip design and energy efficiency optimizing.The method comprises the steps that a circuit netlist is analyzed, functional blocks are divided, and an association diagram is constructed; generating a typical working load containing a transient peak value and a steady-state interval based on actual application; calculating dynamic and static power consumption, and considering temperature sensitive leakage current; constructing a three-dimensional thermal model, gridding a chip, solving a heat conduction equation, and outputting temperature field distribution; three-level optimization of clock gating, DVFS and data flow reconstruction is carried out on the overtemperature area; the optimized parameters are imported into a simulation tool to verify the effect, and robustness is confirmed through Monte Carlo simulation. According to the method, the power consumption prediction precision and optimization pertinence are improved, the temperature distribution uniformity is improved, the power consumption and performance are balanced, the number of design iterations is reduced, and the chip reliability and energy efficiency ratio are enhanced.

The invention relates to the technical field of intelligent terminals, in particular to an intelligent terminal power consumption optimization method based on active and passive identification, which comprises the following steps: passive identification acquires a first signal data set by means of a low-power-consumption wireless communication unit and based on a low-power-consumption wake-up mechanism, active identification period and passive cooperative on-demand wake-up are carried out, and cooperative data acquisition is carried out; carrying out standardized preprocessing on the data, and carrying out weighted fusion on passive electromagnetic and active characteristics according to scene priorities to generate a comprehensive scene vector; querying a predefined strategy mapping table based on the current scene category, obtaining a strategy identifier uniquely associated with the category, and loading a corresponding strategy execution parameter set from a strategy library according to the strategy identifier; analyzing the strategy parameter, generating a time sequence instruction, executing clock gating on the target hardware unit in sequence, and sending instructions by the power supply and the bus arbiter to complete power consumption state switching. The accuracy of scene judgment is improved through an active and passive fusion mechanism, and power consumption regulation and control deviation caused by scene misjudgment is effectively avoided.

The invention provides a satellite communication SoC chip power consumption control method and device, and the method comprises the steps: monitoring the comprehensive operation parameters of all function modules in real time, calculating the power consumption demand through combining the characteristics of a satellite orbit, generating a power consumption control instruction, carrying out the intelligent clock gating and frequency adjustment operation of the function modules, and achieving the power consumption control of the function modules. And finally, accurate distribution control of power consumption is realized. According to the method, real-time optimization management of power consumption can be realized according to dynamic changes of satellite communication services and orbit periodicity characteristics, the in-orbit service life of a satellite is effectively prolonged, and the overall power consumption level is reduced.

The invention relates to the technical field of chips, and provides a time sequence optimization method and device for a clock control path, a medium and a program product, and the method comprises the steps: inserting a multi-stage register on the clock control path of a target circuit module according to the physical size and target frequency of the target circuit module, and constructing to obtain an assembly line chain; fixing a last-stage register of the assembly line chain at a target position; constructing a clock network on the premise of keeping the position of the last-stage register fixed, and in the process of constructing the clock network, shielding a time sequence constraint from the last-stage register to a clock gating unit controlled by the last-stage register; and after the clock network is constructed, physical connection between the clock gating unit and the last-stage register is established, and time sequence optimization is performed on a clock control path between the last-stage register and the clock gating unit. According to the method, power consumption surge, wiring congestion and violation risks caused by an overlong path are avoided, and the time sequence convergence rate and the resource utilization rate of the high-performance chip in the sign-off stage are remarkably improved.

The invention provides a low-power-consumption feed-forward equalizer circuit which comprises a grouping processing module which divides tap values of tap coefficients of the feed-forward equalizer circuit into a plurality of groups, each group comprises a plurality of tap values, and a tap combination value needing to be processed by each lookup table module is calculated; the lookup table module is used for storing the tap combination value which is calculated in advance and performing lookup operation according to the bit combination of the input data to generate an intermediate result; the clock gating trigger module is used for enabling a signal tapdata to be equal to 1 when a tap value is updated, completing updating of the tap value output by a register DFF, and closing an input clock of the DFF when the tap value is kept unchanged and the tapdata is equal to 0; the shift accumulation module performs weight shift operation on the intermediate results output by the lookup table module and then accumulates the intermediate results to generate a plurality of groups of tap value processing results; and the result output module outputs a final equalization signal of the feed-forward equalizer circuit. The FFE circuit is realized by converting the multiplier into the LUT table and the adder, and the power consumption of the FFE circuit is greatly reduced while the signal processing performance of the FFE circuit is ensured.

Disclosed embodiments relate to predicting when a fetch address will hit in a trace cache, e.g., to reduce power consumption when a hit is not predicted. In some embodiments, a processor caches instructions sequentially in a given cache line of instruction cache circuitry. The processor may identify traces of instructions that satisfy one or more criteria and store identified traces in a trace cache. The processor may predict whether a fetch address will hit in the trace cache circuitry. The processor may read in response to a prediction that the fetch address will not hit in the trace cache, instruction data from the instruction cache circuitry and not the trace cache circuitry for the fetch address. The processor may reduce power to (e.g., clock gate) portions of the trace cache circuitry in this scenario.

The invention provides a wireless mouse low-power-consumption intelligent optimization method based on deep learning, and the method comprises the steps: achieving the real-time collection of the operation state data of a wireless mouse through a multi-sensor fusion technology, building a power consumption prediction model based on a long and short-term memory network, so as to learn the time sequence relation between the user behavior and the mouse power consumption change, based on a prediction result, an intelligent power consumption control strategy optimization model is constructed, an optimal power consumption control strategy is generated through a strategy iterative optimization method in combination with parameter configuration of power management, clock gating, sensor sampling and the like, power consumption control parameters are analyzed, and a control instruction is generated. The CPU dominant frequency of the mouse, the voltage of a power management unit, the sampling rate of a sensor and a peripheral working mode are dynamically adjusted, and a power consumption control strategy is optimized by adopting a negative feedback mechanism. According to the wireless mouse, the energy consumption of the wireless mouse can be effectively reduced, meanwhile, the operation smoothness is guaranteed, and the cruising ability and the user experience are improved.

The name of the invention is' early exit of RELU-based activation '. One embodiment provides a graphics processor comprising a memory interface and a processing resource coupled with the memory interface. The processing resources include circuit modules configured to perform operations fused with rectified linear unit operations. The circuit module is configured to detect a negative output of the operation prior to completion of the operation, clock-gate a portion of the circuit module, and operate an output zero for the rectified linear unit.

Provided are a logic built-in self-test (BIST) circuit that performs a scan test improving test coverage for each clock domain and a semiconductor device including the logic BIST circuit. The logic BIST circuit includes an OR gate configured to receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to output an enable clock irrespective of a function enable signal when the register setting signal has a first logic value, and a scan chain configured to capture an output of a first logic circuit connected to flip-flops according to the enable clock.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.

The invention discloses clock gating of an idle index flip-flop array, and specifically describes a system comprising: a first storage element having a plurality of data storage locations; a second storage element having a bit array indicating availability of a corresponding data storage location of the plurality of data storage locations; and a control circuit. The control circuit may include at least a first switching element coupled to a first set of bits in the bit array and at least a second switching element coupled to a second set of bits in the bit array, the at least first switching element selectively enabling the first set of bits to be read or written in response to activation by a first clock gating signal; the at least second switching element selectively enables a second set of bits to be read or written in response to activation by a second clock gating signal.

This application relates to a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments in the field of integrated circuit design technology. The latch includes: an excitation module for transmitting input signals to sensitive nodes N2, N4, N6, and Q through multiple clock-controlled transmission gates; an interlock feedback loop consisting of four three-input clock-gated inverting CE units and four three-input inverting CE units; a module responsible for generating voltages for sensitive nodes N1, N3, N5, and N7, and for achieving interference self-recovery of sensitive nodes N1 to N7 and Q based on signals from sensitive nodes A and B; and an AB node generation and recovery module using two four-input inverting CE units and inversion operation to generate voltages for sensitive nodes A and B from signals from N1 to N7 and Q. This latch has good TNU (Terror-Noise Nullification) immunity, enabling three-node flip-flop recovery even when any three sensitive nodes experience a TNU.

The invention relates to a clock gating circuit and a corresponding system. A reset domain crossover circuit deasserts a clock enable signal in response to receiving an asserted software reset write request signal, and asserts the clock enable circuit in response to detecting a falling edge on the software reset signal. The reset domain crossover circuit comprises a synchronizer, a falling edge detection circuit and a clock enable circuit, wherein the synchronizer receives a software reset signal and generates a synchronous software reset signal; the falling edge detection circuit receives a synchronization software reset signal from a synchronizer and generates a falling edge signal when a falling edge on the synchronization software reset signal is detected. The clock enable circuit is coupled to a falling edge detection circuit that receives a falling edge signal.

The present invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency divider includes a plurality of registers, a counter, a control signal generator, and a clock gating circuit. With respect to the plurality of registers, at least a portion of the plurality of registers is set to have a value. The counter is configured to sequentially generate a plurality of count values, wherein the plurality of count values ​​respectively correspond to the at least a portion of the registers, and the plurality of count values ​​are repeatedly generated. The control signal generator is configured to generate a control signal based on the received count value and the corresponding register value. The clock gating circuit is configured to mask or unmask an input clock signal based on the control signal to generate an output clock signal.

This application relates to a low-power ruggedized module with controllable clock edge timing. The module includes a clock gating circuit, a ruggedized unit, and a clock and power supply module. In the clock gating circuit, the substrates of two PMOS transistors are connected to a variable DC power supply to achieve controllable clock edge timing. The ruggedized unit uses a cross-coupled CMOS bistable structure through a bistable latch module to store the synchronous data after clock gating in nodes X0 to X3, and inputs the data to nodes X0 to X3 through an input path via an input control module. In the clock and power supply module, the voltage VDD is set to 1V, reducing overall power consumption and saving energy. This module has the function of resisting six-node flip-flops, making it more robust and safer.

The invention discloses a circuit structure and a method for ensuring the stability of a clock circuit signal in a power-on stage, and the circuit structure comprises an asynchronous frequency divider which is formed by cascading a plurality of stages of D triggers and is triggered by an output signal of a clock circuit; the clock gating unit is used for shielding a current signal output by the asynchronous frequency divider after the count of the asynchronous frequency divider reaches a set parameter and a frequency division clock signal is started to be output; and the clock stability judgment logic circuit is used for carrying out stability judgment on the shielded signal, and when the judgment result is stable, the clock gating unit relieves shielding on the current crystal oscillator clock signal and transmits the current crystal oscillator clock signal to the digital circuit. Through a circuit structure of an asynchronous frequency divider and a gated clock technology, a crystal oscillator clock is safely and reliably converted into a working clock of a digital circuit.

The present invention relates to a structured chip design architecture and method, which includes a segmentation component, an idle state signal adding component, a clock generation component and a clock tree synthesis component; the segmentation component is used to perform appropriate module segmentation and hierarchical segmentation on each submodule of each IP module of the chip; the idle state signal adding component is used to add a module idle state signal to each submodule; the clock generation component is used to call a clock gating unit before each submodule, generate a gated clock according to the corresponding module idle state signal and send it to the corresponding submodule; the clock tree synthesis component is used to, during clock tree synthesis, output a segmented long clock tree from the clock of the clock gating unit according to the idea of ​​segmenting a long clock tree.

The application relates to the technical field of integrated circuits and provides a built-in self-test circuit and method for a chip. The circuit comprises a control bidirectional selector for establishing a control path relationship among a plurality of objects to be tested; a data bidirectional selector for establishing a data path relationship; a management component for performing independent clock gating operations on input clock trees of the plurality of objects to be tested and performing independent system reset operations on input reset signals; and a test component for coordinating the components to set the control path relationship and the data path relationship among one or more objects to be tested according to a serial relationship, a parallel relationship or a serial-parallel mixed application relationship and to perform testing. Thus, various communication protocols and interface standards can be adapted, and the requirements of chip design development and chip testing for shortening chip testing time and fast response to changes can be met.

The invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency eliminator comprises a plurality of temporary memories, a counter, a control signal generator and a clock pulse gating circuit. At least a portion of the plurality of registers is set to have a value with respect to the plurality of registers. The counter is used for sequentially generating a plurality of count values, the plurality of count values respectively correspond to the at least one part of the temporary register, and the plurality of count values are repeatedly generated. The control signal generator is used for generating a control signal according to the received count value and the value of the corresponding register. The clock gating circuit is used for referring to the control signal to shield or not shield an input clock signal so as to generate an output clock signal.

The invention relates to a low-power-consumption reinforcement module capable of controlling clock edge time. The module comprises a clock gating circuit, a reinforcement unit and a clock and power supply module, in the clock gating circuit, the substrates of the two PMOS transistors are connected with a variable direct-current power supply, so that the function of controlling the clock edge time is realized; the reinforcing unit stores synchronous data after clock gating at nodes X0 to X3 through a bistable latch module by adopting a cross-coupled CMOS bistable structure, and inputs the data to the nodes X0 to X3 through an input control module by adopting an input path; the voltage VDD is set to be 1V in the clock and power supply module, so that the overall power consumption is reduced, and the energy is saved; the module has the function of resisting six-node overturning, and is more stable and higher in safety.

A core circuit in a processor executes instructions in an operating mode and, when the core circuit is idle, transitions to a low-power mode to reduce power consumption. Low power modes include a clock-gated mode, in which a clock signal is blocked, and a power-collapse mode, in which a supply voltage is shut off. An exemplary core control circuit may transition the core circuit from the operating mode to the clock-gated mode to reduce power consumption and then transition the core circuit from the clock-gated mode to the power-collapse mode to further reduce power consumption. The core control circuit is also configured to transition the core circuit back to the operating mode. The core control circuit may transition the core circuit to the power-collapse mode in response to a signal from a timer circuit and transitions the core circuit back to the operating mode in response to an interrupt signal.

The application provides a PCIe clock gating circuit and a PCIe clock control method. The circuit comprises a link width control circuit, a link rate control circuit and a link state control circuit. The link width control circuit is configured to output a control signal for closing the clock of a non-current width related module when the current link width is less than the maximum width. The link rate control circuit is configured to output a control signal for closing the clock of a non-current rate related module. The link state control circuit is configured to output a control signal for closing the clock of a non-normal working state related module when the current link state is a non-normal working state. The non-normal working state related module comprises a related module corresponding to other link states except the current link state. The link state control circuit is further configured to output a control signal for closing the clock of a training code stream sending module, a training code stream receiving module and a link training related module when in a normal working state.

A high-speed serial interface includes a physical layer circuit at a transmit end, a monitor, a clock gating circuit, a control bitstream generation circuit, and a random bitstream generation circuit. The monitor is configured to: when no service data is being sent, instruct the clock gating circuit to stop sending a clock signal to partial modules in the physical layer circuit at the transmit end. The control bitstream generation circuit sends a first control bitstream through a serializer / deserializer (SerDes), to indicate that the transmit end has turned off partial modules in the physical layer (PHY) circuit at the transmit end and so on. The random bitstream generation circuit sends a random bitstream.

Clock gating cells and integrated circuits are provided. The clock gating cell can include a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal, an inverter configured to receive the second signal and generate a clock output, and a 3-input logic gate including a second 2-input logic gate, the 3-input logic gate configured to generate the first signal. The first 2-input logic gate and the second 2-input logic gate form a set-reset (SR) latch through cross-coupling, the 3-input logic gate includes a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, and activation of the feedback transistor by the internal signal is configured to avoid a race condition by preventing pull-up or pull-down of a first node at which the first signal is generated.

The invention belongs to the technical field of electronic design automation, and provides a statistical method of a gating register, electronic equipment and a storage medium, the method comprises the following steps: starting from a top layer module of circuit design, taking a root clock port on the top layer module as an initial node, and traversing a clock tree of the circuit design along a clock signal propagation direction; key-value pairs are maintained in a pre-created mapping container through traversal, the flattened net is stored as keys, and a clock gating unit set corresponding to the flattened net is stored as values; based on a flattening line net connected with a sink pin of a register in the circuit design, a target clock gating unit set corresponding to the register is determined in the mapping container, clock gating units in the target clock gating unit set are associated with the register, and the sink pin is a clock signal input end. According to the method, the information of the gating register can be accurately counted, and the time complexity of counting is optimized.

This invention discloses a low-power ATPG method, apparatus, chip, chip module, and terminal device. The low-power ATPG method involves minimizing inverter insertion / deletion in the scan chain data path without altering the functional path. This maximizes the shutdown of the chip's integrated clock gating after Shift-0 vector loading, significantly reducing capture-to-flip rate and shift-to-flip rate. This method modifies only the scan chain data structure without affecting the functional path timing, offering advantages such as minimal hardware overhead, significantly reduced power consumption, fewer vectors, and high automation. It can be widely applied in low-power testing processes for various chips, chip modules, terminals, and base stations.

The disclosed apparatus includes various circuit blocks and a clock tree for sending clock signals to the circuit blocks. The clock tree includes various clock drivers. The apparatus also includes control circuitry to power gate a portion of the clock tree including one of the clock drivers in response to one of the circuit blocks being power gated. Various other methods, systems, and computer readable media are also disclosed.

During a low power mode, a fast clock may not be provided to serial / parallel conversion circuitry. An asynchronous gating signal that controls the gating of the fast clock may be synchronized to a slow clock and the fast clock. The frequency of the fast clock may be an integer multiple of the slow clock, such that gating the fast clock based on the fast-slow clock synchronized gating signal results in the gating of the fast clock lasting for a duration that may be an integer multiple of the serialization factor multiplied by the conversion circuitry FIFO buffer depth. This maintains the relationship between the FIFO buffer's read and write pointers and associated clocking circuitry during the clock shutoff period. By maintaining these relationships during the clock shutoff period, the serial / parallel conversion circuitry may enter and exit the low power mode without requiring retraining as data path latencies remain unchanged.