90 results about "Clock gating" patented technology

The invention relates to the technical field of intelligent terminals, in particular to an intelligent terminal power consumption optimization method based on active and passive identification, which comprises the following steps: passive identification acquires a first signal data set by means of a low-power-consumption wireless communication unit and based on a low-power-consumption wake-up mechanism, active identification period and passive cooperative on-demand wake-up are carried out, and cooperative data acquisition is carried out; carrying out standardized preprocessing on the data, and carrying out weighted fusion on passive electromagnetic and active characteristics according to scene priorities to generate a comprehensive scene vector; querying a predefined strategy mapping table based on the current scene category, obtaining a strategy identifier uniquely associated with the category, and loading a corresponding strategy execution parameter set from a strategy library according to the strategy identifier; analyzing the strategy parameter, generating a time sequence instruction, executing clock gating on the target hardware unit in sequence, and sending instructions by the power supply and the bus arbiter to complete power consumption state switching. The accuracy of scene judgment is improved through an active and passive fusion mechanism, and power consumption regulation and control deviation caused by scene misjudgment is effectively avoided.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.

This application relates to a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments in the field of integrated circuit design technology. The latch includes: an excitation module for transmitting input signals to sensitive nodes N2, N4, N6, and Q through multiple clock-controlled transmission gates; an interlock feedback loop consisting of four three-input clock-gated inverting CE units and four three-input inverting CE units; a module responsible for generating voltages for sensitive nodes N1, N3, N5, and N7, and for achieving interference self-recovery of sensitive nodes N1 to N7 and Q based on signals from sensitive nodes A and B; and an AB node generation and recovery module using two four-input inverting CE units and inversion operation to generate voltages for sensitive nodes A and B from signals from N1 to N7 and Q. This latch has good TNU (Terror-Noise Nullification) immunity, enabling three-node flip-flop recovery even when any three sensitive nodes experience a TNU.

The invention relates to a clock gating circuit and a corresponding system. A reset domain crossover circuit deasserts a clock enable signal in response to receiving an asserted software reset write request signal, and asserts the clock enable circuit in response to detecting a falling edge on the software reset signal. The reset domain crossover circuit comprises a synchronizer, a falling edge detection circuit and a clock enable circuit, wherein the synchronizer receives a software reset signal and generates a synchronous software reset signal; the falling edge detection circuit receives a synchronization software reset signal from a synchronizer and generates a falling edge signal when a falling edge on the synchronization software reset signal is detected. The clock enable circuit is coupled to a falling edge detection circuit that receives a falling edge signal.

This application relates to a low-power ruggedized module with controllable clock edge timing. The module includes a clock gating circuit, a ruggedized unit, and a clock and power supply module. In the clock gating circuit, the substrates of two PMOS transistors are connected to a variable DC power supply to achieve controllable clock edge timing. The ruggedized unit uses a cross-coupled CMOS bistable structure through a bistable latch module to store the synchronous data after clock gating in nodes X0 to X3, and inputs the data to nodes X0 to X3 through an input path via an input control module. In the clock and power supply module, the voltage VDD is set to 1V, reducing overall power consumption and saving energy. This module has the function of resisting six-node flip-flops, making it more robust and safer.

The application relates to the technical field of integrated circuits and provides a built-in self-test circuit and method for a chip. The circuit comprises a control bidirectional selector for establishing a control path relationship among a plurality of objects to be tested; a data bidirectional selector for establishing a data path relationship; a management component for performing independent clock gating operations on input clock trees of the plurality of objects to be tested and performing independent system reset operations on input reset signals; and a test component for coordinating the components to set the control path relationship and the data path relationship among one or more objects to be tested according to a serial relationship, a parallel relationship or a serial-parallel mixed application relationship and to perform testing. Thus, various communication protocols and interface standards can be adapted, and the requirements of chip design development and chip testing for shortening chip testing time and fast response to changes can be met.

A high-speed serial interface includes a physical layer circuit at a transmit end, a monitor, a clock gating circuit, a control bitstream generation circuit, and a random bitstream generation circuit. The monitor is configured to: when no service data is being sent, instruct the clock gating circuit to stop sending a clock signal to partial modules in the physical layer circuit at the transmit end. The control bitstream generation circuit sends a first control bitstream through a serializer / deserializer (SerDes), to indicate that the transmit end has turned off partial modules in the physical layer (PHY) circuit at the transmit end and so on. The random bitstream generation circuit sends a random bitstream.

The invention belongs to the technical field of electronic design automation, and provides a statistical method of a gating register, electronic equipment and a storage medium, the method comprises the following steps: starting from a top layer module of circuit design, taking a root clock port on the top layer module as an initial node, and traversing a clock tree of the circuit design along a clock signal propagation direction; key-value pairs are maintained in a pre-created mapping container through traversal, the flattened net is stored as keys, and a clock gating unit set corresponding to the flattened net is stored as values; based on a flattening line net connected with a sink pin of a register in the circuit design, a target clock gating unit set corresponding to the register is determined in the mapping container, clock gating units in the target clock gating unit set are associated with the register, and the sink pin is a clock signal input end. According to the method, the information of the gating register can be accurately counted, and the time complexity of counting is optimized.

The disclosed apparatus includes various circuit blocks and a clock tree for sending clock signals to the circuit blocks. The clock tree includes various clock drivers. The apparatus also includes control circuitry to power gate a portion of the clock tree including one of the clock drivers in response to one of the circuit blocks being power gated. Various other methods, systems, and computer readable media are also disclosed.

During a low power mode, a fast clock may not be provided to serial / parallel conversion circuitry. An asynchronous gating signal that controls the gating of the fast clock may be synchronized to a slow clock and the fast clock. The frequency of the fast clock may be an integer multiple of the slow clock, such that gating the fast clock based on the fast-slow clock synchronized gating signal results in the gating of the fast clock lasting for a duration that may be an integer multiple of the serialization factor multiplied by the conversion circuitry FIFO buffer depth. This maintains the relationship between the FIFO buffer's read and write pointers and associated clocking circuitry during the clock shutoff period. By maintaining these relationships during the clock shutoff period, the serial / parallel conversion circuitry may enter and exit the low power mode without requiring retraining as data path latencies remain unchanged.

The application discloses a neuromorphic processor supporting asynchronous event driving, comprising: an event dispatcher, configured to receive events and send the events to a neuromorphic processing core or an event queue according to a current time step state; the event dispatcher is configured to ensure the correctness of the event processing sequence through time step conflict detection and a timestamp-based scheduling strategy; the event queue is configured to cache non-current time step events or events that cannot be processed immediately; the neuromorphic processing core is configured to execute an event processing program based on a neuromorphic instruction set architecture; the neuromorphic instruction set comprises a BRE instruction, configured to dynamically jump to a corresponding processing program according to an event type, and realize low-power mode switching in cooperation with a clock gating module; the processor executes the BRE instruction after the event processing is completed, enters a sleep state, and suspends a clock signal through the clock gating until a new event arrives. The application has the advantages of good compatibility, good adaptability, low power consumption and the like.

The invention discloses a low-power-consumption management device and method for an SATA (Serial Advanced Technology Attachment) controller, which relate to the technical field of SATA solid state disks, are integrated on an SoC (System on Chip), and comprise an SATA physical layer unit, an SATA control unit, a crystal oscillator clock unit, a clock gating unit, a phase-locked loop unit, a power consumption management unit and a configuration register unit. The SATA physical layer and the SATA control unit are integrated as independent power supply domains, when a DEVSLP signal is effective, the power supply is cut off, and meanwhile, a phase-locked loop, a crystal oscillator clock and other clock units and a CPU and the like are matched to cut off a power consumption source, so that the SoC chip enters a lowest power consumption state. The entering and exiting processes of the DEVSLP low-power-consumption mode are achieved through cooperative operation of software and hardware, and data loss and command exception are avoided.

The application discloses an LDPC decoding method and system with a dynamic clock-off function, and relates to the technical field of communication. The method comprises the following steps: counting the number of current code words to be decoded; counting the actual iteration number in the decoding process, and calculating the average iteration number; determining the number of decoding cores that need to be started with a clock signal according to the number of current code words to be decoded, the average iteration number and system performance constraints; and dynamically controlling the on-off of the clock signal of the decoding core based on the number of decoding cores that need to be started with the clock signal. The application can dynamically perceive the load and channel quality, accurately match the required decoding resources, and maximally reduce the power consumption of idle resources on the premise of guaranteeing the system performance constraints, and is suitable for high-bandwidth and low-power communication scenes such as 50G PON.

Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.

This disclosure relates to a hardware unit with clock gating for performing matrix multiplication. The disclosure provides hardware units and methods for performing matrix multiplication via a multi-stage pipeline, wherein memory elements associated with one or more stages of the pipeline are clock-gated based on data elements and / or portions thereof known to have zero values ​​or which can be considered to have zero values. In some cases, memory elements may be clock-gated based on each data element, based on whether the data element has a zero value or can be considered to have a zero value. In other cases, memory elements may be clock-gated based on a subset of elements, based on the bit width of the data element. For example, if the bit width of a data element is less than the maximum bit width of the data element, a subset of bits associated with that data element may be considered to have zero values ​​and a subset of memory elements associated with that data element may not be clock-controlled.

The invention provides a virtualized verification environment, a verification method, computer equipment and a storage medium. The verification environment comprises a clock controller, a clock gating unit, an agent module and a Q-Channel model, wherein the model is used for executing the following functions: outputting a state signal to the clock controller; receiving a clock signal output by the clock gating unit, and receiving a request signal output by the clock controller; and completing handshake with the clock controller, and determining whether to execute a request of the request signal according to the state signal, so as to verify the clock signal in the model after the model completes handshake with the clock controller. Wherein the request signal is automatically initiated by the clock controller under the condition of receiving the enable signal and the state signal; the request signal comprises a request for entering a low-power-consumption state or a request for exiting the low-power-consumption state. According to the method, automatic handshake can be realized, the output logic of the handshake signal does not need to be considered at the excitation end, the code quantity is reduced, and the coverage rate is improved.

This invention provides a method and apparatus for power consumption control of a satellite communication SoC chip. The method includes: real-time monitoring of the comprehensive operating parameters of each functional module, calculating power consumption requirements based on satellite orbital characteristics, generating power consumption control commands, performing intelligent clock gating and frequency adjustment operations on the functional modules, and ultimately achieving precise power consumption distribution control. This method can achieve real-time optimized power consumption management based on the dynamic changes of satellite communication services and the periodic characteristics of the orbit, effectively extending the satellite's on-orbit operational life and reducing the overall power consumption level.

This application discloses a high-speed data acquisition and processing method and system for PLC based on FPGA. First, it constructs a detailed real-time heat map and load vector by real-time sensing of multi-point temperature, data input rate, and task queue status on the FPGA chip. Based on this real-time information, it accurately predicts future power consumption and potential hotspot areas to optimize the modeling of internal thermal coupling effects and overcome the shortcomings of traditional models that underestimate peak power consumption. Finally, based on the prediction results, it intelligently generates task execution plans and refined clock gating masks, achieving proactive and adaptive management of FPGA resources. This approach significantly improves the operational stability and reliability of FPGA in high-speed data acquisition and processing scenarios, thus laying a solid foundation for precise industrial control and intelligent decision-making.

The invention relates to a power consumption adjusting method for generating test excitation by an automatic test pattern. The method comprises the following steps: providing a test register module; analyzing the distribution condition of clock gating units ICG in the integrated circuit; and dynamically controlling an enabling signal of the ICG through the test register module based on an analysis result of the ICG distribution condition, so as to realize power consumption adjustment of ATPG test excitation generated by an automatic test pattern. By dynamically controlling the enable signal of the clock gating unit, the power consumption adjustment method for ATPG test excitation is realized, and the problems that the yield is reduced due to over-high test power consumption, the traditional threshold adjustment effect is poor and the like are solved.

A pixel array. The pixel array includes a plurality of light emitting signal lines, a plurality of pixel circuits, and a plurality of clock gating circuits. Each of the pixel circuits includes a first color sub-pixel circuit, a second color sub-pixel circuit, and a third color sub-pixel circuit, wherein the second color sub-pixel circuit and the third color sub-pixel circuit of the pixel circuit are coupled to one of the light emitting signal lines, respectively. The clock gating circuits are coupled between one of the first color sub-pixel circuits of the pixel circuits and one of the light emitting signal lines, respectively, to provide a gated light emitting signal based on a corresponding light emitting signal and a received light emitting clock, wherein each of the first color sub-pixel circuits is lit based on the received gated light emitting signal.

The present invention relates to the technical field of integrated circuits. Disclosed are a clock gating circuit, a clock signal control method, a chip, and an electronic device. By newly adding a feedback circuit constructed on the basis of a first back-pressure signal generation module and a first OR gate unit to a conventional clock gating circuit, when a second register group needs to work, a second enable signal corresponding to a second gating unit is generated to control the second gating unit to be turned on; and on the basis of the second enable signal, the feedback circuit controls a first gating unit to be turned on, thereby controlling the second register group to enter a working state. Hence, in the present invention, simply by generating the second enable signal, the first gating unit and the second gating unit can be simultaneously controlled to be turned on, and there is no need to simultaneously generate a first enable signal and the second enable signal to respectively control the first gating unit and the second gating unit to be turned on, thereby avoiding the process of determining, on the basis of the second gating unit, which additional gating units need to be turned on, and thus effectively improving the working efficiency of the clock gating circuit.

The present disclosure relates to an interfacing method for RTL simulation of an integrated circuit and a system performing the same. The method comprises: obtaining a clock gating time during which a clock supplied to the integrated circuit is gated; obtaining a data holding time during which the clock is not gated but input data do not switch; and providing a metric corresponding to a ratio, within a unit time, occupied by the clock gating time and the data holding time.

Various embodiments provide for cloning a clock gate based on input / output switching activity of clocked circuit elements gated by the clock gate, where the cloning can be performed as part of a clock tree generation or optimization process performed by an electronic design automation (EDA) software.

Provided in the present application are a PCIe clock gating circuit and a PCIe clock control method. The circuit comprises: a link width control circuit, a link rate control circuit and a link state control circuit, wherein the link width control circuit is used for outputting, when a current link width is less than a maximum width, a control signal for turning off a clock of a module related to a non-current link width; the link rate control circuit is used for outputting a control signal for turning off a clock of a module related to a non-current rate; the link state control circuit is used for outputting, when a current link state is an abnormal operation state, a control signal for turning off a clock of a module related to the abnormal operation state, the module related to the abnormal operation state comprising related modules corresponding to link states other than the current link state; and the link state control circuit is also used for outputting, when being in a normal operation state, a control signal for turning off clocks of a training code streaming sending module, a training code stream receiving module and a module related to link training.

The invention provides a clock current-limiting management method based on double-register configuration, which comprises the following implementation steps of: defining a clock as periodic pulses, and circularly numbering according to '0, 1,..., N-1'; a [N-1: 0] bit current limiting parameter register is configured, each Bit corresponds to a numbered pulse, and a'pass / cut-off 'rule is stored; configuring a starting register to realize closing of a current limiting mechanism and effective starting of new parameters; a clock gating sequence is generated through output of the two registers, on-off of clock pulses is controlled, and therefore periodic and non-periodic regulation and control are achieved. The clock pulse is dynamically managed through hardware, the power consumption and the data rate can be accurately adjusted, the regulation and control fineness is high, other modules are not influenced, the occupied resources in a large-scale ASIC are few, operation is easy and convenient, and the application prospect is wide.

Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.

This application discloses a clock management device, method, chip, electronic device, and storage medium, belonging to the field of chip technology. In this device, while issuing an access command, the memory controller also outputs a clock management signal to the clock gating unit connected to the relay module of the corresponding data bus, indicating that the clock gating unit outputs a clock signal to the relay module. Furthermore, after a preset number of clock cycles, the memory controller sends a clock management signal to the clock gating unit, indicating that the clock gating unit stops outputting a clock signal to the relay module, thus stopping the clock gating unit from outputting a clock signal to the relay module. This achieves timely activation of the relay module's clock signal when the data bus is occupied and timely deactivation of the relay module's clock signal after memory access is completed, realizing fine-grained and dynamic management of the clock signals of the relay modules on each data bus, and significantly reducing the overall power consumption introduced by the clock signal.

Circuit, showing: a latch (120) configured to generate a gating control signal (Q) in response to a latch enable signal (EB) and an input clock signal (CP), wherein the latch (120) has a pair of logic gates (210, 220) each configured to perform a complex logic function at multiple levels; and a logic circuit (130) configured to receive the gating control signal (Q) and the input clock signal (CP) and to generate an output clock signal (CPQ) in response to the gating control signal (Q) and the input clock signal (CP), where the logic gates (210, 220) are: at least one header switch (M1) and at least one footer switch (M3), each configured to be controlled by the input clock signal (CP); a first (M5), a second (M13) and a third switch (M7) which are coupled in series with at least one header switch (M1); a fourth (M6), a fifth (M14) and a sixth switch (M8) coupled in series with at least one header switch (M1); and a pair of cross-coupled inverters (310, 320) coupled to at least one footer switch (M3), wherein the second (M13) and fifth switches (M14) are configured to be controlled by outputs of the inverters (310, 320); wherein the first (M5) and third switches (M7) are configured to be controlled by the latch release signal (EB), and the fourth (M6) and sixth switches (M8) are configured to be controlled by a logical complement of the latch release signal (EB).

The invention relates to the technical field of integrated circuits and provides a built-in self-test circuit and method for a chip. The circuit comprises a control bidirectional selector which is used for constructing a control path relation among a plurality of objects to be tested; the data bidirectional selector is used for constructing a data path relationship; the management component is used for executing independent clock gating operation on respective input clock trees of the plurality of to-be-tested objects and executing independent system reset operation on respective input reset signals of the plurality of to-be-tested objects; and the test component is used for coordinating the components so as to set a control path relationship and a data path relationship among one or more objects to be tested according to a serial relationship, a parallel relationship or a serial-parallel mixed application relationship and test. Therefore, the method is beneficial to adapting to various communication protocols and interface standards, and meets the requirements of chip design and development and chip testing for shortening the chip testing time and quickly responding to changes.