142results about "Dataflow computers" patented technology

A reconfigurable processor chip includes: a plurality of reconfigurable processing elements based on distributed storage, components of the reconfigurable processing elements being logically interconnected. The components include: a reconfigurable computing component configured to calculate data; a data flow controller using a data flow driving mode, the data flow driving mode is configured to control start and end of a computing task and a data transmission task based on data flow information about the computing task and message transferring of upstream and downstream reconfigurable processing elements; a distributed memory configured to implement data storage of a corresponding reconfigurable processing element; and a programmable data routing element configured to implement communication between the plurality of reconfigurable processing elements to control a direction of a data packet, and implement flexible transmission of the data packet.

In some aspects, a program is executed on a coarse-grained reconfigurable (CGR) processor. The CGR determines that the program produces an output that includes a variable length tensor, determines a maximum size of the variable length tensor and sets, based on the maximum size, a maximum of a counter associated with the program. The counter is set to an initial value of zero. The CGR initiates execution of the program, causing the program to receive an input tensor. Based on determining that the program is operating on a first portion of the input tensor, the CGR performs an update to the counter, to create an updated counter, and communicates the updated counter to one or more consumers within the program. After determining that the program has completed operating on the input tensor, a final size of the output is communicated to one or more downstream consumers external to the program.

A method for reducing latency and increasing throughput in a reconfigurable computing system includes receiving a compute graph for execution on a reconfigurable dataflow processor comprising a grid of compute units and grid of memory units interconnected with a switching array. The compute graph includes a node specifying an operation on a tensor. The node may be split into multiple nodes that each specify the operation on a distinctive portion of the tensor to produce a first modified compute graph. The first modified compute graph may be executed. In addition, the multiple nodes may be within a single meta-pipeline stage and may be processed in parallel. Furthermore, the compute graph may further comprise a separate node for gathering the distinctive portions of the tensor into a complete tensor, to produce a second modified compute graph.

Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.

Disclosed herein is a co-designed compiler and CGRA architecture that achieves both high programmability and extreme energy efficiency. The architecture includes a rich set of control-flow operators that support arbitrary control flow and memory access on the CGRA fabric. The architecture is able to realize both energy and area savings over prior art implementations by offloading most control operations into a programmable on-chip network where they can re-use existing network switches.

Push-pull mechanisms for handling dataflow between circuit blocks are disclosed. In certain embodiments, a network of dataflow gaskets includes a source gasket coupled to a first circuit block and a destination gasket coupled to a second circuit block. The source gasket and the destination gasket are connected by a push mechanism that uses write channels to write data from the source gasket to the destination gasket, and a pull mechanism that uses read channels to read data from the source gasket to the destination gasket. The source gasket and the destination gasket can switch between a push mode and a pull mode to ease traffic based on data available to transfer at the source gasket and / or a space available to receive data in the destination gasket. For example, a transfer size register can be used to set a threshold to aid between the mode transitions.

A method for merging buffers and associated operations includes receiving a compute graph for a reconfigurable dataflow computing system and conducting a buffer allocation and merging process responsive to determining that a first operation specified by a first operation node is a memory indexing operation and that the first operation node is a producer for exactly one consuming node that specifies a second operation. The buffer allocation and merging process may include replacing the first operation node and the consuming node with a merged buffer node within the graph responsive to determining that the first operation and the second operation can be merged into a merged indexing operation and that the resource cost of the merged node is less than the sum of the resource costs of separate buffer nodes. A corresponding system and computer readable medium are also disclosed herein.

Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. The present disclosure provides a schedule-aware, dynamically reconfigurable, tree-based partial sum accumulator architecture for HW accelerators, wherein the depth of an adder tree in the HW accelerator is dynamically based on a dataflow schedule generated by a compiler. The adder tree depth is adjusted on a per-layer basis at runtime. Configuration registers, programmed via software, dynamically alter the adder tree depth for partial sum accumulation based on the dataflow schedule. By facilitating a variable depth adder tree during runtime, the compiler can choose a compute optimal dataflow schedule that minimizes the number of compute cycles needed to accumulate partial sums across multiple processing elements (PEs) within a PE array of a HW accelerator. Other embodiments may be described and / or claimed.

Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.

A method in a reconfigurable computing system includes receiving a user program for execution on a reconfigurable dataflow computing system, comprising a grid of compute units and grid of memory units interconnected with a switching array. The user program includes multiple tensor-based algebraic expressions that are converted to an intermediate representation comprising one or more logical operations executable via dataflow through compute units. These one or more logical operations are preceded by or followed by a buffer, each buffer corresponding to one or more memory units. The method includes determining whether splitting a selected buffer yields a reduced cost and then splitting the selected buffer, in response to the determining step, to produce first and second buffers. Dataflow through memory units corresponding to the first and second buffers is controlled by one or more memory units within the grid of memory units. Buffer splitting optimization reduces memory unit consumption.

The invention discloses a data processing method and device, electronic equipment and a storage medium. The data processing method comprises the following steps: acquiring a computational graph; determining at least one core operator based on the computational graph; determining arrangement modes corresponding to the plurality of operators through at least one round of iterative operation; wherein in each round of iterative operation, one or more core operators are selected from at least one core operator to serve as initial operators; determining an arrangement mode corresponding to each initial operator according to the read-write overhead of each initial operator in a plurality of preset arrangement modes; the initial operator is taken as a starting point, forward and backward propagation is carried out according to the dependency relationship in combination with the arrangement mode corresponding to the initial operator, the arrangement mode corresponding to each operator is obtained in sequence, and in the process of obtaining the arrangement mode corresponding to each operator in sequence, the arrangement mode corresponding to the current operator is obtained in combination with the arrangement mode corresponding to the adjacent operator; the adjacent operators are operators which are adjacent to the current operator according to the dependency relationship and have determined arrangement modes.

A method is provided for automatically placing and routing processing elements (PEs), where each PE has limited connectivity to its neighbors. The method may obtain layout primitive (PP) position window information that defines possible positions of a set of PPs within a coarse-grained reconfigurable array (CGRA). The method may obtain hardware constraints with respect to the PE array, the hardware constraints including local connectivity constraints and remote connectivity constraints. The method may receive a computational graph (CG) representing a mathematical expression to be computed by the PE array. The method may determine a location of the PE in the PE array based on the CG, the PP location window information, and hardware constraints.

Techniques and systems disclosed herein may relate to a server processing work requests of a work requester. For example, the work requester may generate a plurality of work requests comprising functions of an application to be executed by a dependency-aware (DA) server, determine processing dependencies associated with the work requests, communicate, to the DA server, the processing dependencies, and enqueue the work requests on a dependent queue and a conditioned dependent queue based on processing dependencies associated with the DA server. The DA server may then select one of the work requests from the dependent queue or the conditioned dependent queue for processing and processing the selected work request.

The embodiment of the invention provides a method for carrying out calculation based on a data flow graph (DFG) and related equipment. The method comprises the steps that a first operator obtains a plurality of data values from a second operator, the data flow diagram comprises the first operator and the second operator, and the data values are stored in a plurality of instruction units corresponding to the second operator in the DFG respectively; the first operator calculates an output result of the first operator according to the plurality of data values in the second operator, and the plurality of data values in the second operator are input of the first operator. By the proposed techniques, cycling or recursion may be performed in the DFG.

A technique is disclosed for operand propagation and accumulation within a processing array of an integrated circuit using overlapping patch regions. The system includes an interconnecting processing patch defined over a rectilinear subset of processing elements, with an origin processing element broadcasting operand data to the remaining elements in a directionally constrained, time-staggered wavefront pattern. A logical processing patch is separately defined over a second rectilinear subset of processing elements. The interconnecting processing patch and the logical processing patch partially overlap to form an interconnecting patch mesh comprising a common set of processing elements. Operand data is propagated from the origin of the interconnecting patch to the common processing elements within the patch mesh, enabling operand handoff or accumulation across patch boundaries. The architecture supports fine-grained, localized data movement and patch-level execution coordination across a mesh of processing elements to optimize compute reuse, operand locality, and execution throughput.

A computer implemented method comprises a server processing work requests of a work requester. The work requester can communicate to the server a processing dependency of one work request on a second work request. The server can associate the dependency with the work requests and / or a queue of work requests. The dependency include a condition to be met in association with processing the work requests, and the condition can include an action for the server to take in association with processing a work request. A computing system can comprise a work requester, a server, and a set of dependency-aware queues for processing a set of work requests. A queue and / or work requests on the queues can be associated with a processing dependency and the server can process work requests enqueued to the queues in an order based on the dependencies. A work requester / server interface can comprise a dependency framework.

An apparatus comprising: at least one processing element configured to process a data flow in at least one direction of a plurality of directions; a configuration register comprising at least one setting that determines the processing of the data flow with the at least one processing element; and a shift register configured to select data of the at least one processing element from the at least one direction, and to provide at least one shifted data sample to a plurality of slices configured to perform at least one arithmetic operation with the data flow; wherein at least one slice of the plurality of slices is configured with the at least one setting of the configuration register.

A method for a reconfigurable computing system includes receiving a compute graph for execution on multiple RDPs interconnected with a ring network having R interconnected RDPs. A compute graph with a node specifying a reduction operation for a first and second tensor is detected. Executing the compute graph on the multiple RDPs.

The invention belongs to the technical field of information technology, and discloses a special signal generating device based on software defined radio and a GPU server, comprising: a graphic processing unit used for generating high-speed orthogonal data streams corresponding to various communication systems and modulation modes, the high-speed orthogonal data streams being transmitted to an intermediate frequency signal unit through an optical fiber; the intermediate frequency signal unit is used for receiving the high-speed orthogonal data stream, completing signal modulation and outputting an intermediate frequency signal; the software-defined radio platform is used for carrying out secondary development to realize signal generation and reception, and the secondary development builds a heterogeneous system integrated by a central processing unit and a graphic processing unit based on general radio software; the central processing unit is used for task scheduling and memory configuration; the invention aims to solve the problem that a signal generating device in the prior art cannot realize high-efficiency collaboration of a central processing unit and a graphic processing unit in high-speed data stream processing.

A method for merging buffers and associated operations includes receiving a compute graph for a reconfigurable dataflow computing system and conducting a buffer allocation and merging process responsive to determining that a first operation specified by a first operation node is a memory indexing operation and that the first operation node is a producer for exactly one consuming node that specifies a second operation. The buffer allocation and merging process may include replacing the first operation node and the consuming node with a merged buffer node within the graph responsive to determining that the first operation and the second operation can be merged into a merged indexing operation and that the resource cost of the merged node is less than the sum of the resource costs of separate buffer nodes. A corresponding system and computer readable medium are also disclosed herein.

The embodiment of the invention provides a data processing method and device, a storage medium and a program product. In the method, a segmentation calculation device determines the segmentation number of at least one layer of circulation used for executing an operator and the number of needed cache blocks, and the operator is a unit for executing an instruction. Further, the segmentation calculation device determines, in a pipeline including an operator, an adjustment point for adjusting the length of the pipeline. Further, the segmentation calculation device adjusts at least one of the number of segmentation portions and the number of cache blocks based on the adjustment point. Therefore, according to the embodiment of the invention, the calculation efficiency can be improved, and cache resources are saved.

To provide a conversion program, a conversion method and a conversion device for improving processing capability.SOLUTION: Acquiring a mapping result including a predetermined DFG and information on assignment of operations to respective computing units and wiring between the computing units determined so as to correspond to the predetermined DFG for a CGRA having a plurality of computing units, and extracting a portion corresponding to a predetermined DFG pattern from the predetermined DFG; A computer is made to execute processing for determining a conversion candidate DFG from among DFGs corresponding to a pattern of an extraction place on the basis of a position to which the extraction place in a mapping result is assigned and the number of transmission paths of data to be used between arithmetic units, and generating a converted DFG by converting a predetermined DFG on the basis of the conversion candidate DFG.SELECTED DRAWING: Figure 6

A method for processing agent data received from one or more agents traversing an environment for use in a simultaneous localisation and mapping process. The method includes determining a pipeline including a number of nodes, and a node configuration for some of the nodes. Each node relates to a respective data processing task implemented using a respective software module, the nodes being interconnected so as to define a node sequence representing a sequence of data processing tasks. The node and pipeline are then used to load and configure software modules, which are then executed to provide output data from at least one software module as processed agent data, wherein the processed agent data is used in a simultaneous localisation and mapping process.

A flexible processor includes (i) numerous configurable processors interconnected by modular interconnection fabric circuits that are configurable to partition the configurable processors into one or more groups, for parallel execution, and to interconnect the configurable processors in any order for pipelined operations, Each configurable processor may include (i) a control circuit; (ii) numerous configurable arithmetic logic circuits; and (iii) configurable interconnection fabric circuits for interconnecting the configurable arithmetic logic circuits.

Embodiments of the present disclosure provide an artificial intelligence (AI) chip and an AI chip-based data processing method. The AI chip includes: a data flow network for processing, on the basis of an AI algorithm, data to be processed. The data flow network includes: at least one calculation module, each configured to calculate, on the basis of one of at least one operation node corresponding to the AI algorithm, the data to be processed, and output a calculation result; and a next transfer module corresponding to each calculation module, connected to each calculation module, and configured to receive the calculation result output by each calculation module and process the calculation result, the data to be processed flowing in the data flow network according to a preset data flow direction.

Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. The present disclosure provides a schedule-aware, dynamically reconfigurable, tree-based partial sum accumulator architecture for HW accelerators, wherein the depth of an adder tree in the HW accelerator is dynamically based on a dataflow schedule generated by a compiler. The adder tree depth is adjusted on a per-layer basis at runtime. Configuration registers, programmed via software, dynamically alter the adder tree depth for partial sum accumulation based on the dataflow schedule. By facilitating a variable depth adder tree during runtime, the compiler can choose a compute optimal dataflow schedule that minimizes the number of compute cycles needed to accumulate partial sums across multiple processing elements (PEs) within a PE array of a HW accelerator. Other embodiments may be described and / or claimed.

A method for a reconfigurable computing system includes receiving a compute graph for execution on multiple RDPs interconnected with a ring network having R interconnected RDPs. A compute graph with a node specifying a reduction operation for a first and second tensor is detected. The detected compute graph node is partitioned into a compute subgraph corresponding to an RDP of the R interconnected RDPs. A first node is inserted into the compute subgraph that specifies a partial reduction operation for producing a partial reduction result corresponding to a shard of the first tensor and a shard of the second tensor. A second node is inserted for communicating the partial reduction result to an adjacent RDP. A third node is inserted that specifies a reduction operation for producing a total reduction result. A fourth node is inserted for communicating the total reduction result to at least one other RDP.

The invention relates to a computing device (1) comprising a processor unit (2) having a plurality of computing cores (2.1) working in cooperation and a plurality of storage elements (2.2) assigned to the computing cores (2.1), and having at least one input interface (3) for receiving information to be processed by the computing cores (2.1) and at least one output interface (4) for outputting information processed by the computing cores (2.1). The computing device according to the invention is characterized in that the storage elements (2.2) are formed by two-port RAM, each processor core (2.1) has exactly two inputs (E) for receiving information and exactly one output (A) for outputting information, each input (E) and each output (A) being each formed by one storage element (2.2), the physical distances (d) starting from the respective processor core (2.1) to the storage elements (2.2) connected to the processor core (2.1) are equidistant.

Push-pull mechanisms for handling dataflow between circuit blocks are disclosed. In certain embodiments, a network of dataflow gaskets includes a source gasket coupled to a first circuit block and a destination gasket coupled to a second circuit block. The source gasket and the destination gasket are connected by a push mechanism that uses write channels to write data from the source gasket to the destination gasket, and a pull mechanism that uses read channels to read data from the source gasket to the destination gasket. The source gasket and the destination gasket can switch between a push mode and a pull mode to ease traffic based on data available to transfer at the source gasket and / or a space available to receive data in the destination gasket. For example, a transfer size register can be used to set a threshold to aid between the mode transitions.