21results about "Associative processors" patented technology

Embodiments of the present disclosure provide a processor, an instruction processing method, and an electronic device including the processor. The processor includes a plurality of processor cores and an accelerator module, wherein each of the plurality of processor cores is configured to execute a first type of instruction; the accelerator module includes at least one accelerator engine configured to execute a second type of instruction different from the first type of instruction; the accelerator module is coupled with and shared by the plurality of processor cores, and each of the plurality of processor cores dispatches an object instruction belonging to the second type of instruction in an instruction stream processed by itself to the accelerator module for execution and receives an execution result message of the object instruction from the accelerator module. The processor can have higher accelerator module usage efficiency.

The invention provides a cache replacement method and device, equipment and a storage medium, a cache is formed by connecting n paths of groups, and n is 4 or 8; if n is 4, dividing every two paths into one group to obtain a first group and a second group; 4-bit access information is recorded; if n is 8, every two paths are divided into one group, and a third group, a fourth group, a fifth group and a sixth group are obtained; every two groups are divided into a large group, and a first large group and a second large group are obtained; 10 bit access information is recorded; the method comprises the following steps: acquiring cached access information; determining a cache line which is not accessed for the longest time according to the access information; and replacing the cache line which is not accessed for the longest time. According to the method provided by the invention, the cache line can be quickly replaced through the access information.

The invention provides a dual-binary turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; determining a processing module according to the length of the processing data; wherein the processing module uniquely corresponds to one storage unit; and performing multi-round parallel processing on the processing data based on the DVB-RCS2 standard through the determined processing module. According to the method, a processing module is determined according to the length of processing data; wherein the processing module uniquely corresponds to one storage unit; through the determined processing module, multi-round parallel processing is performed on the processing data based on the DVB-RCS2 standard, parallel processing of the processing data is realized, the processing time is reduced, and the processing efficiency is improved.

The present disclosure provides a multi-core parallel simulation method and device, computer equipment, storage medium and program product, relates to the chip design and simulation technical field, and the implementation scheme is: in the window interval, the simulation instance independently executes the first event associated with the local, the outbound message generated in the process of executing the first event is locally buffered to be batched to the message queue when the predetermined sending condition is met; the inbound message is received from the message queue according to the predetermined receiving rule; when the boundary of the window interval is reached, the simulation instance executes the second event associated with the inbound message; and the temporary storage state is changed to the visible state for the remaining simulation instances via the synchronization manager; and the simulation time of each simulation instance is uniformly advanced to the next window interval after the window interval, which can significantly reduce the synchronization frequency and cross-core communication overhead, improve the simulation throughput and scalability, and help improve the chip design efficiency.

The invention provides an airborne high-performance computing platform, which comprises a general data processing module used for meeting functional requirements of various application software on real-time reading of processed data through network dynamic configuration under control management of a system; the main control interface module is used for completing system resource scheduling and management and system key instruction storage functions and realizing interface scheduling and management functions with each subsystem; the power supply module is used for supplying power to each module in the platform; the map card module is used for realizing storage of graphic processing resource data; wherein various data sources are accessed to the general data processing module through the external interface, data processing of different data sources is completed through the general data processing module to obtain processed data, and the processed data is transmitted to the main control interface module through the internal SRIO switching network and then is transmitted to the airborne avionics system to complete service processing. According to the method, multiplexing of hardware resources by different functions is realized through system reconstruction and automatic loading, and the development requirements of future high-performance computing are met.

A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application.

The invention provides an instruction data packet generation method and apparatus, and an electronic device. The method comprises the steps of obtaining a processing instruction; determining a source operand for processing the instruction according to a pre-configured instruction configuration file; determining a definition of a source operand and a register corresponding to the source operand according to a pre-configured source operand configuration file; determining the definition of the register according to a pre-configured register configuration file; and according to the definition of the source operand and the definition of the register, binding the processing instruction, the source operand and the register, and generating a data packet for calling the processing instruction. According to the instruction data packet generation method provided by the invention, during modification each time, instruction modification can be realized through the configured instruction configuration file, the configured source operand configuration file and the configured register configuration file, so that instruction configuration modification is completed without changing scripts, the period of instruction configuration modification each time is shortened, and the modification efficiency is improved. And development cycle lag is avoided.

The embodiment of the invention provides multi-chip equipment, a data transmission method, an electronic device and a medium. The multi-chip equipment comprises N chips, N is a positive integer larger than 1, each chip in the N chips comprises a processor and a memory, the memory of the first chip in the N chips is configured to collect operation information about a first thread in the first chip and determine whether an inter-chip data transmission condition is met or not, and the processor is configured to send the operation information about the first thread in the first chip to the processor. And sending synchronous data to a second chip in the N chips under the condition of determining that the data transmission condition among the chips is satisfied, and the second chip is configured to receive the synchronization data, generate synchronization feedback data associated with the synchronization data based on operation information of a second thread in the second chip, and send the synchronization feedback data to the first chip.

An electronic chip, a chip assembly, a computing device, and a method are described. The electronic chip comprises a plurality of processing cores and at least one hardware interface coupled to at least one of the one or more processing cores. At least one processing core implements a game engine and / or a simulation engine and at least one or more processing cores implements an artificial intelligence engine, whereby implementations are on-chip implementations in hardware by dedicated electronic circuitry. The at least one or more game and / or simulation engines performs tasks on sensory, generating data sets that are processed through machine learning algorithms by the hardwired artificial intelligence engine. The data sets processed by the hardwired artificial intelligence engine include at least contextual data and target data, wherein combining both data and processing by dedicated hardware results in enhanced machine learning processing.

The invention provides a multi-core parallel simulation method and device, computer equipment, a storage medium and a program product, and relates to the technical field of chip design and emulation.According to the implementation scheme, in a window interval, a simulation instance independently executes a first event associated with the local, outbound messages generated during execution of the first event are buffered locally to be sent to a message queue in batches when a predetermined sending condition is satisfied; receiving the inbound message from the message queue according to a preset receiving rule; upon reaching a boundary of the window interval, the emulation instance performs a second event associated with the inbound message; and changing, via a synchronization manager, the temporary storage state into a visible state for the remaining simulation instances; and the simulation time of each simulation instance is uniformly advanced to the next window interval after the window interval, so that the synchronization frequency and the cross-core communication overhead can be remarkably reduced, the simulation throughput and expansibility are improved, and the chip design efficiency is favorably improved.

The invention provides an instruction execution method and apparatus, and an electronic device. The method comprises the steps of obtaining an input command; determining a first instruction corresponding to the input command; a data packet of the first instruction is obtained, and the data packet is obtained based on a pre-configured instruction configuration file, a pre-configured source operand configuration file and a pre-configured register configuration file; determining the slot parallel execution number of the vector processor; and according to the slot parallel execution quantity, processing the data packet in each beat through a functional unit of the vector processor. According to the instruction execution method provided by the invention, during modification each time, instruction execution can be realized through the configured instruction configuration file, the configured source operand configuration file and the configured register configuration file, so that instruction execution can be completed without changing scripts, the period of instruction configuration modification each time is shortened, and development period lag is avoided.

The present application discloses a chiplet-based microprocessor system, an architecture method, a chip, and an electronic device. The microprocessor system is based on a chiplet architecture, and comprises: a plurality of computing dies having a computing function; a data die coupled to the plurality of computing dies, wherein the data die is provided with an external interface unit, a memory read-write unit, and a plurality of co-processing units for data acceleration processing; and a plurality of memory units arranged close to the data die. According to the microprocessor system provided by the present application, the co-processing units are arranged on the data die, thereby effectively utilizing the space on the data die, achieving computation offloading, and achieving high performance of the microprocessor system.

To provide a device and a method for real-time calibration of a cubit in a quantum processor.SOLUTION: A device include: a quantum processor including a plurality of cubits each having a specific state; a quantum controller for generating a sequence of an electromagnetic (EM) pulse and operating the state of the plurality of cubits on the basis of a set of control parameters; a cubit measurement unit for measuring one or more sensors related to corresponding one or more cubits among the plurality of cubits and generating corresponding one or more values measured; and a machine learning engine for evaluating the one or more measured values according to a machine learning process, and for generating updated control parameters. The quantum controller uses the updated control parameters to generate a subsequent sequence of the EM pulse to operate the state of the plurality of cubits.SELECTED DRAWING: Figure 2

Provided in the embodiments of the present disclosure are a processor, an instruction processing method, and an electronic device comprising the processor. The processor comprises a plurality of processor cores and an accelerator module, each of the plurality of processor cores being configured to execute first-type instructions; the accelerator module comprises at least one accelerator engine that is configured to execute second-type instructions different from the first-type instructions; the accelerator module is coupled to the plurality of processor cores and shared by the plurality of processor cores; each of the plurality of processor cores dispatches, from an instruction stream processed thereby, an object instruction belonging to the second-type instructions to the accelerator module for execution, and receives from the accelerator module an execution result message for the object instruction.

The application discloses a processor, a data processing method and an electronic device, and the application achieves the purpose of processing data by a processor other than a CPU by acquiring data and processing the acquired data by a first processing unit, a second processing unit or a third processing unit; and the first processing unit, the second processing unit and the third processing unit are respectively used for processing different data, so that different types of data can be processed simultaneously in the processor, the data processing speed of the processor is improved, the problems of large load and high power consumption caused by processing all data in the same processor or processing unit are further avoided, the power consumption demand of the CPU is relieved, and the operation efficiency of the system is improved.

This application is directed to in-memory associative processing for vectors. An apparatus can perform a compute operation on a first contiguous bit set of a first vector and a first contiguous bit set of a second vector. The first contiguous bit set can be stored in a first plane of a memory die, and the compute operation can be based on a truth table for the compute operation. The apparatus can perform a second compute operation on a second contiguous bit set of the first vector and a second contiguous bit set of the second vector. The second contiguous bit set can be stored in a second plane of the memory die and the compute operation is based on the truth table for the compute operation.

A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application. The system further comprises an archive of configuration files and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises first and second compilers that generate for the application, based on the respective first and second constraints, first and second configuration files that are stored in the archive of configuration files and adapted to be executed data-parallel compatible on respective first and second reconfigurable processors.

The invention provides a floating point continuous accumulation method and an adder, and the method comprises the steps: carrying out the addition calculation of the mantissa of a first source operand and the mantissa of a second source operand in a period, obtaining an accumulation result, and obtaining a next second source operand; wherein the source operand is in a floating point format; in the next period, order matching between the accumulation result and the next second source operand is carried out according to the relation between the index of the accumulation result and the index of the next second source operand; in each subsequent period, carrying out addition calculation on the mantissa of the accumulated result after the order and the mantissa of the next second source operand to obtain the accumulated result, and meanwhile, obtaining the next second source operand; and performing order matching between the accumulation result and the next second source operand according to the relationship between the index of the accumulation result and the index of the next second source operand. According to the method, effective data calculation can be performed in each period under the high dominant frequency, so that the operation efficiency is improved, and the power consumption is reduced.

The invention discloses a microprocessor system based on core particles, an architecture method, a chip and electronic equipment. The microprocessor system is based on a core particle architecture, and the microprocessor system comprises a plurality of computing chips with computing functions; the data wafer is coupled with the plurality of computing wafers, and is provided with an external interface unit, a memory read-write unit and a plurality of co-processing units for data acceleration processing; and a plurality of memory units arranged close to the data wafer. According to the microprocessor system provided by the invention, the co-processing unit is arranged on the data wafer, so that the space on the data wafer is effectively utilized, the computing power unloading is realized, and the high performance of the microprocessor system is realized.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

An electronic chip, a chip assembly, a computing device, and a method are described. The electronic chip comprises a plurality of processing cores and at least one hardware interface coupled to at least one of the one or more processing cores. At least one processing core implements a game engine and / or a simulation engine and at least one or more processing cores implements an artificial intelligence engine, whereby implementations are on-chip implementations in hardware by dedicated electronic circuitry. The at least one or more game and / or simulation engines performs tasks on sensory, generating data sets that are processed through machine learning algorithms by the hardwired artificial intelligence engine. The data sets processed by the hardwired artificial intelligence engine include at least contextual data and target data, wherein combining both data and processing by dedicated hardware results in enhanced machine learning processing.