38results about "Associative processors" patented technology

An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required control signals. The instruction decoder circuitry is responsive to a single instruction (referred to herein as a repeating multiply-accumulate instruction) having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations required, to generate control signals to control the SIMD processing circuitry. In response to those control signals, the SIMD data processing circuitry performs the plurality of iterations of a multiply-accumulate process, each iteration involving performance of N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements. For each iteration, the SIMD data processing circuitry determines N input data elements from said first vector and a single coefficient data element from the second vector to be multiplied with each of the N input data elements. The N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process are then used to produce N multiply-accumulate results. This mechanism provides a particularly energy efficient mechanism for performing SIMD multiply-accumulate operations, as for example are required for FIR filter processes.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Systems, methods, and apparatuses relating to debugging a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. At least a first of the plurality of processing elements is to enter a halted state in response to being represented as a first of the plurality of dataflow operators.

Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.

In the parallel control method and electronic equipment provided by the present invention, by using memory, at least two ring interconnected processors, and at least one bridge chip, the at least two processors include at least one first-level processor connected to the bridge chip, The memory includes a number of storage partitions, each of which is connected to a processor, and each storage partition runs an operating system, and the first-level processor receives the sending and executing instructions or forwarding instructions determined by its corresponding first operating system according to the data packet , and process the data packet according to the execution instruction, and store the processing result in the storage partition connected to the first-level processor, and forward the data packet to the target processor corresponding to the target operating system according to the forwarding instruction, and the target processor processes the data packet and will process the The results are stored in the corresponding storage partitions, so that the hardware resources of each operating system on the single board can be physically isolated to improve data security.

The invention discloses a hot switching method for a dual-mode redundant microprocessor, and aims to provide better processor state monitoring and fault-tolerance effects and endow a processor with a hot switching capability so as to improve the stability and adaptability of an embedded microprocessor in a radiation environment. The adopted technical scheme is that a judgment logic of a dual-mode redundant processor is established; an instruction state machine, address access, data flow processing and a processor state are monitored separately; the processor state is evaluated; during resetting, a second processor is in an idle state, a first processor executes the instruction content in a memory in sequence until the first processor has an error, at the moment, processor switching is performed, and a bus switching logic cuts off a data path of the first processor, transfers data to the second processor and sends a switching interruption request to the second processor; and the second processor uses data in a shared data memory to restore an execution state of the first processor and continues to execute an instruction, thereby realizing the hot switching.

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and / or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

The invention discloses a parallel accelerating method and system in heterogeneous computation. The method comprises the following steps: determining a topological structure of data transmission between GPUs (Graphics Processing Unit) in advance according to the quantity of the GPUs; acquiring a current task by each GPU in the topological structure and computing data in the current task, so as to obtain a calculating result corresponding to the current task; sharing the calculating result which is obtained by each GPU and corresponds to the current task to the other GPUs in the topological structure; after obtaining the calculating results of the other GPUs in the topological structure by each GPU, starting to execute the next task. By adopting the parallel accelerating method and system in the heterogeneous computation, the parallel computation capability of the GPUs can be improved and the bandwidth requirements on nodes of each GPU are reduced.

The invention provides a motherboard and a server, the motherboard includes: a board body, a preset number of Purley platform CPUs and at least one memory; a preset number of Purley platform CPUs and at least one memory are respectively installed on the board body ; The preset number of Purley platform CPUs are connected in turn; each memory is connected to one of the preset number of Purley platform CPUs; each memory is used for receiving external input waiting When burning data, send the data to be burned to the connected Purley platform CPU; each Purley platform CPU is used to burn the data to be burned when receiving the data to be burned sent by the connected memory , to have functions corresponding to the data to be programmed. Therefore, the solution provided by the present invention can improve the function expandability of the motherboard.

A method of booting a multisystem including a first core and a second core, the method includes: executing a boot loader of the first core; setting a network interface of the first core to be in an enable state; detecting the second core that is connected to the network interface of the first core; mapping a first memory of the first core to a second memory of the second core; loading a booting image of the first core and a booting image of the second core on the first memory; and transferring the booting image of the second core loaded on the first memory to the second core via a network.