3results about "Associative processors" patented technology

The present disclosure provides a multi-core parallel simulation method and device, computer equipment, storage medium and program product, relates to the chip design and simulation technical field, and the implementation scheme is: in the window interval, the simulation instance independently executes the first event associated with the local, the outbound message generated in the process of executing the first event is locally buffered to be batched to the message queue when the predetermined sending condition is met; the inbound message is received from the message queue according to the predetermined receiving rule; when the boundary of the window interval is reached, the simulation instance executes the second event associated with the inbound message; and the temporary storage state is changed to the visible state for the remaining simulation instances via the synchronization manager; and the simulation time of each simulation instance is uniformly advanced to the next window interval after the window interval, which can significantly reduce the synchronization frequency and cross-core communication overhead, improve the simulation throughput and scalability, and help improve the chip design efficiency.

A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application.

An electronic chip, a chip assembly, a computing device, and a method are described. The electronic chip comprises a plurality of processing cores and at least one hardware interface coupled to at least one of the one or more processing cores. At least one processing core implements a game engine and / or a simulation engine and at least one or more processing cores implements an artificial intelligence engine, whereby implementations are on-chip implementations in hardware by dedicated electronic circuitry. The at least one or more game and / or simulation engines performs tasks on sensory, generating data sets that are processed through machine learning algorithms by the hardwired artificial intelligence engine. The data sets processed by the hardwired artificial intelligence engine include at least contextual data and target data, wherein combining both data and processing by dedicated hardware results in enhanced machine learning processing.