10results about "Associative processors" patented technology

The invention provides a dual-binary turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; determining a processing module according to the length of the processing data; wherein the processing module uniquely corresponds to one storage unit; and performing multi-round parallel processing on the processing data based on the DVB-RCS2 standard through the determined processing module. According to the method, a processing module is determined according to the length of processing data; wherein the processing module uniquely corresponds to one storage unit; through the determined processing module, multi-round parallel processing is performed on the processing data based on the DVB-RCS2 standard, parallel processing of the processing data is realized, the processing time is reduced, and the processing efficiency is improved.

The present disclosure provides a multi-core parallel simulation method and device, computer equipment, storage medium and program product, relates to the chip design and simulation technical field, and the implementation scheme is: in the window interval, the simulation instance independently executes the first event associated with the local, the outbound message generated in the process of executing the first event is locally buffered to be batched to the message queue when the predetermined sending condition is met; the inbound message is received from the message queue according to the predetermined receiving rule; when the boundary of the window interval is reached, the simulation instance executes the second event associated with the inbound message; and the temporary storage state is changed to the visible state for the remaining simulation instances via the synchronization manager; and the simulation time of each simulation instance is uniformly advanced to the next window interval after the window interval, which can significantly reduce the synchronization frequency and cross-core communication overhead, improve the simulation throughput and scalability, and help improve the chip design efficiency.

The invention provides an airborne high-performance computing platform, which comprises a general data processing module used for meeting functional requirements of various application software on real-time reading of processed data through network dynamic configuration under control management of a system; the main control interface module is used for completing system resource scheduling and management and system key instruction storage functions and realizing interface scheduling and management functions with each subsystem; the power supply module is used for supplying power to each module in the platform; the map card module is used for realizing storage of graphic processing resource data; wherein various data sources are accessed to the general data processing module through the external interface, data processing of different data sources is completed through the general data processing module to obtain processed data, and the processed data is transmitted to the main control interface module through the internal SRIO switching network and then is transmitted to the airborne avionics system to complete service processing. According to the method, multiplexing of hardware resources by different functions is realized through system reconstruction and automatic loading, and the development requirements of future high-performance computing are met.

A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application.

The invention provides an instruction data packet generation method and apparatus, and an electronic device. The method comprises the steps of obtaining a processing instruction; determining a source operand for processing the instruction according to a pre-configured instruction configuration file; determining a definition of a source operand and a register corresponding to the source operand according to a pre-configured source operand configuration file; determining the definition of the register according to a pre-configured register configuration file; and according to the definition of the source operand and the definition of the register, binding the processing instruction, the source operand and the register, and generating a data packet for calling the processing instruction. According to the instruction data packet generation method provided by the invention, during modification each time, instruction modification can be realized through the configured instruction configuration file, the configured source operand configuration file and the configured register configuration file, so that instruction configuration modification is completed without changing scripts, the period of instruction configuration modification each time is shortened, and the modification efficiency is improved. And development cycle lag is avoided.

An electronic chip, a chip assembly, a computing device, and a method are described. The electronic chip comprises a plurality of processing cores and at least one hardware interface coupled to at least one of the one or more processing cores. At least one processing core implements a game engine and / or a simulation engine and at least one or more processing cores implements an artificial intelligence engine, whereby implementations are on-chip implementations in hardware by dedicated electronic circuitry. The at least one or more game and / or simulation engines performs tasks on sensory, generating data sets that are processed through machine learning algorithms by the hardwired artificial intelligence engine. The data sets processed by the hardwired artificial intelligence engine include at least contextual data and target data, wherein combining both data and processing by dedicated hardware results in enhanced machine learning processing.

The invention provides a multi-core parallel simulation method and device, computer equipment, a storage medium and a program product, and relates to the technical field of chip design and emulation.According to the implementation scheme, in a window interval, a simulation instance independently executes a first event associated with the local, outbound messages generated during execution of the first event are buffered locally to be sent to a message queue in batches when a predetermined sending condition is satisfied; receiving the inbound message from the message queue according to a preset receiving rule; upon reaching a boundary of the window interval, the emulation instance performs a second event associated with the inbound message; and changing, via a synchronization manager, the temporary storage state into a visible state for the remaining simulation instances; and the simulation time of each simulation instance is uniformly advanced to the next window interval after the window interval, so that the synchronization frequency and the cross-core communication overhead can be remarkably reduced, the simulation throughput and expansibility are improved, and the chip design efficiency is favorably improved.

The invention provides an instruction execution method and apparatus, and an electronic device. The method comprises the steps of obtaining an input command; determining a first instruction corresponding to the input command; a data packet of the first instruction is obtained, and the data packet is obtained based on a pre-configured instruction configuration file, a pre-configured source operand configuration file and a pre-configured register configuration file; determining the slot parallel execution number of the vector processor; and according to the slot parallel execution quantity, processing the data packet in each beat through a functional unit of the vector processor. According to the instruction execution method provided by the invention, during modification each time, instruction execution can be realized through the configured instruction configuration file, the configured source operand configuration file and the configured register configuration file, so that instruction execution can be completed without changing scripts, the period of instruction configuration modification each time is shortened, and development period lag is avoided.

Provided in the embodiments of the present disclosure are a processor, an instruction processing method, and an electronic device comprising the processor. The processor comprises a plurality of processor cores and an accelerator module, each of the plurality of processor cores being configured to execute first-type instructions; the accelerator module comprises at least one accelerator engine that is configured to execute second-type instructions different from the first-type instructions; the accelerator module is coupled to the plurality of processor cores and shared by the plurality of processor cores; each of the plurality of processor cores dispatches, from an instruction stream processed thereby, an object instruction belonging to the second-type instructions to the accelerator module for execution, and receives from the accelerator module an execution result message for the object instruction.

An electronic chip, a chip assembly, a computing device, and a method are described. The electronic chip comprises a plurality of processing cores and at least one hardware interface coupled to at least one of the one or more processing cores. At least one processing core implements a game engine and / or a simulation engine and at least one or more processing cores implements an artificial intelligence engine, whereby implementations are on-chip implementations in hardware by dedicated electronic circuitry. The at least one or more game and / or simulation engines performs tasks on sensory, generating data sets that are processed through machine learning algorithms by the hardwired artificial intelligence engine. The data sets processed by the hardwired artificial intelligence engine include at least contextual data and target data, wherein combining both data and processing by dedicated hardware results in enhanced machine learning processing.