648 results about "External interface" patented technology

The invention discloses a visual arrangement method for model tool calling based on an MCP, and relates to the technical field of artificial intelligence, the method is applied to a model context protocol MCP server, and the method comprises the following steps: receiving a first tool calling request sent by a client, the first tool calling request being generated by a large language model deployed on the client according to the MCP; the first tool calling request is analyzed through a preset unified agent tool and preset tool configuration information to construct a second tool calling request, and the tool configuration information is generated according to configuration operation of a preset visual arrangement interface on the MCP server; sending the second tool calling request to the external interface service, and receiving response information generated by the external interface service according to the second tool calling request; and constructing a request result according to the MCP and the response information, and sending the request result to the large language model. According to the method, the model tool calling efficiency is improved.

Disclosed are a method and apparatus for identifying peripheral configuration of server, a method and apparatus for laying out peripheral silkscreen, and a server. The method includes: determining a PCIE external interface of each central processing unit on the basis of configuration requirement information of a server to be identified; determining, in sequence according to a level state of each peripheral ID signal transmitted by each PCIE external interface, a peripheral type that is capable of being configured for a peripheral bandwidth corresponding to the peripheral ID signal, allocating corresponding serial numbers to peripherals of different peripheral types, generating a peripheral silkscreen including all peripheral sequences managed by the server to be identified; sending the peripheral silkscreen to a basic input output system and / or a baseboard management controller, and allowing the basic input output system and / or the baseboard management controller to unify respective default silkscreen into the peripheral silkscreen.

The invention provides a storage and calculation integrated calculation module based on an OAM (Operation Administration and Maintenance) form, which is used for integrating a plurality of storage and calculation integrated chips of different types and realizing communication between a CPU (Central Processing Unit) and the storage and calculation integrated chips, and is characterized in that an external interface of the calculation module is connected with an external UBB (Universal Business Business) bottom plate by adopting an interface designed by an OAM protocol; the calculation module comprises a power supply interlayer card, a controller card and a memory operator card which are sequentially connected in a stacked mode, and the power supply interlayer card is configured in the mode that a power supply interface designed through an OAM protocol is used for conducting power supply conversion, supplying power to the controller card and the memory operator card and providing a path for data signal transmission between the controller card and a CPU on an external UBB bottom plate; the controller card is configured to perform conversion among different protocols, and communication and data signal transmission between the operator card and a CPU (Central Processing Unit) on the external UBB bottom plate; the storage operator card is configured to store a data signal and provide a chip connection interface for one or more storage and calculation integrated chips; and a data signal is transmitted to the storage and calculation integrated chip connected with the chip connecting interface through the chip connecting interface.

A Harvard-architecture computer simultaneously reads instructions using an instruction bus and accesses data over a separate data bus. A debug module has an external interface to an external debugger that initiates a debugging session by setting a debug bit in a debug mode register. When the debug bit is set, a first mux to disconnect an instruction pointer and an instruction buffer from the instruction bus and instead connects the data bus to the instruction bus. A second mux disconnects a load / store unit in an execution core from the instruction bus and instead connects the debug module to the instruction bus. The external debugger sees a unified memory space and writes addresses to the debug module that are sent through the second mux to access the data memory, and instruction addresses are sent through the second mux and the first mux to the instruction memory to read or write instructions.

The satellite-borne heterogeneous computing system comprises a CPU (central processing unit) module, an FPGA (field programmable gate array) module and an NPU (network processing unit) module, the CPU module is used for receiving instructions and telemetering polling of a satellite service computer, reading load scientific data received by the FPGA module, providing installation and operation environments for various types of universal application programs, and scheduling and controlling the NPU module; the FPGA module is used for providing external interface expansion, receiving load scientific data and sending the load scientific data to the CPU module, and is also used for providing a logic control function comprising SPI FLASH triple modular redundancy logic and barking reset; and the NPU module is used for performing high-performance calculation and providing a high-computing-power environment for the system. The system has high flexibility, reliability and universality, and can operate various computing software and neural network algorithms; the power consumption is low, and strict requirements of a satellite platform on power consumption can be met. And a plurality of systems are interconnected to form a distributed computing system, so that the performance is extremely high.

The present invention relates to a fully automated train monitoring system, a method, a device, and a storage medium, the system comprising: a central security interface server, which is used for protocol adaptation between different interfaces and unified data integration; a central external interface server, which is in communication with the central security interface server and is used for completing acquisition of rail transit data; a central real-time monitoring server, which is in communication with the central security interface server and is used for fully automated operation of monitoring an on-site train in real time; a central information processing server, which is in communication with the central external interface server and the central real-time monitoring server and is used for processing the rail transit data; and an operating terminal, which is in communication with the central information processing server and is used for displaying, on the basis of different user role definitions, human-computer interaction interfaces having different operating functions. Compared with the related technology, the present invention has advantages such as flexible architecture, numerous functional modules, a high degree of automation, powerful performance, security and dependability, and human-centered design.

The invention relates to the technical field of platform door control, in particular to a communication-based SIL4 platform door system, which comprises a domain controller, a DCU (Data Control Unit), an external interface and other subsystem equipment, the platform door system realizes interconnection and intercommunication with a signal system and other subsystem equipment through bus connection and hard wire connection, high safety and high reliability of the system are ensured, a dual-CPU architecture is adopted in a domain controller and a door control unit, dual processing and cross verification can be carried out on data by utilizing a dual-CPU design, and the system is convenient to use. The accuracy and consistency of data are ensured, so that an existing relay circuit is replaced to reach an SIL4 security level; a data transparent transmission mechanism is carried out by using a single CPU, so that the data transmission delay is reduced, and the real-time response capability is improved.

The invention provides an FPGA (Field Programmable Gate Array) accelerator card with a hard synchronization function, which comprises an FPGA chip used for processing a computing task issued by a universal processor system, the FPGA chip is provided with a storage module and a power supply module, and external interfaces comprise a PCIE (Peripheral Component Interface Express) interface, a QSFP (Quad Small Form-factor Pluggable) optical interface, an SMA (Shape Memory Alloy) interface and an RS422 interface. And the PCIE interface and the QSFP optical interface are respectively interconnected with the high-speed port of the FPGA module at a high speed. And the storage module, the SMA interface and the RS422 interface are all connected to a general I / O pin of the FPGA. According to the invention, the synchronization signal from the external device can be received, and the PCIE message interrupt is sent to the universal processor system end through the PCIE interface, so that the synchronization time base establishment between the universal processor system and the acceleration card external device is realized. And the message interruption of the PCIE is used as a strong real-time synchronization mode, so that the accurate control on the external equipment can be realized. Meanwhile, the PCIE module and the QSFP optical interface can achieve high-speed data transmission, and the acceleration card supporting strong real-time processing is formed by combining high-density parallel computing of the FPGA.

The invention discloses an FPGA prototype verification platform based on an RISC-V chip. The FPGA prototype verification platform comprises the RISC-V chip, an RISC-V processor core is instantiated in FPGA logic resources, and the RISC-V processor core realizes a standard RISC-V instruction set, supports an RV32I / RV64I basic integer instruction set, M standard multiplication and division extension, A atom operation extension and F single precision floating point extension; the off-chip memory is used for providing code and data storage for the RISC-V chip by using FPGA off-chip storage resources; the RISC-V chip is connected with the off-chip memory through the memory controller and the bus interface; the external interface circuit realizes that an I / O interface is externally connected with a sensor and an actuator, and the application range of the RISC-V chip is expanded; the programmable logic circuit constructs various hardware acceleration units according to needs by utilizing programmable logic resources of the FPGA and is interconnected with the RISC-V chip through a standard AXI bus or a custom bus, and the hardware acceleration units cooperate with the RISC-V chip to work, so that the system performance is improved; and the software and hardware collaboration system provides a software development environment and a hardware development suite.

The utility model discloses a portable vector network analyzer which comprises a shell, an energy storage power supply, a display control panel, an external interface, a numerical control circuit board and a radio frequency circuit board. The energy storage power supply is used for providing a working power supply, the display control panel is used for displaying and controlling the portable vector network analyzer, the external interface is used for connecting peripheral equipment, and the radio frequency circuit board is used for converting a radio frequency signal input by the radio frequency input and output port into an intermediate frequency signal and then sending the intermediate frequency signal to the numerical control circuit board; and the numerical control circuit board is used for performing electrical parameter analysis on the intermediate frequency signal and displaying an electrical parameter analysis result through the display control panel. As the working power supply is provided by the energy storage power supply, the vector network analyzer can be ensured to continuously work for a long time without an external power supply, and a complete test function of a common vector network is provided.

The invention relates to a satellite navigation baseband processing device optimized by a coprocessor. A core processing part of the device adopts a realization framework of a main processor and a coprocessor; the coprocessor is used for scheduling hardware acceleration computing resources in real time under exchange control of the main processor, and completing high-real-time processing tasks such as signal capture and tracking loop processing of satellite navigation; an instruction set and an external interface of the coprocessor are subjected to targeted optimization, the bus bit width and the internal storage width of the coprocessor are expanded, and the in-situ width of an ALU and a register of the coprocessor is reserved; performing bus data access and storage by adopting an external port access instruction and an internal memory access instruction which are matched with the expanded bus according to the expansion state; and performing access and storage of single register data by adopting a bus write enable, an access instruction and a storage instruction which are matched with the expanded internal storage width. According to the invention, the function load of the main processor is effectively reduced, and the implementation cost of the baseband processing device is reduced.

The invention discloses a supply chain management system for research and development of electronic materials, and belongs to the technical field of supply chain management systems. Internet-of-things equipment data is acquired through sensors deployed in a raw material production link, a warehouse storage area and a transport vehicle, external interface data is from a supplier system, enterprise internal system data comprises PLM, ERP and MES system data, and the data processing layer performs real-time cleaning, conversion and stream batch fusion processing on the acquired data based on a stream calculation engine and performs data processing on the acquired data. The data storage layer adopts a hybrid storage architecture and comprises a Kafka cluster used for storing real-time data, an InfluxDB used for storing time sequence data, an HBase used for storing unstructured data and a MySQL cluster used for storing dimension data.

The embodiment of the invention provides a butterfly computing unit, a butterfly computing unit array, a reconfigurable array and a chip. The butterfly computing unit comprises a first-in first-out cache unit, a butterfly computing module, a multiplier module, a twiddle factor storage module, a first external interface and a second external interface. The first external interface inputs radix-2 or radix-3 FFT data. And the first-in first-out cache unit caches the input data or the data output by the butterfly computing module or the data output by the multiplier module. And the butterfly calculation module receives the data output by the first-in first-out cache unit, and performs butterfly calculation to obtain butterfly calculation result data. And the multiplier module obtains the twiddle factor from the twiddle factor storage module and performs multiplication calculation on the data output by the first-in first-out cache unit or the data output by the butterfly calculation module according to the twiddle factor to obtain multiplication calculation result data. And the second external interface sends out multiplication calculation result data. According to the invention, the structure of the butterfly computing unit is simplified, and the hardware resource consumption is reduced.

The invention, which relates to the technical field of the semiconductor manufacturing equipment, provides a stepping motion apparatus for inhibiting the counter-acting force of an external interface, comprising a load, a Y-direction execution mechanism, an X-direction execution mechanism, a Y-direction counter-acting force balance mechanism, an X-direction counter-acting force balance mechanism, a support frame and a marble platform. The load is arranged on the Y-direction executing mechanism, the Y-direction executing mechanism is arranged on the X-direction executing mechanism, the X-direction executing mechanism is arranged on the supporting frame, the supporting frame is arranged on the marble platform, and the Y-direction counter-acting force balancing mechanism and the X-direction counter-acting force balancing mechanism are both arranged on the supporting frame. Compared with the prior art, the stepping type motion device for restraining the counter-acting force of the external interface can restrain the counter-acting force generated by the stepping type motion device on the mechanical installation interface of the foundation frame in the working process, and the motion and measurement precision of the stepping type motion device is guaranteed.

The invention provides a PID self-tuning vacuum pressure adjusting device. The PID self-tuning vacuum pressure adjusting device comprises a human-computer interface, an external interface, a control unit, a pressure acquisition module, a PID self-tuning unit, a power execution unit and a valve, the PID self-tuning unit realizes a pressure adjustment function, is different from a conventional PID adjustment algorithm, has the capability of automatically correcting PID parameters, outputs a valve position adjustment value, controls the pressure to quickly approach a target position, and reduces steady-state errors. The power execution unit receives the target valve position, and a driving motor drives a speed reducer to run to the target position; the valve department controls the through-flow area of the pipeline so as to adjust the pressure value of the pipeline. By the adoption of the device, for the vacuum pressure adjusting technology with hysteresis quality, the pressure of the cavity can be adjusted more accurately, steady-state errors are smaller, fluid waste caused by fluctuation is reduced, equipment can be separated from a PLC to operate independently according to a preset target value, flexibility is higher, and the equipment cost can be reduced.

The invention relates to the technical field of computers, and discloses a first-in first-out memory capable of achieving random address access and a data processing method in order to solve the problem that data written into an FIFO (First In First Out) memory cannot be modified in a current-level circuit. Each storage block is used for storing an Ethernet frame; the write control logic and the read control logic are used for performing read-write access on the current storage block according to a first-in first-out sequence through the first external interface signal, and further used for performing data backward reading / rewriting on a specified address of the current storage block through the first external interface signal and the second external interface signal; the second external interface signal comprises an in-block write enable signal, an in-block write address signal, an in-block read enable signal, an in-block read address signal, a block write end signal and a block read end signal. By adopting the first-in first-out memory capable of being accessed by the random address, data in the FIFO memory can be modified in a current-stage circuit.

The invention relates to the technical field of data processing, and particularly provides a non-intrusive log processing method, system and device and a storage medium, and the method comprises the steps: marking annotations for business items of a business application layer through a dependency management function; triggering a pre-developed section component layer based on the annotation when the business item is called, intercepting operation data of the business item by the section component layer, and generating log data by analyzing the annotation attribute of the business item and the operation data; and calling an external interface of a pre-constructed log micro-service, sending the log data to a message queue of the log micro-service, and providing the log data to a consumer of the log micro-service by the message queue. According to the method, an annotation form is used, self-defined annotation is added on a method needing to operate log recording, decoupling of business codes and log recording codes in the encoding stage is achieved, and non-intrusive log obtaining and processing are achieved.

The invention discloses a model-based electronic information product interface definition and mapping method and device, and the method comprises the steps: defining a logic layer interface model of a single machine according to the logic function of an interface, decomposing and refining a black box function logic interface of a subsystem and a flow item borne by the black box function logic interface, and capturing all external interfaces of the concerned single machine; defining a physical layer interface model of the single machine, describing physical node information in the interface, and replacing the type of the external interface of the single machine from the logic layer interface model to the corresponding physical layer interface model; defining an equipment layer interface of the single machine, and generating single machine external electrical connector node information based on a mapping relation between the physical layer interface and the equipment layer interface; obtaining a user-defined interface information table, and generating an interface data list containing single-machine external connectors and connector node information based on the incidence relation of the model information; and analyzing a structured text which is exported by the SysML model and contains detailed information of a single-machine interface through a schematic diagram design tool, and automatically creating a schematic diagram design model of a corresponding interface connector.

A basic computing unit includes a processor and a memory, and the basic computing unit communicates with an extension unit through an external interface. The extension unit is configured to extend a function of the basic computing unit. The basic computing unit is further provided with a mounting structure, and the basic computing unit is fastened, via the mounting structure, to a chassis on which the basic computing unit is located. A position of the mounting structure on the basic computing unit is determined based on the processor, the memory, and a stress factor, and positions of mounting structures on basic computing units of different sizes overlap.

A device and method used for protection against attacks using a HID keyboard or mouse, the device comprising: one or more HID internal interfaces for connecting the HID input interface of the protected device; one or more HID external interfaces for connecting to the external device; a forwarding control module for connecting to the HID internal interface and HID external interface respectively; and protocol analysis module, for performing protocol analysis on the external device connected to the HID external interface to determine whether the external device is a legitimate HID keyboard or mouse device; wherein, the forwarding control module is used to switch the HID internal interface and the HID external on or off to prevent illegal HID keyboard or mouse devices from accessing to the protected device. The present invention can prevent the unauthorized access of HID keyboard or mouse devices from damaging the protected devices.

The invention relates to a data transmission method and device, a core particle, a computer readable storage medium and a computer program product. The method comprises the following steps: receiving first data from a consistency interconnection bus through a first receiver; the first receiver is matched with an external interface of the consistency interconnection bus; performing first conversion on the first data, and sending the converted first data to a core particle interconnection module through a first transmitter; the first transmitter is matched with the external interface of the core particle interconnection module; receiving second data from the chip particle interconnection module through a second receiver; the second receiver is matched with an external interface of the core particle interconnection module; second conversion is carried out on the second data, and the converted second data is sent to the consistency interconnection bus through the second transmitter; and the second transmitter is matched with the external interface of the consistency interconnection bus. By adopting the method, the communication between the consistency interconnection bus of the core particles and the core particle interconnection module can be realized.

The invention discloses a caching method for questions and answers of a large language model. The method comprises the following steps: obtaining multiple rounds of dialogue results of the large model according to questions input by a user; inputting multiple rounds of dialogue results into the large model for identification, removing unsatisfied answers of the user and returning correct questions and answers; inputting the obtained questions into a large language model for keyword extraction, and obtaining keywords with the same semantics as the questions; taking the keyword as a key and the answer as a value, writing the keyword and the answer into a distributed redis cache, and setting the validity period and the writing time of the cache; obtaining a new round of questions of the user and judging whether cache information can be searched from the cache or not; if yes, the cached answer is returned to serve as the reply of the current user question; otherwise, if not found, the large model generates a new answer according to the business process. The response speed is increased, the load of the server is reduced, external interface calling is reduced, and the use cost of the external interface is reduced.

The invention discloses an AURORA-based simplex IP core receiving and transmitting fusion processing method, which belongs to the technical field of communication, and comprises the following steps: creating an AURORA project, and carrying out parameter configuration; wherein the AURORA project comprises a transmitting end IP core and a receiving end IP core; adjusting the modules in the sending end IP core and the receiving end IP core; interconnection is carried out on the adjusted sending end IP core and the adjusted receiving end IP core, and the sending end IP core and the receiving end IP core are respectively connected with an external interface; and carrying out position constraint on the connected sending end IP core and the receiving end IP core, and generating a bit stream so as to realize sending and receiving fusion processing. By adopting the method, data transmission can be realized when the same channel TX and RX are connected with different peripherals.

The invention discloses a system and method compatible with ARINC 739 and ARINC 661, and the system employs an MVC mode, and divides an airborne system function into an airborne system model, a view, and a controller. The model is used for realizing the service logic of the airborne system function and providing the underlying implementation of an external interface of the airborne system function; the view is used for realizing a user interface by adopting interface elements compatible with an ARINC 739 protocol and an ARINC 661 protocol; the controller is used for processing the user request and forwarding the user request to the model; meanwhile, forwarding data returned by the model to the view for display; wherein the controller comprises a universal interface layer, and the universal interface layer is used for shielding the difference between an ARINC 739 protocol and an ARINC 661 protocol and providing a uniform access interface for the view. The method can adapt to different avionics system architectures.

The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

The invention discloses a multi-serial-port management method for interlocking equipment. The method comprises the following steps: creating a main thread, a plurality of control threads and a monitoring analysis thread by utilizing a multi-serial-port management module; the main thread reads a configuration file and controls starting, closing and configuration updating of the multiple control threads and the monitoring analysis threads; each control thread controls a serial port on the interlocking equipment to perform data transmission with a corresponding external interface according to the configuration file, closes the serial port when the serial port is abnormal, and opens the serial port after the abnormality is cleared; and the monitoring analysis thread records the state of the serial port according to the configuration file and counts the total communication data amount and rate of each serial port. When the serial port is abnormal, the interlocking equipment does not need to be restarted like the prior art, so that the operation of the interlocking equipment is not influenced, and the working efficiency is improved.

A vehicle including a transceiver, a vehicle sensor unit and a processor is disclosed. The transceiver may be configured to receive interface information from an interface sensor unit associated with an external interface. The external interface may be configured to be removably attached to a plurality of connection ports disposed on the vehicle. The vehicle sensor unit may be configured to determine vehicle information associated with at least one of a vehicle movement and the plurality of connection ports. The processor may obtain the interface information and / or the vehicle information. The processor may further determine an interface location relative to the vehicle based on the interface information and / or the vehicle information. Further, the processor may control a vehicle speed and / or a vehicle steering wheel rotation based on the interface location.

The invention provides a service RAN (Radio Access Network) protocol stack dynamic expansion and contraction method and system, and the system comprises a digital object management module which is used for regularly pushing received key performance indexes to a decision control module; the decision control module is used for judging whether the service instance needs to be subjected to capacity expansion or capacity shrinkage based on the key performance index, forming a capacity expansion instruction or a capacity shrinkage instruction, and sending the capacity expansion instruction or the capacity shrinkage instruction to the service scheduling module; the service scheduling module is used for carrying out service instance capacity expansion or service instance capacity reduction based on the capacity expansion instruction or the capacity reduction instruction sent by the decision control module; the API server module serves as an external uniform interface of the system and is used for data interaction between an external RAN network and the system and data interaction among modules in the system; and the database module is used for storing system data. According to the scheme, the adaptability and the flexibility of the RAN network are improved, the reliability and the stability of the system are enhanced, rapid updating and deployment are supported, and resource utilization is optimized.

The invention provides a universal high-speed DSP (Digital Signal Processor) + FPGA (Field Programmable Gate Array) embedded computer and an operation method thereof. Comprising a printed circuit board, an external interface connector, an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor) and an SDRAM (Synchronous Dynamic Random Access Memory) are arranged on the printed circuit board, the FPGA is connected with the DSP, the FPGA and the DSP are respectively connected with the external interface connector, and the DSP is also connected with the SDRAM; the external interface connector is installed on the edge of the printed circuit board, and the printed circuit board is locked on a controlled device through the external interface connector. According to the invention, the external interfaces are arranged at one place through the external interface connector, and are connected with the control equipment through the interface connector, so that the connection mode is simplified, and the connection reliability is improved; the FPGA + DSP and peripheral interfaces all adopt universal modules, so that the size of the computer is reduced, and replacement and installation are facilitated; and digital logic is reconstructed, reused and tailored in a self-defined manner, so that the diversity of the computer is greatly improved.

The invention discloses a task execution method based on a model context protocol, and the method is characterized in that the method comprises the following steps: constructing a task planning and decomposing agent which is used for decomposing a complex task of a user into a subtask tree with a lower difficulty level; constructing a service registration agent, and for the sub-tasks decomposed by the task decomposition agent, generating a corresponding MCP service by using predefined external interface identity information and registering the MCP service to an execution environment; and constructing a task execution agent, calling services from the MCP client according to the decomposed sub-tasks and the registered MCP services, and obtaining output. And meanwhile, integrating service output to generate a final result. Through multi-agent cooperation, task decomposition, MCP service generation and registration, tool calling and result integration are autonomously completed, and manual intervention is not needed.