380 results about "Core Particle" patented technology

The invention discloses an inter-core-particle communication control method, device, equipment, medium and product, the method is applied to a wafer-level chip, the wafer-level chip comprises a plurality of core particles, and the method comprises the following steps: determining transmission data and target transmission parameter information of a target receiving end core particle through a sending end core particle, performing transmission judgment on the transmission data, and determining a transmission judgment result; when the transmission judgment result is that transmission can be carried out, transmitting the transmission data to the target receiving end core particle based on the target transmission parameter information, and adjusting the target transmission parameter information; the method comprises the following steps: determining receiving end congestion information through a receiving end core grain according to received transmission data, generating a return message and feeding back the return message to a sending end core grain; and adjusting the to-be-adjusted transmission parameter information according to the return message through the sending end core grain to obtain the adjusted transmission parameter information. Flow control is actively carried out through the core particles at the sending end, the problem of transmission congestion of the core particles is avoided, and therefore the performance advantages of the wafer-level chip are brought into full play.

The invention relates to a core particle testing method and system, computer equipment, a storage medium and a computer program product, and is applied to the technical field of chip testing. The method comprises the following steps: acquiring the number of module chips of a to-be-tested core particle; determining at least one test environment component matched with the number of the module chips; the at least one test environment assembly is in one-to-one correspondence with the module chips of the to-be-tested core particles; and running each test environment component in parallel, and testing the corresponding module chip through each test environment component according to a preset test case to obtain a test result of each module chip. By adopting the method, different chip specifications can be adapted, the development cost is saved, the test environment components run in parallel when the core particles are tested, and the test efficiency of the core particles is improved.

A latent heat storage particle that comprises a core particle and a coating part covering at least a part of the surface of the core particle, wherein: the core particle is composed of an element selected from the group consisting of Al, Mg, Si, Ti, Fe, Ni, Cu, Zn, Sn, Sb, Ga, In, Bi, Pb and Cd or an alloy or a compound mainly composed of the same and has a melting point of 100° C. or higher; the coating part is composed of one or more selected from the group consisting of an element different from the component of the core particle, an alloy and an inorganic compound containing the element and a mixture thereof, which does not undergo a chemical reaction with the core particle in the temperature range of the operating temperature; and at least a part of the coating part is in a particulate shape.

The invention provides a 3D structure core particle test layout design method supporting cross-layer cascade test and single core particle self-test, and the method comprises the following steps: a, designing the test point layout of 3D stacked core particles, each layer of core particles adopting a hexagonal arrangement mode, and enabling a test PIN in one layer to be connected with six signal PINs in the same layer; and meanwhile, a vertical test channel is arranged, so that the in-layer test PIN of each layer is connected with the corresponding test PIN of the adjacent layer through a vertical interconnection structure. According to the invention, full test coverage of 3D stacking is adapted, the problem that interlayer signals are difficult to test in a 3D structure is solved through the in-layer hexagonal layout and the vertical test channel, and full-scene coverage of in-layer, interlayer and cross-core particle signals is realized.

The invention relates to the technical field of fracturing propping agents, in particular to a method for preparing a ceramsite sand fracturing propping agent by taking asbestos ore as a raw material. The ceramsite sand fracturing propping agent comprises inner core particles and an outer layer covering film, wherein the inner core particles comprise the following components in parts by weight: 25-35 parts of asbestos ore, 40-50 parts of bauxite, 10-20 parts of solid waste ceramsite sand, 1-3 parts of a sintering aid, 15-25 parts of potassium feldspar, 3-8 parts of dolomite, 8-12 parts of kaolin, 1-2 parts of titanium oxide and 0.5-1.5 parts of manganese powder; and the outer-layer covering film is modified epoxy resin. The ceramsite sand fracturing propping agent prepared by the invention not only has excellent mechanical property and high flow conductivity, but also has excellent hydrophobic property, so that the service life of the ceramsite sand fracturing propping agent is prolonged.

The invention discloses a self-suspending proppant and a preparation method thereof, and relates to the technical field of oil and gas field fracturing exploitation, the method comprises the following steps: S1, preparing modified core particles; step S2, preparing coated particles; and S3, preparing the self-suspending proppant. The self-suspending proppant prepared by introducing a silane coupling agent, a hydrophobic monomer and a sulfonic group-containing monomer and coating acrylamide polymer films with different functions in a double-layer manner mainly comprises modified inner core particles, an outer coating layer 1 and an outer coating layer 2, the self-suspension proppant has the advantages of being stable in structure, good in self-suspension capacity, high in shear resistance, capable of still keeping suspension after being washed for multiple times and the like.

The invention provides a data transmission method between core particles, which is applied to a first core particle and comprises the following steps: encrypting plaintext data to obtain ciphertext data; and sending the ciphertext data to a second core grain. The invention further provides a data transmission method applied to the second core particle, a chip, a computer readable medium and a computer program product.

The invention discloses a preparation method of a composite slow-release carbon source, which comprises the following steps: preparing an inner core: uniformly dry-mixing lignin powder and a quick-acting carbon source, and adding a first binder to prepare inner core particles; middle layer wrapping: alternately spraying a second binder and middle layer coating powder until the middle layer is completely wrapped to obtain double-layer particles; outer layer wrapping: alternately spraying a third binder and outer layer coating powder until the outer layer is completely wrapped to obtain three layers of particles; and spraying a biodegradable polymer solution on the surfaces of the three layers of particles to form a coating film. Through the three-layer structural design of the quick start layer, the stable maintenance layer and the long-acting guarantee layer, accurate matching of carbon source release and microbial metabolism requirements is realized. The outer-layer quick-acting carbon source quickly starts microbial activity, the middle layer provides stable and continuous carbon source supply, and the inner core ensures the tail-section treatment effect. The sequential release mechanism effectively avoids burst release waste of the carbon source, so that the utilization rate of the carbon source is greatly improved.

The invention discloses a preparation method of magnesium-calcium refractory aggregate with a core-shell structure, which comprises the following steps: granulating dolomite powder to form core particles, and uniformly adhering magnesium source powder to the core particles to form precursor particles with a double-layer structure; the adding amount of the magnesium source powder is controlled according to the mass ratio of the content of MgO in the magnesium source powder to the content of MgCa (CO3) 2 in the dolomite powder being (5-30): 100; and finally, heating and sintering the dried product of the precursor particles at the heating rate of 5 DEG C / min, and preserving heat to obtain the magnesium-calcium refractory aggregate with the core-shell structure. The method has the advantages of easily available raw materials and low production cost; the process is simple and suitable for large-scale production; the product is high in hydration resistance, high in refractoriness, excellent in slag corrosion resistance and wide in market prospect.

The invention provides a method for stacking core particles on a wafer and a semiconductor device. The method comprises the following steps of: S1, arranging the wafer in a laminating device in a manner that one surface with a circuit pattern structure faces downwards; s2, absorbing the upper surface of a wafer from top to bottom by using a wafer absorbing device, and placing the wafer in the laminating device in a manner that one surface with a circuit pattern structure faces upwards; and S3, carrying out bonding by taking the direction from bottom to top as the bonding direction from the wafer to the wafer, and completing the stacking of the core particles on the wafer. According to the invention, particle pollution introduced by intermediate processes (such as cutting, picking, overturning and the like of a chip) in processing engineering is avoided, so that the technical problems of bonding strength reduction and bonding electrical failure are greatly avoided.

The invention provides a core particle type selection method, which comprises the following steps: S1, acquiring a core particle library in a data form constructed according to a specified core particle library specification, the core particle library containing a plurality of core particles and description files thereof; s2, obtaining a to-be-accelerated application, obtaining the application, and converting the application into a task data flow diagram by using a semantic matching rule, the task data flow diagram comprising operators and dependency relationships thereof; s3, according to the core particle library and the task data flow diagram, performing multiple times of grouping mapping for each core particle combination based on the multiple core particle combinations, calculating performance indexes of each task grouping mapping scheme, and determining an optimal core particle combination according to the performance indexes of the task grouping mapping schemes, the task grouping mapping scheme comprises a plurality of mapping relations, and each mapping relation comprises an operator in an application, a grouping serial number of the operator and an operation core grain distributed for the operator. According to the method, the model selection efficiency and quality of the core particle integration system can be improved, and the time overhead and cost of manual model selection are reduced.

The embodiment of the invention provides a chip verification method, system and device and a storage medium, a chip comprises a core particle group, the core particle group is formed by coupling a plurality of core particles, and the method comprises the following steps: based on a core particle verification environment, performing a verification test on a to-be-tested designed core particle; after the core particles pass the verification test, a core particle group verification environment is generated, the core particle group verification environment comprises a plurality of core particle verification sub-environments, and the core particle verification sub-environments are obtained based on instantiation of the core particle verification environment; and based on the core particle group verification environment, carrying out verification test on a to-be-tested designed core particle group. According to the chip verification method in the embodiment of the invention, complete verification of the core particle group can be realized.

The invention discloses a wafer cutting method, and relates to the technical field of wafer cutting processing. The wafer comprises a front face and a back face which are oppositely arranged, the front face is provided with a plurality of chip function areas and cutting channel areas located between every two adjacent chip function areas, and the wafer cutting method comprises the steps that a front face protection film is attached to the front face of the wafer; carrying out thinning processing on the back surface of the wafer so that the wafer is thinned to a preset thickness; removing the protective film on the front surface, and pasting a through cutting film on the back surface of the wafer; performing laser grooving treatment on the front surface of the wafer corresponding to the cutting channel region; performing back laser transmission invisible cutting on the wafer subjected to the laser slotting treatment corresponding to the cutting channel region, so that the wafer is divided into a plurality of core particles; and stretching the through cutting film so as to enable two adjacent core particles in the wafer to generate an interval, and carrying out material taking treatment on the core particles. According to the method, the steps are few, the film reversing process from grooving to hidden cutting is omitted, the wafer cutting efficiency can be improved, the fragment rate is reduced, the number of core particles is increased, and the machining cost of a single core particle is reduced.

The invention discloses a windowing heat dissipation structure of an ABF carrier plate on a PCB and a process method, and belongs to the field of integrated circuit packaging processes, the windowing heat dissipation structure comprises an ABF carrier plate, the front surface of the ABF carrier plate is connected with a first core particle through a copper column bump, the back surface of the ABF carrier plate is connected with a second core particle through a copper column bump, a redistribution layer is arranged between the copper column bumps, and the first core particle is connected with a second core particle through a copper column bump. The first core particle and the second core particle are connected through a redistribution layer in the copper column protruding block. A plurality of solder balls are arranged on the two sides of the back face of the ABF carrier plate, the back face of the ABF carrier plate is connected with a windowing PCB through the solder balls, and the second core particles leak out of the windowing position of the windowing PCB, so that the second core particles leak out of a window body and are directly exposed in the external environment; according to the invention, the limitation of a traditional closed structure on heat dissipation is broken through, so that heat can be dissipated into surrounding air more quickly, the heat dissipation efficiency of the core particle II is remarkably enhanced, and the working temperature of the core particle II can be effectively reduced.

The invention provides a connection point arrangement method for core particle interfaces and a core particle system.The method comprises the steps that a core particle boundary and the total number M of groups to be arranged are obtained, the core particle boundary represents an area where connection points on core particles can be arranged, and the total number of groups is the sum of the number of groups of all parallel interfaces of the core particles; dividing a plurality of non-overlapping grouping exclusive areas N in the boundary of the core particles according to the total number M of groups, N being greater than or equal to M; a corresponding packet exclusive area is matched for each packet, connection points of the corresponding packet are arranged in each packet exclusive area, and the connection points of each packet comprise data connection points and redundant connection points; according to the method, the connection points of the same group are arranged in a more concentrated manner, so that concentrated faults appear in the same group with a higher probability, and the fault-tolerant capability of the parallel interface is improved.

The embodiment of the invention provides a reconfigurable chip system and a reconfiguration method thereof, and electronic equipment. The reconfigurable chip system comprises a substrate; the one or more chips are arranged on the substrate and are interconnected through the substrate; wherein a first type of core particles and a second type of core particles are integrated in at least part of the chips, and the first type of core particles are different from the second type of core particles; the plurality of mode controllers are respectively arranged in the first type of core particles and the second type of core particles, and are configured to dynamically start or disable the first type of core particles and / or the second type of core particles in response to a mode configuration instruction written into the mode controllers through a bus, the bus connects the first type of core particles and the second type of core particles. By adopting the technical scheme, the first type of core particles and / or the second type of core particles can be dynamically enabled or disabled, so that the chip shows different characteristics.

The invention provides an interconnection high-speed interface, a core particle and a communication method, and the interconnection high-speed interface comprises a first packaging module which is used for receiving home terminal write address request information, home terminal write data information and home terminal read address request information of a core particle main body, carrying out the packaging processing of the information, and sending the information to a far-end core particle; the first decapsulation module is used for receiving far-end write completion information and far-end read data information of a far-end core particle, performing decapsulation processing and sending the information to the core particle main body; the second de-encapsulation module is used for receiving far-end write address request information, far-end write data information and far-end read address request information from a far-end core particle, performing de-encapsulation processing and sending the information to the core particle main body; and the second packaging module is used for receiving the local-end write completion information and the local-end read data information of the core particle main body, performing packaging processing and sending the information to the far-end core particle. Through the interconnection high-speed interface, the core particle and the communication method provided by the invention, the AXI interface can be adapted to the UCIe link.

This silver-coated copper powder is composed of aggregates of silver-coated copper particles each comprising a copper core particle and a silver coat layer disposed on at least some of the surface of the core particle. When the number of copper crystal grains per the silver-coated copper particle determined by examining cross sections of the silver-coated copper particles by an electron beam backscatter diffraction method is expressed by N (grains), the BET specific surface area is expressed by SSA (m2 / g), and the volume-cumulative particle diameter at 50% volume-cumulation determined by a laser diffraction / scattering particle size distribution examination is expressed by D50 (μm), then a value defined by N / (SSA×D50) is 0.3 (grains / {(m2 / g)×(μm)}) to 5.0 (grains / {(m2 / g)×(μm)\}) inclusive.

The embodiment of the invention discloses a core particle testing method and device and a chip, relates to the technical field of semiconductor testing, and can improve the testing efficiency of core particles to a certain extent. The method comprises the following steps: determining a critical path in a current to-be-detected core particle; the key path is a part of paths in all paths formed by a circuit between an input port and an output port of the core particle, and the key path is used for testing an item to be tested; and testing the to-be-tested item based on the key path. The core particle comprises at least one critical path which is arranged on the packaging substrate, the critical path is a part of paths in all paths formed by a circuit between an input port and an output port of the core particle, and the critical path is configured to be used for testing a test item required in a core particle test standard specification in a test stage. The method and the device are suitable for various test scenes of the core particles and the chips.

The invention discloses a preparation method of a core-shell structure hard alloy with high strength and high toughness, and belongs to the technical field of hard alloys and powder metallurgy. According to the preparation method, a micro heterostructure is formed after sintering through a pre-constructed'fine grain hard core-coarse grain tough shell 'powder system, and deflection and energy dissipation are promoted during crack propagation by utilizing the performance difference and interfacial effect between the core and a matrix, so that the strength and toughness of the material are synergistically improved. The method is simple in process and low in cost, the material performance can be flexibly designed by adjusting the core particle size, the core-shell components and the core-shell proportion, and the method is suitable for tools, drilling tools, wear-resistant parts and the like with strict requirements for obdurability.

The invention relates to an electrical property testing device and an electrical property testing method of a silicon substrate chip. The device comprises a wafer-level chip to be tested and a test platform, the wafer-level chip to be tested comprises a plurality of core particles and a plurality of test areas; the core particles are connected based on interconnection lines; a metal interconnection structure is pre-buried on the core particle; each test area covers the crossed area of the four core particles; the crossed region comprises a part of metal interconnection structure; and the test platform is used for controlling the probe card to be in contact with the metal interconnection structures in the test areas to carry out an electrical test on the wafer-level chip to be tested. According to the electrical property testing device, a wafer level interconnection electrical property testing method based on a window translation mode can be realized, and a whole set of testing solution which can cover the whole wafer, can be reused and can be traced is designed aiming at the reliability problem of a cross-region interconnection structure in a large-scale photomask splicing process.

Disclosed is a modified polymer obtained by enclosing and / or grafting a non-thermosensitive polymer particle with a thermosensitive polymer, the modified polymer has a viscosity exhibiting a significant change at 40 to 90℃. Also disclosed is a polymer having a core-shell structure, wherein the core particle consists essentially of a non-thermosensitive polymer, and the shell is located on the outer surface of the core particle and consists essentially of a segment derived from a thermosensitive polymer, the polymer has a viscosity exhibiting a significant change at 40 to 90℃. Further disclosed is a method for preparing an aqueous dispersion of polymer. Still further disclosed is a coating composition comprising the above modified polymer, the above polymer, or the above aqueous dispersion of polymer, a substrate coated with the coating composition, as well as use of the modified polymer, the polymer, or the aqueous dispersion of polymer.

A method for manufacturing a perovskite quantum dot composite material that easily forms core-shell particles through a one-stage synthesis step is provided, along with the perovskite quantum dot composite material and an ink containing the perovskite quantum dot composite material. This perovskite quantum dot composite material suppresses surface defects of the perovskite quantum dots by forming an ionic crystal layer comprising halides in the shell layer and exhibits a very high PLQY (Power Level Quality). The perovskite quantum dot composite material comprises core particles and a shell layer surrounding the core particles. The core particles are composed of metal halide perovskites, and the shell layer comprises an organic halide compound with an ionic crystal structure having the same halogen composition as the core particles. The PLQY is greater than 75%, and the change in emission wavelength is less than 5 nm over a period of 10,000 minutes at room temperature.

The invention discloses a manufacturing method of a three-dimensional system chip, and the method comprises the steps: providing a first wafer which comprises first core particles; providing a second core particle; manufacturing an interconnection patch cord, wherein the interconnection patch cord is used for interconnecting the electrodes in the same first core particle and / or the electrodes among different first core particles; a bonding layer is formed on the first wafer and the second core particle, and the bonding layer exposes a partial region of the electrode or the patch cord to serve as an I / O interconnection electrode; bonding the first wafer and the second chip particle by using a bonding layer, wherein the I / O interconnection electrodes of the first wafer and the second chip particle are opposite to each other; and depositing metal on the I / O interconnection electrodes of the first wafer and the second wafer until interconnection is formed. And three-dimensional system physical integration of a plurality of heterogeneous and heterogeneous core particles is realized so as to complete electrical interconnection among all the core particles required by a system chip.

A modified metal oxide particle sol, when applied as a coating onto a substrate, is capable of having transparency, a high particle refractive index and good coat resistivity. The modified metal oxide particle sol is composed of modified metal oxide particles (iii) in which stannic oxide particles (i) having an average primary particle size of 4 to 50 nm serve as cores and are coated with metal oxide particles (ii) of at least one metal oxide selected from the group consisting of antimony oxide, stannic oxide and silicon oxide and having an average primary particle size of 1 to 10 nm, which modified metal oxide particles (iii) are dispersed in an organic solvent. The average primary particle size of the core particles (i) and the average primary particle size of the coating particles (ii) satisfy the relationshipsize of core particles(i)≥size of coating particles(ii),the ratio (total weight of metal oxides other than stannic oxide) / (weight of stannic oxide) is from 0.005 to 1.0, and the sol includes an amine (a) having a water solubility of 0.1 g / L or more and an amine (b) having a water solubility of less than 0.1 g / L.

This heat storage resistor comprises latent heat storage particles and a solid medium, and has an electric resistivity within the range of 1 × 10-7 to 3 × 103 Ω·cm, wherein: the latent heat storage particles each have a core particle and a coating part that covers at least part of the surface of the core particle; the core particle has, as a component thereof, a certain element or the like, and has a melting point of 100°C or higher; and the coating part has, as a component thereof, an element or the like that is different from the component of the core particle, does not cause chemical reaction with the core particle in an operation temperature range, and has an electric resistivity within the range of 1 × 10-7 to 3 × 103Ω·cm.

A carrier for forming an electrophotographic image is provided. The carrier comprises a core particle and a coating layer coating the core particle. The coating layer contains chargeable particles and a dispersant. The carrier has an apparent density of from 2.0 g / cm3 or greater but less than 2.5 g / cm3.

A toner particle includes a core particle including a binder resin, and a plurality of fine particles that are smaller than the core particle and that are attached to a surface of the core particle. The fine particles include silica fine particles, and inorganic fine particles having a band gap energy of 2.5 to 7.0 eV and a relative permittivity of 30 to 100. The toner particle has a content of titanium dioxide of less than 1% by mass.

This invention discloses a method for preparing diamond rare-earth europium (EEUR) color core particles, belonging to the field of non-metallic element materials. The method involves coating a europium oxide suspension onto a single polished silicon wafer, followed by microwave plasma chemical vapor deposition (CPCVD) to form EEUR color core particles. This method allows for the growth of EEUR color core particles on the surface of a diamond film. The absence of obvious traces of Eu₂O₃ nanoparticles on the surface of the EEUR color core particles indicates that the diamond implantation solution within the europium oxide particles rapidly forms the EEUR color core particles during CPCVD, resulting in the diamond core ultimately covering the europium oxide particles, thus forming a core-shell structure, i.e., the diamond rare-earth europium color core particles. The obtained EEUR color core particles are mostly irregularly shaped with a diameter of approximately 8 μm.

The present invention relates to the field of pharmaceutical formulations, and in particular to a fine granule and a preparation method therefor. The provided fine granule is a fine granule having core particles, a coating layer and an additional material layer. Hydroxypropyl cellulose and / or hydroxypropyl methylcellulose in a specific proportion are selected as a tackifier, and low-substituted hydroxypropyl cellulose is used as a disintegrating agent, so that the prepared fine granule has good particle compactness, disintegration performance and dissolution performance. An anti-adherent is homogenized during the preparation of the coating layer material, so that the prepared coating layer material has good anti-adhesion effect, and does not adhere in the particle coating process, thereby ensuring the integrity of the particles. A fluidized granulation coating machine is selected for preparation and coating of the core particles, thereby ensuring more uniform particle size distribution of the fine granule.