986 results about "Electroless plating" patented technology

A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line. The third embodiment electroless deposits metal over a metal barrier layer that is roughen by chemical mechanical polishing. A solder bump is formed using an electroless deposition of Cu or Ni by: depositing an Al layer 220 and a barrier metal layer 230 over a substrate 10. The barrier layer 230 is polished and activated. Next, the aluminum layer 220 and the barrier metal layer 230 are patterned. A metal layer 240 is electroless deposited. Next a solder bump 250 is formed over the electroless metal layer 240.

A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, the third conductive material selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over the cap, and depositing a conductive material over the chalcogenide stack.

The invention includes processes for combined polymer surface treatment and metal deposition. Processes of the invention include forming an aqueous solution containing a metal activator, such as an oxidized species of silver, cobalt, ruthenium, cerium, iron, manganese, nickel, rhodium, or vanadium. The activator can be suitably oxidized to a higher oxidation state electrochemically. Exposing a part to be plated (such as an organic resin, e.g. a printed circuit board substrate) to the solution enables reactive hydroxyl species (e.g. hydroxyl radicals) to be generated and to texture the polymer surface. Such texturing facilitates good plated metal adhesion. As part of this contacting process sufficient time is allowed for both surface texturing to take place and for the oxidized metal activator to adsorb onto said part. The part is then contacted with a reducing agent capable of reducing the metal activator to a lower ionic form, or a lower oxidation state. That reduction can result in the formation of metallic catalytic material over the surface of the part. The reduced metal activator can then function to catalyze the electroless deposition of metal such as copper from solution by contacting the part with the plating solution.

A capping film serving as an interconnect protective film formed on a surface of interconnect metal on a semiconductor substrate is formed after forming a catalyst layer for electroless plating under low oxygen concentration condition. A method for forming a capping film for protecting a surface of interconnect metal includes preparing a metal catalyst solution containing a metal element nobler than interconnect metal and having dissolved oxygen concentration of 7 ppm or less, bringing said metal catalyst solution into contact with a surface of interconnect metal to form a metal catalyst layer on the surface of the interconnect metal, and performing electroless plating to form a capping film on the surface of the interconnect metal.

An electromagnetic shield for an electronic module includes a surface finish that is applied to the surface of an electronic module so as to minimize the size of the shield. Once the shield is in place, the shield acts to address electromagnetic interference (EMI) concerns associated with the electronic module. An electronic module having a ring of conductive material embedded about its peripheral edge is formed. The electronic module is then sub-diced so as to expose the ring of conductive material. After sub-dicing, a conductive material may be applied through an electroless plating process followed by an electrolytic plating process. Alternatively, a conductive epoxy may be sprayed or painted onto the surface of the electronic module.

An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

A method for forming a battery from via thin-film deposition processes is disclosed. A mesoporous carbon material is deposited onto a surface of a conductive substrate that has high surface area, conductive micro-structures formed thereon. A porous, dielectric separator layer is then deposited on the layer of mesoporous carbon material to form a half cell of an energy storage device. The mesoporous carbon material is made up of CVD-deposited carbon fullerene “onions” and carbon nano-tubes, and has a high porosity capable of retaining lithium ions in concentrations useful for storing significant quantities of electrical energy. Embodiments of the invention further provide for the formation of an electrode having a high surface area conductive region that is useful in a battery structure. In one configuration the electrode has a high surface area conductive region comprising a porous dendritic structure that can be formed by electroplating, physical vapor deposition, chemical vapor deposition, thermal spraying, and/or electroless plating techniques.

A corrosion resistant component of semiconductor processing equipment such as a plasma chamber includes a metal surface such as aluminum or aluminum alloy, stainless steel, or refractory metal coated with a phosphorus nickel plating and an outer ceramic coating such as alumina, silicon carbide, silicon nitride, boron carbide or aluminum nitride. The phosphorus nickel plating can be deposited by electroless plating and the ceramic coating can be deposited by thermal spraying. To promote adhesion of the ceramic coating, the phosphorus nickel plating can be subjected to a surface roughening treatment prior to depositing the ceramic coating.

A laminated body is prepared, in which at an end surface at which internal electrodes are exposed, the internal electrodes disposed adjacently are electrically isolated from each other, and a distance between the internal electrodes disposed adjacently is about 20 μm or less when measured along the thickness direction of an insulator layer, and a withdrawn-depth of the internal electrodes is about 1 μm or less when measured from the end surface. In a step of electroless plating, plating deposits formed at the end portions of the plurality of internal electrodes are increased in size so as to be connected to each other.

A reactor for plating a metal onto a surface of a workpiece is set forth. The reactor comprises a reactor bowl including an electroplating solution disposed therein and an anode disposed in the reactor bowl in contact with the electroplating solution. A contact assembly is spaced from the anode within the reactor bowl. The contact assembly includes a plurality of contacts disposed to contact a peripheral edge of the surface of the workpiece to provide electroplating power to the surface of the workpiece. The contacts execute a wiping action against the surface of the workpiece as the workpiece is brought into engagement therewith. The contact assembly also including a barrier disposed interior of the plurality of contacts. The barrier includes a member disposed to engage the surface of the workpiece to assist in isolating the plurality of contacts from the electroplating solution. In one embodiment, the plurality of contacts are in the form of discrete flexures while in another embodiment the plurality of contacts are in the form of a Belleville ring contact. A flow path may be provided in the contact assembly for providing a purging gas to the plurality of contacts and the peripheral edge of the workpiece. The purging gas may be used to assist in the formation of the barrier of the contact assembly. A combined electroplating/electroless plating tool and method are also set forth.

To protect the collimator of a transferred plasma arc torch from premature failure due to corrosion, an anti-corrosive covering is applied on the exposed face surface and a portion of the inner exit bore of the collimator. The specification describes several methods for producing the collimator for a plasma torch having an anti-corrosive coating or cladding on the exposed surfaces thereof, including electroplating, electroless plating, flame spraying, plasma spraying, plasma transferred arc, hot isostatic pressing and explosive cladding.

Thermoplastic compositions that are capable of being used in a laser direct structuring process to provide enhanced plating performance and good mechanical properties. The compositions of the present invention include a thermoplastic base resin, a laser direct structuring additive and a white pigment. The compositions can be used in a variety of applications such as personal computers, notebook and portable computers, cell phone antennas and other such communications equipment, medical applications, RFID applications, and automotive applications.

A dressing for promoting healing and pain relief of the body of a living organism having a pathologic condition has at least one layer of conductive material having a resistance no greater than 1000 Ω/cm². When placed proximate a portion of the body of the living organism suffering from the pathologic condition, the dressing alters the electrodynamic processes occurring in conjunction with said pathologic condition to promote healing and pain relief in the living organism. When used as a wound dressing, the conductive material is placed in contact with tissue around the periphery of the wound and with the wound, lowering the electrical potential and resistance of the wound and increasing the wound current. In an exemplary embodiment, the conductive material is a multi-ply nylon fabric plated with silver by an autocatalytic electroless plating process and with the plies in electrical continuity. The dressing provides an antimicrobial and analgesic effect. The dressing may be provided for numerous applications and may include other layers such as an absorbent layer, a semi-permeable layer and additional layer of conductor material. Multilaminate embodiments of the present invention exhibit conductive material concentration gradients and, potentially, a capacitive effect when sequential conductor layers are insulated by intervening layers.

A conductive electrolessly plated powder used, for example, for bonding a small electrode of an electronic device, its producing method, and a conductive material containing the plated powder. Conventionally, there has been known, as conductive powders, metallic powders such as of nickel, carbon powders, and conductive plating powders the resin core particles of which are coated with a metal, e.g., nickel. However, there has been no conductive electrolessly plated powders having a good conductivity with respect to connection between conductive patterns having an oxide coating thereon or between electrodes and no methods for producing such powders industrially. The conductive electrolessly plated powder of the present invention consists of resin spherical core particles the average size of which is 1 to 20 mum and each of which has a nickel or nickel alloy coating formed by electroless plating. The coating includes small projections of 0.05 to 4 mum on its outermost layer and the coating is substantially continuous with the small projections. A method of producing such a powder is also disclosed.

A negative electrode material for a nonaqueous electrolyte secondary battery having a high discharge capacity and a good cycle life is made from alloy particles having an average particle diameter of 0.1-50 mum and including Si phase grains 40 and a phase of a solid solution or an intermetallic compound of Si and other element selected from Group 2A elements, transition elements, Group 3B elements, and Group 4B elements from the long form periodic table (for example, an NiSi2 phase 42 and an [NiSi2+NiSi] phase 41) at least partially enveloping the Si phase grains. 5-99 wt % of this material is Si phase grains. The alloy particles can be manufactured by rapid solidification (such as atomization or roller quenching) of a melt including Si and the other element, or by adhering the other element to Si powder by electroless plating or mechanical alloying and then performing heat treatment. Even if rapid solidification is carried out, a negative electrode material having a good discharge capacity and cycle life is obtained without heat treatment.

A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer of the barrier metal stack removed by etching. The diffusion barrier and C4 solder bump may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.

Methods for fabricating a conductive contact (through-via) through a full thickness of a substrate such as a semiconductor wafer or interposer substrate, and semiconductor devices and systems incorporating the conductive through-via are provided. The conductive contact is fabricated by applying a metal layer onto a backside of a substrate, forming a through-hole through the substrate and the metal layer, sealing the hole in the metal layer by an electroless plating process, and filling the hole by an electroplating or an electroless plating process.

A reactor for plating a metal onto a surface of a workpiece is set forth. The reactor comprises a reactor bowl including an electroplating solution disposed therein and an anode disposed in the reactor bowl in contact with the electroplating solution. A contact assembly is spaced from the anode within the reactor bowl. The contact assembly includes a plurality of contacts disposed to contact a peripheral edge of the surface of the workpiece to provide electroplating power to the surface of the workpiece. The contacts execute a wiping action against the surface of the workpiece as the workpiece is brought into engagement therewith The contact assembly also including a barrier disposed interior of the plurality of contacts. The barrier includes a member disposed to engage the surface of the workpiece to assist in isolating the plurality of contacts from the electroplating solution. In one embodiment, the plurality of contacts are in the form of discrete flexures while in another embodiment the plurality of contacts are in the form of a Belleville ring contact. A flow path may be provided in the contact assembly for providing a purging gas to the plurality of contacts and the peripheral edge of the workpiece. The purging gas may be used to assist in the formation of the barrier of the contact assembly. A combined electroplating/electroless plating tool and method are also set forth.

A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating. The one or more metals used to treat the exposed surface may include any rare earth or transition metal, such as, for example, hafnium, lanthanum, etc.

The present invention relates to an electroless-plating liquid useful for forming a protective film for selectively protecting the surface of the exposed interconnects of a semiconductor device which has such an embedded interconnect structure that an electric conductor, such as copper or silver, is embedded in fine recesses for interconnects formed in the surface of a semiconductor substrate, and to a semiconductor device in which the surface of the exposed interconnects is selectively protected with a protective film. The electroless-plating liquid contains cobalt ions, a complexing agent and a reducing agent containing no alkali metal.

A catalyst with high activity for cleaning the tail gas of car is prepared through preparing the coated composite alumina layer containing Ce, Zr and one or more of La, Pr, Y, Fe, Mn, Cu and Ba on the cellular cordierite ceramic carrier, and chemically plating Pd.

A method and apparatus for electrolessly depositing a multilayer film using a fluid processing solution(s) that can clean and then electrolessly deposit a metal films having discrete or varying composition onto a conductive surface using a single processing cell. The process advantageously includes in-situ cleaning step in order to minimize the formation of oxides on the conductive surfaces, by minimizing or preventing the exposure of the conductive surfaces to oxygen (e.g., air) between the cleaning step and an electroless deposition process step(s). In one aspect, the chemical components used in the fluid processing solution(s) are selected so that the interaction of various chemical components will not drastically change the desirable properties of each of the interacting fluids, generate particles in the fluid lines or on the surface of the substrate, and/or generate a significant amount of heat which can damage the hardware or significantly change the electroless process results. In another aspect, no rinsing steps are required between the various deposition steps used to form the various layers, since the processing fluids are selected so that they are compatible with each other. In another aspect, throughout the process the conductive surfaces are continually in contact with various chemical components that will inhibit oxidation of the conductive surfaces and/or reduce the oxidized metal surfaces. In one aspect, a multilayer structure can formed on the surface of the conductive surface using the continuous electroless deposition process where the first layer of the multilayer structure has at least two of the following elements cobalt (Co), tungsten (W), phosphorus (P) or boron (B); and a second layer contains at least two of the following elements cobalt (Co), boron (B) or phosphorus (P). Formation of a multilayer structure on the conductive surface may have advantage since each deposited layer can have differing properties which when placed together will form a layer that has improved properties over a single deposited layer.

A silica-based interlayer insulating layer having a low dielectric constant is formed with SOG material on a substrate, in which a wiring-layer forming space is then formed. If necessary, a UV ray irradiation is performed under an oxidizing atmosphere. A Si—OH bond is formed on a surface of the insulating layer. A monomolecular layer film is then adhered to the inner surface of the space, which is then modified to be a catalyst with a solution containing Pd compound. On the catalyst monomolecular layer, a copper-diffusion-resistant film is formed by electroless plating, on which a copper plate is then formed as a wiring layer.

This invention describes a rapid tooling process that integrates solid freeform fabrication (SFF) with electroforming to produce metal tools including molds, dies, and electrical discharge machining (EDM) electrodes. An SFF part is metalized by electroless plating and then placed in an electroplating solution, where metal is deposited upon the part by electrolysis. When the desired thickness of metal has been reached, the SFF part is removed from the metal shell. The shell is then optionally backed with other materials to form a mold cavity, and EDM electrode, or other desired parts for tooling. Thermomechanical modeling and numerical simulation with finite element analysis (FEA) is used to determine the geometry of the SFF part and the electroform thickness for minimizing the manufacturing time and cost while satisfy the tooling requirement.

The adhesion of a diffusion barrier or capping layer to Cu and/or Cu alloy interconnect members is significantly enhanced by treating the exposed surface of the Cu and/or Cu alloy interconnect members with a silane or dichlorosilane plasma to form a layer of copper silicide thereon prior to depositing the capping layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu or Cu alloy interconnect member in a silane or dichlorosilane plasma to form the copper silicide layer and depositing a capping layer of silicon nitride thereon.

A method of forming a wafer level package includes attaching a laser-activated dielectric material to an integrated circuit substrate to form an assembly, the integrated circuit substrate including a plurality of electronic components having terminals on first surfaces thereof. The laser-activated dielectric material is laser activated and ablated with a laser to form laser-ablated artifacts in the laser-activated dielectric material and simultaneously to form an electrically conductive laser-activated layer lining the laser-ablated artifacts. The laser-ablated artifacts are filled using an electroless plating process in which an electrically conductive filler material is selectively plated on the laser-activated layer to form an embedded circuit pattern within the laser-activated dielectric material.

The present invention is directed towards metallized carbon nanotubes, methods for making metallized carbon nanotubes using an electroless plating technique, methods for dispensing metallized carbon nanotubes onto a substrate. The present invention is also directed towards cold cathode field emitting materials comprising metallized carbon nanotubes, and methods of using metallized carbon nanotubes as cold cathode field emitters.

A method of manufacturing a semiconductor device for realizing a semiconductor device which is suitable for enhancing the operating speed thereof and which is high in quality and reliability is provided.

The method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device including a barrier film (7) having a copper diffusion preventive function and formed on a copper-containing metallic wire (9), the method including the steps of: conducting electroplating by use of an electroplating liquid containing a catalyst metal (10) added thereto so as thereby to form the metallic wiring (2) containing the catalyst metal (10); and conducting electroless plating by use of the catalyst metal (10) exposed at the surface of the metallic wiring (2) as a catalyst so as thereby to form the barrier film (7) having the copper diffusion preventive function on the metallic wiring (2).

Process for roughening a surface of a base metal substrate includes contacting the surface with an aqueous solution comprising oxalic acid, sulfuric acid, and hydrogen peroxide at a temperature and for a period of time effective to roughen the surface to an average roughness greater than 60 Ra, removing a modest amount of base material, and generating no narrow and deep crevices at all. The surface is roughened prior to application of an electroless coating onto the substrate.