710 results about "Semiconductor chip" patented technology

The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. In particular, the disclosure relates to a semiconductor power packaging including the semiconductor device. It is a goal of the present disclosure to provide a method for manufacturing a semiconductor device without an insulation layer as a support layer for semiconductor dies thereby enhancing thermal and electrical performance as well as such a semiconductor device.

The objective is to provide a semiconductor wafer and a method for manufacturing a semiconductor wafer that can suppress deterioration of the visibility of identification parts that allow for the identification of the semiconductor wafer, even when an epitaxial growth layer is formed on the upper surface of a semiconductor substrate. [Solution] The semiconductor wafer according to this disclosure comprises a semiconductor substrate, an epitaxial growth layer provided on the upper surface of the semiconductor substrate, and an identification portion provided inside the semiconductor substrate and not exposed from the upper and lower surfaces of the semiconductor substrate, which is capable of identifying the semiconductor wafer.

The present disclosure provides, in some embodiments, a semiconductor package which includes a first semiconductor chip; a first support film that is disposed side by side with the first semiconductor chip; a second semiconductor chip that is disposed on the first semiconductor chip so as to be misaligned with the first semiconductor chip and includes a first overhang region which is supported by the first support film; a second support film that is disposed on the first support film side by side with the second semiconductor chip; an encapsulant that covers at least a portion of each of the first semiconductor chip, the second semiconductor chip, the first support film, and the second support film; and a redistribution structure that is disposed on the encapsulant and electrically connected to the first semiconductor chip and the second semiconductor chip.

Power semiconductor packages are provided. In one example, the power semiconductor package includes a first semiconductor die, a second semiconductor die, and a submount having a first side and a second side opposing the first side. The first semiconductor die is coupled to the first side of the submount, and the second semiconductor die is coupled to the second side of the submount.

A semiconductor device includes an active region extending in a first direction; a gate structure on the active region and extending in a second direction intersecting the first direction; source / drain regions on side surfaces of the gate structure and on the active region; front side contacts on a first side of the source / drain regions; backside contacts at least partially penetrating the active region and on a second side of the source / drain regions opposite the first side; and an interlayer insulating layer on the gate structure, on the source / drain regions, and on the front side contacts. An entire upper surface of the gate structure that is opposite the active region in a third direction perpendicular to the first and second directions is in contact with the interlayer insulating layer.

A semiconductor device includes a first semiconductor chip, a second semiconductor chip, a wire connecting the first semiconductor chip and second semiconductor chip, a first frame portion on which the first semiconductor chip is mounted, a second frame portion positioned above the first frame portion and apart in a left-right direction from the first frame portion and on which the second semiconductor chip is mounted, and a sealing member, wherein a recess recessed downward is formed on an upper surface of the second frame portion, the recess is positioned above the first frame portion, and the second semiconductor chip is fixed in the recess.

Provided is a semiconductor device that can prevent resin leakage during transfer molding and prevent poor appearance. The semiconductor device includes: semiconductor chips; a frame surrounding the semiconductor chips and covering the semiconductor chips from above; control terminals electrically connected to the semiconductor chips and projecting from a top surface side of the frame; and a sealing resin provided inside the frame and sealing the semiconductor chips.

According to the present disclosure there is provided a control circuit for a packaged semiconductor chip rail guide tapper driving means, comprising a control signal generator configured to generate control signals at a control frequency, and a drive module arranged to receive the control signals and output drive signals to the driving means based on the control signals to drive a rail guide tapper to tap a rail guide at a tapping frequency corresponding to the control frequency.

The utility model discloses a self-adaptive clamping and positioning device for a wafer expanding ring. The self-adaptive clamping and positioning device comprises a positioning and clamping seat, a bearing part and a floating pressing strip, the bearing part is fixed at the bottom of the positioning and clamping seat and is used for supporting the wafer expanding ring; the top of the positioning clamping seat is provided with a semi-annular structure matched with the wafer expanding ring. The floating pressing strip is of a semi-annular structure matched with the wafer expanding ring and is detachably installed on the positioning clamping base through a front face clamping structure and a side face clamping structure. When the floating pressing strip is installed in place, a circular cavity for placing the wafer expanding ring can be formed between the floating pressing strip and the positioning clamping seat. The wafer expanding ring positioning and clamping device conveniently and reliably solves the positioning and clamping problems of the wafer expanding ring, effectively assists production in the fields of micro electronic elements, semiconductor chips and the like, can be suitable for most of wafer expanding rings, and is wide in application range and small in limitation.

An object of the present disclosure is to suppress reduction of noise resistance and parasitic oscillation in a semiconductor device. A semiconductor device includes: a plurality of semiconductor chips parallelly connected to each other; a source electrode; a first source pattern connected to the source electrode; a source sensing terminal; and a second source pattern connected to the source sensing terminal, wherein a surface of each of the semiconductor chips is connected to the first source pattern, a surface of a reference chip is connected to the second source pattern, a surface of at least one non-reference chip as the semiconductor chip other than the reference chip is not connected to the second source pattern, and a resistance value of a gate resistance of the reference chip is larger than a resistance value of a gate resistance of the non-reference chip.

This invention provides a method for fabricating a dummy gate process in a semiconductor chip, comprising: providing a substrate in which a plurality of shallow trench isolation structures are formed; forming an ONO layer on the surface of the substrate with the shallow trench isolation structures; forming photoresist at the position of the dummy gate pattern corresponding to the shallow trench isolation structure; wet etching to remove the top silicon oxide layer in the ONO layer not covering the photoresist; after removing the photoresist, wet etching to remove the silicon nitride layer and silicon oxide layer in the ONO layer; forming a gate oxide layer; forming a dummy gate pattern on the surface of the substrate with the gate oxide layer; forming a sidewall layer on the surface of the dummy gate pattern; etching the substrate on both sides of the dummy gate pattern and forming source / drain regions using epitaxy; filling the source / drain regions with an intermediate dielectric layer, and then removing the dummy gate pattern. This invention avoids device failure caused by device short circuits, thereby improving device reliability.

This invention provides a common-source common-gate field-effect transistor (CFET) and a semiconductor chip with a shielded gate, comprising multiple parallel-connected transistor structure groups, each including a first transistor structure and a second transistor structure. A first stacked structure is connected to the upper end of a first drain, and both a first oxide layer and a second stacked structure are connected to the upper end of the first stacked structure. A first shielded gate is connected inside the first oxide layer and is connected to the first source. A first gate is connected to the upper end of the first oxide layer, and the first source is connected to the first oxide layer and the second stacked structure. A third stacked structure is connected to the upper end of a second drain, and the second oxide layer and a fourth stacked structure are connected to the upper end of the third stacked structure. A second shielded gate is connected to the interior of the second oxide layer and is connected to the second gate. The second gate is connected to the upper end of the second oxide layer, and the second source is connected to the second oxide layer and the fourth stacked structure.

The application discloses a semiconductor chip bonding method, which can be used in the field of semiconductor packaging. In the method, first, bonding material is attached to the back of a target circuit sheet with a bonding structure; then, known good chips are selected from chips contained in the target circuit sheet; then, the known good chips are correspondingly bonded into a plurality of recesses formed in the target wafer to obtain a reconstructed wafer; the bonding material is in contact with the bottom surface of the recess; finally, the reconstructed wafer is bonded through a wafer-to-wafer hybrid bonding process. Thus, through the known good chip screening and wafer reconstruction, the serial patching of the traditional D2W is converted into wafer-level overall bonding, the equipment throughput and production efficiency are greatly improved, the good chip-to-good chip bonding is realized, the bad chip matching is reduced, the composite yield after bonding is significantly improved, and the packaging cost is reduced.

This invention relates to the field of semiconductor chip manufacturing technology, specifically disclosing a fixture for mass semiconductor chip mounting. The fixture includes a worktable, a first main body mounted on top of the worktable, a connecting arm mounted inside the first main body, a second main body mounted at one end of the connecting arm, and a housing mounted at the bottom of the second main body. A fixing plate is mounted on one side of the housing via two connecting brackets. Multiple vacuum adsorption mechanisms are arranged inside the fixing plate, each including multiple fixing tubes. Vacuum adsorption heads are mounted at the bottom ends of the fixing tubes. A detection mechanism is located at the bottom of the fixing plate, and clamping mechanisms are located at the bottom of the two connecting brackets. In this invention, the detection mechanism and clamping mechanism work together to comprehensively detect the coaxiality of the vacuum adsorption heads, ensuring precise movement of the vacuum adsorption heads during use, thereby improving the yield rate of chip mounting.

The present application relates to inkjet adaptive planarization compositions, methods of forming a cured film, methods of manufacturing a device, and uses of a composition for inkjet adaptive planarization. The formulation may exhibit at least one of properties as an advanced material or as a high-performance material. The formulation may be used in the nanotechnology process to make semiconductor device / display device application, for example semiconductor chip, or a liquid crystal, quantum dot, OLED display fabricated on a substrate controlled by semiconductors.

A package includes a first leadframe including a plurality of leads and a conductor, a first semiconductor die mounted on a first surface of the first leadframe and attached to a first subset of the plurality of leads and the conductor, and a second semiconductor die mounted on the first surface of the first leadframe and attached a second subset of the plurality of leads and the conductor. The conductor provides a direct electrical connection for an electrical signal between the first semiconductor die and the second semiconductor die. The package further includes a second leadframe. The first leadframe is mounted on the second leadframe via a second surface of the first leadframe, the second surface opposite the first surface. The second leadframe provides a ground return path between the first semiconductor die and the second semiconductor die for the electrical signal.

A semiconductor device including one or more support structures for supporting a semiconductor-die stack having a region that overhangs a substrate. In an example embodiment, the support structures may be implemented using suitably shaped pieces of relatively thick round or ribbon wire attached to metal pads on the substrate. During the encapsulation operation, the one or more support structures may counteract a bending force applied to the semiconductor-die stack by a flow of the molding compound. At least some embodiments may beneficially be used, e.g., to enable high-yield fabrication of devices having sixteen or more stacked memory dies.

The invention relates to a chip stack package. Embodiments of the present disclosure provide a chip-on-package package, the chip-on-package package including: a first semiconductor chip having a front bump on a first surface; a second semiconductor chip stacked on a second surface of the first semiconductor chip opposite to the first surface; a carrier bump bonded to the front bump; a molding member surrounding the first semiconductor chip, the second semiconductor chip, and the carrier bump; and an external connection bump disposed on the carrier bump.

The invention relates to a radiation-emitting semiconductor chip having the following features: —a semiconductor body including an active region which, during operation, generates electromagnetic radiation and is arranged in a resonator, —at least one recess in the semiconductor body, which recess completely penetrates the active region, wherein—the recess has a first lateral face and a second lateral face opposite the first lateral face, and—the first lateral face has a first coating which specifies a reflectivity for the electromagnetic radiation of the active region, and / or—the second lateral face has a second coating which specifies a reflectivity for the electromagnetic radiation of the active region. The invention further relates to a method for producing such a semiconductor chip.

This invention provides an anomaly tracing system and method for chip carrier tray damage, belonging to the field of semiconductor chip testing technology. The system includes: a cabinet storage detection system for acquiring and sending six-sided images of the damaged tray to a tray damage tracing system; the tray damage tracing system compares the six-sided images of the damaged tray with the six-sided images of the corresponding normal tray. If the deviation of any region on any face is greater than or equal to a preset value, the region is marked as a candidate damage region, and feature point coordinates are extracted to construct a polygon; the smallest bounding polygon covering all vertices of the polygon is compared with the rectangular region of the corresponding contact position of the mechanism. If there is a spatial intersection between the two, the mechanism is determined to be a highly correlated suspected mechanism causing the tray damage. This invention achieves automated identification and accurate correlation between damaged areas and interference points.

To facilitate the extraction of electrodes onto the sealing member. [Solution] The semiconductor device of the embodiment comprises a wiring board, a laminate, a sealing member, and through electrodes. The laminate includes first to third semiconductor chips positioned opposite the wiring board such that a first surface is inclined with respect to the wiring board. Each of the first to third semiconductor chips has an electrode pad at the edge of its first surface. A second semiconductor chip is laminated in a first direction on one layer above the first semiconductor chip so as not to overlap with the electrode pad of the first semiconductor chip, and a third semiconductor chip is laminated in a first direction on one layer above the second semiconductor chip so as not to overlap with the electrode pad of the second semiconductor chip. The sealing member covering the laminate has a third surface on the electrode pad side that is substantially parallel to the plane containing the electrode pads of at least two semiconductor chips. Multiple through electrodes extend from the electrode pads through the sealing member in a second direction perpendicular to the first direction and connect to the wiring board.

The application discloses a kind of transient diodes. Including: device main body;The device main body includes: at least one first bidirectional semiconductor chip, at least one second bidirectional semiconductor chip and conductive layer;The conductive layer is arranged between the first bidirectional semiconductor chip and the second bidirectional semiconductor chip, so that the first bidirectional semiconductor chip and the second bidirectional semiconductor chip are connected in series;Wherein, the first bidirectional semiconductor chip is N-type substrate bidirectional semiconductor chip, and the second bidirectional semiconductor chip is P-type substrate bidirectional semiconductor chip.The application provides a kind of transient diodes, realize to reduce transient diode residual voltage, improve the protection ability of device.

A thermoelectric power generation device with a furnace includes a furnace head disposed in the middle of an upper bracket. The upper bracket includes support legs connected to a base ring. A heat-conducting structure is disposed beside the furnace head. The top of the heat-conducting structure is connected to the upper bracket, and the bottom of the heat-conducting structure extends downward and connects to a power generation component located below the furnace head. The power generation component includes a heat-absorbing plate, a heat-dissipating structure, and one or more semiconductor chips. One side of the heat-absorbing plate is tightly fitted to the heat-conducting structure, the other side of the heat-absorbing plate is tightly fitted to one side of the semiconductor chip, and the other side of the semiconductor chip is tightly fitted to the heat-dissipating structure. The heat-conducting structure includes a bracket, which includes a heat-conducting ring and heat-conducting columns surrounding the outside of the furnace head and close to the furnace head. The heat-conducting ring and the base ring are connected as a single unit by a first screw. This invention features high power generation efficiency.

A method for joining a first semiconductor substrate (100) (semiconductor chip) to a second semiconductor substrate (200) (semiconductor wafer) by mixed joining is disclosed. The first semiconductor substrate (100) has an organic insulating film (102), a plurality of electrodes (103), and a plurality of dummy electrodes (104). The second semiconductor substrate (200) has an organic insulating film (202) and a plurality of electrodes (203). In the method, after position alignment of the electrodes (103) and the electrodes (203) is performed, the organic insulating film (102) and the organic insulating film (202) are joined to each other, and the electrodes (103) and the electrodes (203) are joined to each other. In the mixed joining, the dummy electrodes (104) are provided on the first semiconductor substrate (100) to protrude more than the terminal electrodes (103), and the front ends of the dummy electrodes (104) are embedded in the organic insulating film (202) of the second semiconductor substrate (200). Thus, joining of the semiconductor substrates to each other is reliably performed, and manufacturing yield is improved.

A semiconductor package includes a plurality of stacked memory core dies connected to first data lines, a logic die including a processor connected to second data lines, and a buffer die stacked between the plurality of memory core dies and the logic die and including a data line reconfiguration circuit connected to the first data lines and the second data lines. The data line reconfiguration circuit includes at least one of a multiplexer circuit, a serializer / deserializer circuit, or a compressor.

A leadframe includes an array of leads around the die pad. The array includes first and second sets of leads. At least one lead in the first set includes a base portion co-planar with the die pad and a raised portion, wherein the die pad is downset relative to the raised portion. A semiconductor die is mounted to the die pad. Bonding wires electrically couple the semiconductor die to leads in the second set of leads. A clip electrically couples the semiconductor die to the raised portion of the leads in the first set of leads. The clip is positioned to extend of the bonding wires.

This application relates to a method, apparatus, semiconductor chip, and computer device for streaming data processing. The method includes: dividing the streaming data into multiple data blocks according to a time axis, wherein each data block corresponds to a time interval on the time axis; in a first time interval, a first calculation block performs calculations and classifications on the data blocks in the first time interval to obtain a first identification result and caches the first identification result; in a second time interval, a second calculation block performs calculations on the data blocks in the second time interval to obtain a second calculation result; the second calculation block retrieves the cached first identification result and classifies the first identification result and the second calculation result to obtain a second identification result. This method solves the problem of high repetitive calculation rate in streaming data processing by smart devices, which leads to high power consumption and high cost of smart devices. It reduces the repetitive calculation rate of streaming data, improves computational efficiency, and reduces costs.

The invention relates to assembly and disassembly of electronic devices, e.g. power modules or MEMS modules. In that context, the invention is situated at the intersection of advanced assembly of electronic devices and environmental sustainability. It addresses the critical need for Robust Eco-Design (RED) with design in the 7R setting. For that purpose, the invention foresees to equip components of the electronic device which are to be fixed to each other, e.g. a heat sink, a substrate, and a semiconductor chip, with interlocking arrangements which can be securely fixed to each other with a shrink fitting procedure. This allows, on the one hand, stable fixation of the components and, on the other hand, simple separation of the components for the purpose of disassembling the electronic device.

This disclosure provides a semiconductor package and a method of manufacturing a semiconductor package. The semiconductor package includes: a substrate including a redistribution layer; a plurality of semiconductor chips disposed on the substrate, each of the plurality of semiconductor chips being connected to the redistribution layer via a plurality of bumps disposed on its lower surface; a molding layer encapsulating the plurality of semiconductor chips on the substrate; a surface metal layer on the molding layer and covering at least a portion of the molding layer; a plurality of thermal vias extending vertically to connect the surface metal layer to the redistribution layer; and a plurality of pins disposed on the lower surface of the redistribution layer and connected to the plurality of bumps via the redistribution layer. The bumps and pins adjacent to the plurality of thermal vias are configured as thermal bumps and thermal pins. The thermal bumps, thermal pins, and the plurality of thermal vias are connected to each other via the redistribution layer.

This relaxes the constraints on the layout of the stacked structure of semiconductor chips on which logarithmic transformation transistors and current-voltage transformation transistors used for event detection are formed. [Solution] The imaging device comprises a photoelectric conversion element, a logarithmic transistor that generates an optical voltage by logarithmically converting the optical current output from the photoelectric conversion element, and a current-voltage conversion transistor that converts the optical current into an output voltage based on the optical voltage generated by the logarithmic transistor. A second chip is stacked on a first chip on which the photoelectric conversion element is formed, and at least one of the logarithmic transistor and the current-voltage conversion transistor is formed on the first chip.