6893 results about "Semiconductor chip" patented technology

A LIDAR system has a semiconductor chip configured to concurrently output multiple LIDAR output signals. The semiconductor chip includes alternate waveguides. Each of the alternate waveguides carries a different outgoing LIDAR signal. Each of the LIDAR output signals includes light from a different one of the LIDAR output signals. The semiconductor chip includes a reflecting surface that receives incoming LIDAR signals that each includes light from a different one of the LIDAR output signals. The semiconductor chip also includes comparative waveguides. Each of the comparative waveguides receives a comparative signal from the reflecting surface. Each of the comparative signals includes light from a different one of the incoming LIDAR signals.

To provide a semiconductor package containing an insulating material.SOLUTION: A semiconductor package 1000 contains: a re-wiring structure body 300 that contains a re-wiring layer containing copper (Cu) and an insulation layer 310 surrounding the re-wiring layer; a semiconductor chip 100 that is mounted onto the re-wiring structure body, and contains a plurality of chip-coupling members 130; an internal coupling terminal 134 that is arranged between the re-wiring structure body and the semiconductor chip, and electrically connects the re-wiring layer and a connection pad; an external coupling terminal 600 that is adhered to a lower side of the re-wiring structure body, and is electrically connected to the re-wiring layer; and a sealing member 250 that surrounds the semiconductor chip and the internal coupling terminal on the re-wiring structure body. The insulation layer is made of an insulating material, where K satisfies 20 or more in a TC index.SELECTED DRAWING: Figure 1

IC devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on / in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of such edges. Angled transistors provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips.

A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

The invention discloses a three-temperature test method and device for a semiconductor chip, and relates to the technical field of semiconductor chip testing, and the method comprises the steps: inputting an initialization parameter set into an impedance temperature mapping model, carrying out the phase angle analysis and multi-band feature fusion through a broadband impedance spectrum analysis method, obtaining a chip junction temperature instantaneous value, and carrying out the measurement of the junction temperature instantaneous value. A PID controller is utilized to dynamically compensate a junction temperature instantaneous value of a chip, a fuzzy rule base inference engine is utilized to map the junction temperature instantaneous value into an execution instruction set, the execution instruction set is converted into a bidirectional voltage signal through pulse width modulation, a semiconductor chilling plate is driven to perform bidirectional temperature rise and drop control in a three-temperature environment, and real-time temperature change test data is synchronously acquired. According to the method, the junction temperature instantaneous value of the chip can be more accurately obtained by combining broadband impedance spectroscopy analysis with a multi-band characteristic fusion technology, and meanwhile, the PID controller is combined with the fuzzy rule base inference engine, so that a response can be quickly made under the condition that the temperature is quickly changed, and the response capability is greatly improved.

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

A semiconductor package includes semiconductor chips each including at least one of a front insulating layer or a rear insulating layer, the semiconductor chips bonded to each other through direct bonding between the front insulating layer and the rear insulating layer. At least one of the semiconductor chips includes a device layer including an interconnection structure, and a conductive pattern on a front surface of the device layer. The conductive pattern includes pad patterns electrically connected to the interconnection structure, and a dummy pattern spaced apart from the pad patterns. The dummy pattern includes first dummy patterns between the pad patterns to overlap the pad patterns in a first direction, and a second dummy patterns between the first dummy patterns to overlap the pad patterns in the second direction. The second dummy patterns are spaced apart from the first dummy patterns.

The present invention relates to the technical field of semiconductor chip production, and provides a chip production simulation method and system based on digital twin technology. The method comprises: collecting a processing task of a target chip and retrieving a corresponding test data set; constructing a corresponding design parameter domain and design function; performing optimization, using digital twin technology to construct a twin chip, testing the twin chip, and calculating the design fitness; performing iterative optimization to acquire an optimal design parameter; constructing an optimal twin chip, calculating the similarity between the optimal twin chip and the existing family chips, and performing verification; and carrying out design and production of the target chip. The technical problems of incapability of considering possible hardware faults and anomalies, and incapability of guaranteeing the performance and reliability of the chip due to the uncertainty of the chip production process are solved. More accurate simulation and prediction are carried out on the chip design, and potential hazards are repaired in advance. Moreover, a more detailed and accurate simulation result is provided, so that the technical effects of improving the design efficiency, reducing the costs, and improving the performance and reliability of the chip are achieved.

The invention discloses an intelligent sealing test method and system for a wafer in a semiconductor chip, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: initializing a magneto-electric field cooperation parameter, optimizing the magneto-electric field cooperation parameter through a multi-target genetic algorithm, and driving core-shell nanoparticles to carry out the metallization filling of a high-precision through hole wafer, generating a wafer with a metalized through hole structure; based on the metalized through hole structure wafer, bonding parameters are generated through a laser Doppler frequency vibration spectrum analysis method, flip interconnection is achieved through a thermal ultrasonic virtual process, and a low-defect bonding wafer is generated; a finite element inversion algorithm is adopted, a stress distribution map of a bonding interface is established, an anti-thermal-stress packaging layer is constructed through an intelligent stress matching algorithm, and the low-defect bonding wafer is packaged; and through a multi-target genetic algorithm, magnetoelectric field cooperation parameters are optimized, core-shell nano-particles are driven to directionally deposit, and accurate control over the metallization filling process is achieved.

The invention relates to the technical field of chip optical detection, and discloses a high-precision defect detection method and system for a semiconductor chip. Initial detection data are obtained through laser scattering and photo-thermal microscopic detection, key visual features are extracted and converted into a multi-dimensional visual feature matrix, and the multi-dimensional visual feature matrix is used for detecting the defects of the semiconductor chip; according to the method, a fuzzy sensing area is positioned and potential defects are identified by using a map clustering algorithm, adaptive analysis of a supplementary visual angle is carried out and supplementary detection data is generated, and finally defect identification is carried out through the supplementary data and popularity information to obtain a chip defect result. The method effectively improves the precision and reliability of defect detection, especially has obvious advantages in recognition of complex and fuzzy regions, and solves the problem of insufficient precision of single-path optical imaging detection in the prior art.

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

The invention provides a semiconductor chip automatic test optimization system, and belongs to the technical field of electrical variable measurement. Comprising an acquisition module used for establishing an electrical variable time sequence arranged according to a time sequence, a drift analysis module used for calculating a short-time fluctuation amplitude value, a long-term drift slope and a high-frequency noise amplitude value based on the impedance time sequence arranged according to the time sequence, and a contact judgment module. The evaluation module is used for constructing a contact impedance coefficient based on a short-time fluctuation amplitude value, a long-term drift slope and a high-frequency noise amplitude value in a jth sliding window, and evaluating and optimizing the contact impedance coefficient, and the data marking module is used for marking electrical variable measurement data corresponding to a test channel which is evaluated to be instable in contact as low confidence. According to the system, the ith test channel of the temperature sensor chip can be tested more accurately, the short-time fluctuation amplitude value, the long-term drift slope and the high-frequency noise amplitude value are calculated at the same time, multi-source data participates, and the test accuracy is improved.

The invention discloses a chip mounting device for semiconductor chip processing, and relates to the field of semiconductor chip processing, the chip mounting device comprises a workbench and a support, the workbench is provided with a material box, the support is fixed on the workbench, and a gluing mechanism is fixed on the support. According to the chip mounting device for semiconductor chip processing, an automatic gluing structure is adopted, the continuous and automatic gluing effect of a chip can be achieved, specifically, a first air cylinder drives a positioning disc to move downwards, after the positioning disc is attached to the chip, the first air cylinder continues to stretch, and a material barrel and a gluing plate can move in cooperation with the action of a connecting rod and a sliding block; and in the gluing process, in cooperation with the effects of the piston, the cylinder, the air inlet one-way valve on the cylinder and the air outlet one-way valve on the cylinder, air in the cylinder enters the charging barrel, the glue in the charging barrel can be discharged more easily by increasing the air pressure in the charging barrel, and normal gluing is guaranteed.

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

A semiconductor includes a first semiconductor chip, and a second semiconductor chip provided on the first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate including a first front side and a first back side, and a first back-side bonding layer including a first back-side bonding insulating film, and a first back-side bonding pad, wherein the second semiconductor chip includes a second semiconductor substrate including a second front side that faces the first back side and a second back side, and a second front-side bonding layer including a second front-side bonding insulating film bonded to the first back-side bonding insulating film. A side of the first semiconductor chip includes a plurality of first recesses, which are arranged along a vertical direction, and a second recess, which partially exposes a bottom surface of the second front-side bonding layer between the second front-side bonding layer and the first recesses.

A semiconductor structure includes system-on-integrated chips, a first redistribution circuit structure and first conductive terminals. The system-on-integrated chips each include a die stack having two or more than two tiers, and each tier includes at least one semiconductor die. The first redistribution circuit structure is located on and electrically connected to the system-on-integrated chips. The first conductive terminals are connected on the first redistribution circuit structure, where the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive terminals.

The invention provides a semiconductor chip defect detection positioning method and system, and relates to the technical field of semiconductor chip detection, and the method comprises the steps: obtaining an original image and electrical test data; forming a defect candidate area based on local density analysis; variational mode decomposition is carried out on the electrical data, and electrical characteristic abnormal points are marked; mapping the image features to an electrical characteristic space and calculating mutual information values to determine defect points; and calculating the distribution and path of a diffusion field and determining the severity of the defect. According to the invention, accurate positioning and severity evaluation of chip defects are realized, and the detection efficiency and accuracy are improved.

The present disclosure relates to a MEMS inertial sensor device in a semiconductor chip package that includes an integrated circuit configured to process inertial sensor data. Preferred implementations utilize inertial sensors having different sensitivity ranges to adjust operation of dynamic system control such as motion and or attitude control of autonomous vehicles.

The invention provides a semiconductor chip packaging device and packaging technology, and belongs to the technical field of semiconductor chip packaging. The semiconductor chip packaging device comprises a supporting frame, an upper die and a lower die are arranged on the supporting frame, a packaging mechanism is arranged on the supporting frame, the packaging mechanism comprises two fixing bases, a reversing valve and a first air pipe, and the two fixing bases are fixedly installed on the opposite sides of the upper die and the lower die respectively. The packaging mechanism is arranged, gas is injected into an upper mold and a lower mold through a first gas pipe at the same time, and two first piston plates move relatively, so that epoxy resin in the upper mold and the lower mold is compacted, packaging of the epoxy resin is more uniform, and the protection effect is better after the epoxy resin is solidified; compared with the prior art, the packaging effect is better, compression is not needed after a large amount of epoxy resin is added, and the cost is saved.

The invention discloses a method and system for testing the electrical performance of a semiconductor chip, and the method comprises the steps: building a mapping relation between dielectric loss and loss frequency through obtaining the dielectric loss data, internal material characteristics and dynamic load power factors of the chip under each frequency band, recognizing a loss abnormal region, and analyzing the influence of the loss abnormal region on the performance of the chip; correcting test data by adopting a minimum mean square error algorithm, and optimizing the impedance of the power supply network and the dynamic switching characteristic of a functional module; calculating the breakdown voltage distribution of each layer in the chip, identifying a high-voltage risk region, optimizing the voltage distribution by using a gradient descent algorithm, and dynamically adjusting the working voltage and current; power factor fluctuation is analyzed through a sliding window algorithm, an abnormal area is identified, a power factor is optimized through a PID algorithm, and the working state and transient response of a chip in a dynamic load are improved. According to the method, the problems of nonlinearity of high-frequency dielectric loss, non-uniform breakdown voltage distribution and unstable power factor response under a dynamic load are solved, and comprehensive and accurate evaluation and optimization of chip performance are realized.

A described example includes: a leadframe having a high voltage section and a low voltage section spaced from and electrically isolated from the high voltage section, and a heat slug mounted to the high voltage section. The high voltage section includes an input portion connected to the heat slug at an interior end by a mount portion, and further includes an interior lead portion that is connected to the mount portion by a flexible connect portion. An insulating material mounted to the heat slug provides a die mount area for a semiconductor die having a Hall element that is positioned so that the Hall element is proximate to the heat slug. Mold compound covers the semiconductor die, portions of the leadframe, and portions of the heat slug while a board side surface of the heat slug is exposed forming a thermal pad for a semiconductor device package.

The invention relates to the technical field of semiconductor chips, in particular to a semiconductor chip flushing device and a cleaning method thereof.The semiconductor chip flushing device comprises a cleaning table, a cleaning frame is arranged on the inner wall of the middle of the cleaning table, the cleaning table comprises a cleaning water recycling box, and the rear side of the cleaning water recycling box is fixedly connected with a U-shaped vertical plate; according to the wafer cleaning device, the cleaning table and the cleaning frame are arranged, rapid cleaning of wafers is achieved, one wafer is flushed while the other wafer is pre-flushed through circulating water, the cleaning efficiency is effectively improved, the cleanliness of the surfaces of the wafers is ensured, in addition, the cleaning efficiency is improved, and the cleaning efficiency is improved. According to the device, through the design of the transmission mechanism, the orientation of the wafer is rapidly switched, the overall working efficiency is further improved, meanwhile, through the recycling design of cleaning water, water resources are saved, the production cost is reduced, and the concept of green production is met.

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

A semiconductor module includes a plurality of memory chips in a memory cube are stacked along a first direction parallel to a plane formed by a second direction and a third direction perpendicular to the first direction. The memory cube includes first and third outermost surfaces in the third direction and second and fourth outermost surfaces in the second direction. Each of the memory chips includes a substrate and a wiring layer. The substrate includes first to fourth side surfaces along each of the first to fourth outermost surfaces. A first insulating film is included between the first to fourth outermost surfaces and the corresponding first to fourth side surfaces. Internal wirings included in the wiring layer are connected to electrodes provided on at least one of the second to fourth outermost surfaces. The memory cube is spaced apart from the semiconductor chips and performs signal transmission.

MEMS device (100), having the following features: at least one touch sensor element (120, 1201-1204) configured to detect a touch (124) piezoelectrically, capacitively, optically, or magnetically; and at least one proximity sensor element (130, 1301-1304) configured to detect an object (200) spaced from the proximity sensor element (130, 1301-1304) with sound (190, 191, 192); wherein the at least one touch sensor element (120, 1201-1204) and the at least one proximity sensor element (130, 1301-1304) are integrated on a semiconductor chip (110); wherein the at least one touch sensor element (120, 1201-1204) comprises a plate (142) defining a recess (140) in an insulator (114) and configured to be bent upon contact; and wherein the at least one touch sensor element (120, 1201-1204) is designed to detect a bending of the plate (142) caused by a touch piezoelectrically, capacitively, optically or magnetically, wherein the MEMS device (100) is configured to determine a force of contact based on a magnitude of the bending.

An integrated circuit semiconductor chip is arranged on a substrate having electrically conductive leads and laser direct structuring (LDS) encapsulation material is molded onto the semiconductor chip. In response to LDS processing applied to the LDS encapsulation material molded onto the semiconductor chip, a pattern of electrically conductive formations is provided coupled to selected ones of the electrically conductive leads. Electrically conductive material is provided onto the pattern of electrically conductive formations and one or more planar electrically conductive clips are mounted onto the electrically conductive material. The clip or clips is / are electrically coupled via the electrically conductive material to selected ones of the electrically conductive leads. Further encapsulation material can be molded onto the electrically conductive clip or clips.

The invention provides an intelligent semiconductor chip and a thermal management method thereof, and the method comprises the steps: extracting the gradient features of the interlayer temperature of each semiconductor chip from the temperature information of each barrier layer of a three-dimensional stacked chip in a high-power-consumption module under a current working condition; constructing a temperature coupling field of the high-power-consumption module in the current working condition through each gradient feature and the heat dissipation feature of the packaging layer; a plurality of heat flux concentration areas of the high-power-consumption module in the current working condition are positioned based on the temperature coupling field and the specified sampling frequency, and thermal runaway risk points in the high-power-consumption module are screened out from all the heat flux concentration areas through peak characteristics in junction temperature information of all the heat flux concentration areas; and determining the vector distribution characteristics of the heat flux density in each thermal runaway risk point, and performing layered heat dissipation on the three-dimensional stacked chip in the high-power-consumption module through the vector distribution characteristics of the heat flux density in each thermal runaway risk point. Based on the scheme, thermal field reconstruction of dynamic thermal management in the three-dimensional stacked chip can be realized.

The invention discloses a semiconductor packaging structure and a forming method thereof, and the method comprises the steps: providing a glass substrate which is provided with a plurality of discrete glass through hole interconnection structures, and is also provided with a groove located in the upper surface; a semiconductor chip without internal wiring is provided, the semiconductor chip comprises a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, and a semiconductor device is arranged in the device layer; mounting a semiconductor chip without internal wiring into the groove; an inorganic dielectric layer and a first interconnection structure and a second interconnection structure which are located in the inorganic dielectric layer are formed on the upper surface of the glass substrate, the first interconnection structure is electrically connected with the upper end surface of the glass through hole interconnection structure, and the second interconnection structure is electrically connected with the semiconductor device. The semiconductor chip without internal wiring, the second interconnection structure and a part of the inorganic dielectric layer form a first semiconductor chip; and forming an organic passivation layer and a third interconnection structure located in the organic passivation layer on the lower surface of the glass substrate. And the performance of the packaging structure is improved.

A semiconductor die includes an on-die power switch and a target device. The on-die power switch includes a plurality of power input nodes, a power output node, and a switch circuit. The power input nodes receive a plurality of operation voltages from a plurality of different power sources, respectively. The power output node outputs a target operation voltage selected from the operation voltages. The switch circuit selectively couples one of the power input nodes to the power output node. The target device operates according to the target operation voltage supplied from the on-die power switch. The on-die power switch and the target device are separate circuit blocks of the semiconductor die.