3868 results about "Semiconductor chip" patented technology

The invention discloses an intelligent sealing test method and system for a wafer in a semiconductor chip, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: initializing a magneto-electric field cooperation parameter, optimizing the magneto-electric field cooperation parameter through a multi-target genetic algorithm, and driving core-shell nanoparticles to carry out the metallization filling of a high-precision through hole wafer, generating a wafer with a metalized through hole structure; based on the metalized through hole structure wafer, bonding parameters are generated through a laser Doppler frequency vibration spectrum analysis method, flip interconnection is achieved through a thermal ultrasonic virtual process, and a low-defect bonding wafer is generated; a finite element inversion algorithm is adopted, a stress distribution map of a bonding interface is established, an anti-thermal-stress packaging layer is constructed through an intelligent stress matching algorithm, and the low-defect bonding wafer is packaged; and through a multi-target genetic algorithm, magnetoelectric field cooperation parameters are optimized, core-shell nano-particles are driven to directionally deposit, and accurate control over the metallization filling process is achieved.

The invention provides a semiconductor chip automatic test optimization system, and belongs to the technical field of electrical variable measurement. Comprising an acquisition module used for establishing an electrical variable time sequence arranged according to a time sequence, a drift analysis module used for calculating a short-time fluctuation amplitude value, a long-term drift slope and a high-frequency noise amplitude value based on the impedance time sequence arranged according to the time sequence, and a contact judgment module. The evaluation module is used for constructing a contact impedance coefficient based on a short-time fluctuation amplitude value, a long-term drift slope and a high-frequency noise amplitude value in a jth sliding window, and evaluating and optimizing the contact impedance coefficient, and the data marking module is used for marking electrical variable measurement data corresponding to a test channel which is evaluated to be instable in contact as low confidence. According to the system, the ith test channel of the temperature sensor chip can be tested more accurately, the short-time fluctuation amplitude value, the long-term drift slope and the high-frequency noise amplitude value are calculated at the same time, multi-source data participates, and the test accuracy is improved.

The invention provides a semiconductor chip defect detection positioning method and system, and relates to the technical field of semiconductor chip detection, and the method comprises the steps: obtaining an original image and electrical test data; forming a defect candidate area based on local density analysis; variational mode decomposition is carried out on the electrical data, and electrical characteristic abnormal points are marked; mapping the image features to an electrical characteristic space and calculating mutual information values to determine defect points; and calculating the distribution and path of a diffusion field and determining the severity of the defect. According to the invention, accurate positioning and severity evaluation of chip defects are realized, and the detection efficiency and accuracy are improved.

The invention discloses a semiconductor chip, a preparation method of a metal interconnection layer and the metal interconnection layer. The semiconductor chip comprises a semiconductor substrate, and a plurality of device structures are formed on the semiconductor substrate; the metal interconnection layer is located above the semiconductor substrate and used for connecting a plurality of device structures, and the metal interconnection layer at least comprises a first titanium layer located above the semiconductor substrate, a second titanium layer located above the semiconductor substrate and a third titanium layer located above the semiconductor substrate; a first titanium nitride layer over the first titanium layer; a metal layer over the first titanium nitride layer; the at least two groups of composite barrier layers are positioned above the metal layer; each group of composite barrier layers comprises a second titanium layer and a second titanium nitride layer located above the second titanium layer; the thickness of the second titanium nitride layer in each group of composite barrier layers is smaller than a first preset thickness; and the sum of the thicknesses of the second titanium nitride layers in each group of composite barrier layers is equal to or greater than a second preset thickness. According to the semiconductor chip, the metal residue defect on the surface of the semiconductor substrate is reduced while the thickness requirement is met.

A semiconductor package has a first semiconductor package which includes a first redistribution structure, a first semiconductor chip on a lower surface of the first redistribution structure, a first encapsulant on at least a portion of the first semiconductor chip, a second redistribution structure on the first encapsulant, and a conductive post electrically connecting the first redistribution structure and the second redistribution structure through the first encapsulant; and a second semiconductor package which is on an upper surface of the first redistribution structure and comprises a third redistribution structure, a second semiconductor chip on the third redistribution structure, and a second encapsulant on at least a portion of the second semiconductor chip, wherein the first encapsulant integrally covers each of a lower surface and a side surface of the first semiconductor chip.

A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.

A bonded assembly includes a first semiconductor die containing first semiconductor devices and a first bonding pad embedded within a first silicon oxide layer, where the first bonding pad includes a first copper containing portion, a second semiconductor die containing second semiconductor devices and a second bonding pad that is embedded within a second silicon oxide layer and is bonded to the first bonding pad via metal-to-metal bonding, where the second bonding pad includes a second copper containing portion, and at least one metal silicon oxide layer interposed between the first bonding pad and the second silicon oxide layer. In one embodiment, the at least one metal silicon oxide layer is a manganese silicon oxide layer.

The invention provides a memory, an operation method of the memory and a memory system, and relates to the technical field of semiconductor chips. The memory comprises a memory array and a peripheral circuit coupled to the memory array, the memory array comprises memory blocks, and the memory blocks are coupled to the peripheral circuit through word lines. Wherein the storage block comprises a programmed storage unit and an unprogrammed storage unit, and the programmed storage unit comprises a first storage unit and a second storage unit. The peripheral circuit is configured to: perform a program operation on a third memory cell in the memory block, and apply a first voltage to a first word line coupled to the first memory cell at a first stage of a channel preparation stage of the program operation; and applying a second voltage to a second word line coupled to the second memory cell. Wherein the first word line is located between a third word line coupled with the third storage unit and the second word line, and the first voltage is larger than the second voltage.

The invention discloses a semiconductor structure, a semiconductor device and a preparation method of a semiconductor, and the semiconductor structure comprises a wafer which is divided into a plurality of semiconductor chip regions and a cutting channel region located between two adjacent semiconductor chips; the closed ring structure is arranged between the chip area and the cutting channel area; the cutting channel region is fully paved with the metal cushion layer, and the metal cushion layer is located on the side, close to the wafer, of the cutting channel region; and the pseudo-closed ring structure fills the cutting channel region and is arranged on the metal cushion layer. The low dielectric material or the silicon oxide material in the cutting channel region is divided into a plurality of small blocks by the metal cushion layer and the pseudo closed ring structure, so that the chip and the closed ring structure can be effectively prevented from being damaged in the wafer cutting process.

Provided is a semiconductor package including a three-dimensional (3D) stacked structure in which an upper second semiconductor chip is stacked on a lower first semiconductor chip. In the semiconductor package, a power distribution network for the first semiconductor chip and a power distribution network for the second semiconductor chip are implemented through circuits of the first semiconductor chip and separated from the first semiconductor chip.

A system includes: an inverter configured to convert DC power to AC power, wherein the inverter includes: a power module including: a first substrate, a second substrate including a source plane and a gate plane separated from the source plane by a full trench, the source plane including a step trench, and the gate plane including an electrical connection through the second substrate to a gate input connection of the power module, a semiconductor die disposed between the first substrate and the second substrate, the step trench formed in a portion of the source plane corresponding to an edge of the semiconductor die, and the semiconductor die including a gate connected to the gate plane, and a sinter element disposed between the semiconductor die and the second substrate to connect the semiconductor die to the second substrate; a battery; and a motor.

The invention discloses a power consumption evaluation method for an electric energy metering chip, relates to the technical field of semiconductor chips, and solves the technical problem of power consumption evaluation for the electric energy metering chip. The method comprises the following steps: selecting instruments and equipment according to the electrical characteristics of the electric energy metering chip, building a test circuit according to the selected instruments and equipment, a circuit is built according to a static condition given by an electric energy metering chip manual to measure static power consumption, data of voltage and current of the electric energy metering chip in different working modes along with time change is recorded by data acquisition equipment to measure dynamic power consumption, and data analysis is performed by a comparative analysis method. And the power consumption change of the electric energy metering chip during dynamic metering, different loads and switching of multiple working modes can be calculated in time. And the power consumption evaluation capability of the electric energy metering chip is improved.

A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

One example includes a method for fabricating an integrated circuit (IC) device. The method includes fabricating a semiconductor die comprising a metal top (METTOP) structure and forming a barrier layer over the METTOP structure to cover approximately the entirety of the METTOP structure. The method also includes forming a polyimide (PI) layer over the semiconductor die and over a portion of the barrier layer to form a gap that exposes the barrier layer through the PI layer. The method further includes forming a conductive post in the gap over the barrier layer.

A semiconductor package may include a package substrate, a first interposer on the package substrate, a first semiconductor chip and a second semiconductor chip that are on the first interposer, a second interposer on the first semiconductor chip, a third semiconductor chip on the second interposer, and a first through via that extends into the first semiconductor chip and is between the first interposer and the second interposer.

A method for forming a semiconductor package includes providing a semiconductor chip containing a bond pad located on a top surface of the semiconductor chip, providing a carrier including a chip mounting pad and a landing pad, mounting the semiconductor chip onto the chip mounting pad with the bond pad facing away from the carrier, and attaching an electrical connecting element between the bond pad and the landing pad, wherein the bond pad is formed from nanowires.

A system includes a plurality of semiconductor chips that are stacked on top of each other and that include first and second semiconductor chips. The first semiconductor chip includes a clock signal generating circuit, a transmitting circuit, and a receiving circuit. The clock signal generating circuit generates a clock signal and a delayed version of the clock signal. The transmitting circuit transmits a first data signal in response to the clock signal. The receiving circuit receives a second data signal in response to the delayed version of the clock signal. For example, the receiving circuit receives the delayed version of the clock signal at substantially the same time that the transmitting circuit receives the clock signal.

A semiconductor package includes a first redistribution circuit structure, a semiconductor die, and an electrically conductive structure. The semiconductor die is disposed over and electrically coupled to the first redistribution circuit structure. The electrically conductive structure connects a non-active side of the semiconductor die to a conductive feature of the first redistribution circuit structure, where the semiconductor die is thermally coupled to the first redistribution circuit structure through the electrically conductive structure, and the electrically conductive structure includes a structure of multi-layer with different materials.

A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.

A device package and heatsink assembly includes a device package containing one or more logic elements and one or more other integrated circuit devices mounted to a package substrate and one or more heatsinks. The other integrated circuit devices are higher above the package substrate's surface than the logic elements. Each heatsink contains chambers for a fluid heat transfer medium. A surface of the logic elements is thermally coupled to the fluid. A semiconductor chip package fabrication method includes bonding a diamond-containing dielet to a semiconductor logic die to form a logic die structure; mounting the logic die structure to a package substrate with the logic die sandwiched between the dielet and the substrate, exposing a surface of the dielet; and mounting one or more other integrated circuit devices to the package substrate. The other integrated circuit devices are higher above the package substrate's surface than the logic die structure.

The invention relates to the technical field of defect detection, in particular to a semiconductor chip surface defect detection method based on deep adversarial supervision, which comprises the following steps: acquiring a chip surface image, and inputting a pre-constructed defect detection model to obtain a defect segmentation result of the chip surface image; the defect detection model comprises an encoder, a decoder and a discriminator; the encoder is used for extracting multi-scale features of the chip surface image; the decoder is used for recovering the spatial resolution of the image layer by layer based on the multi-scale features and outputting a defect segmentation result of a corresponding scale; the discriminator is used for discriminating the difference between the defect segmentation result output by the decoder at the corresponding scale and the real label image at the corresponding scale; the method comprises the following steps: updating parameters of an encoder and a decoder by calculating semantic segmentation loss; and then adversarial training is carried out in combination with the discrimination result of the discriminator, and the parameters of the encoder, the decoder and the discriminator are jointly optimized, so that iterative updating of the parameters of the defect detection model is realized. The defect detection precision can be improved.

A semiconductor device semiconductor chip mounted to a leadframe that includes an electrically conductive pad. An electrically conductive clip is arranged in a bridge-like position between the semiconductor chip and the electrically conductive pad. The electrically conductive clip is soldered to the semiconductor chip and to the electrically conductive pad via soldering material applied at coupling surfaces facing towards the semiconductor chip and the electrically conductive pad. The device further includes a pair of complementary positioning formations formed by a cavity in the electrically conductive clip and a protrusion (such as a stud bump or a stack of stud bumps) formed in the electrically conductive pad. The complementary positioning formations are mutually engaged to retain the electrically conductive clip in the bridge-like position to avoid displacement during soldering.

A semiconductor package includes first and second semiconductor dies on a buffer die. The first semiconductor die includes first memory blocks on a first semiconductor substrate, a first interlayer dielectric layer, a first through via penetrating the first semiconductor substrate and connected to the buffer die, and first conductive pads on the first interlayer dielectric layer and connected to the first memory blocks. The second semiconductor die includes first calculation blocks on a second semiconductor substrate and configured to calculate data received from the first memory blocks and store results to the first memory blocks, a second interlayer dielectric layer, and second conductive pads below the second interlayer dielectric layer and connected to the first calculation blocks. A top surface of the first interlayer dielectric layer contacts the second interlayer dielectric layer. The first conductive pads contact the second conductive pads.

An electronic module is provided that includes a microchannel cooler having a glass manifold contacting a first side of a microchannel chip, a plurality of functional semiconductor chips located face up on a second side of the microchannel chip. Each semiconductor chip of the plurality of functional semiconductor chips is coefficient of thermal expansion (CTE) matched, and a first redistribution layer (RDL) containing structure or organic interposer is located above and in electrical contact with the plurality of functional semiconductor chips. In either case, the first RDL containing structure and the organic imposer are not CTE matched to the functional semiconductor chips.

The invention belongs to but not limited to the technical field of power semiconductor packaging, and discloses a packaging structure of a power semiconductor device. The power module comprises a lead frame, a plastic package body, a base island, a bonding wire and a semiconductor chip assembly, a first power unit and a second power unit are integrated, the first unit comprises two driving ICs, six IGBTs and six FRD chips, the second unit comprises two driving ICs and six MOS chips, 46 pins are provided, and functions are clearly divided. All the IC chips and the FRD chips are arranged on the same base island, the back faces of the chips are welded to the base island, and the front faces of the chips are connected with pins in a standard mode through bonding wires. The structure solves the problems of complex packaging layout, disordered connection and the like in the prior art, can drive the compressor and the fan respectively, realizes high integration level and compact layout, shortens an electric connection path, reduces parasitic parameters, reduces the overall size and cost, and improves reliability and engineering compatibility.

Apparatus and methods for power amplifiers with broadband matching networks are disclosed. In certain embodiments, a mobile device includes a transceiver that generates a radio frequency input signal, and a front-end system including a compound semiconductor die and a silicon switch die. The compound semiconductor die includes a power amplifier including one or more power amplifier stages that amplify the radio frequency input signal to generate a radio frequency output signal. The silicon switch die includes a band selection switch that receives the radio frequency output signal. The compound semiconductor die and the silicon switch die each include at least one controllable impedance for providing a bandwidth adjustment to the power amplifier.

The invention discloses a discrete device packaging structure based on direct lead bonding, which belongs to the technical field of semiconductor device packaging and comprises a power semiconductor chip, a drain metal substrate, a grid lead terminal, a drain lead terminal, a bonding wire and a supporting shell. The drain electrode metal substrate is connected with the lower surface of the power semiconductor chip through solder. The gate metal electrode on the upper surface of the power semiconductor chip is connected with the gate lead terminal through a bonding wire, and the source metal electrode on the upper surface of the power semiconductor chip is connected with the source lead terminal through solder. The interior of the supporting shell is filled with silica gel or an injection molding process, and the supporting shell covers the power semiconductor chip to serve as an insulating medium. The power density of the device is improved, the parasitic parameter of the whole device is reduced, and the reliability of the interconnection structure is improved.

Provided is a ranging device capable of suppressing an electric power loss and a decrease in an SNR at low cost.A ranging device of the present disclosure includes a photonic circuit and an electric circuit on the same semiconductor chip, the photonic circuit including: a light source; a waveguide that guides light from the light source; an optical switch distribution network that distributes first light split from the light; a grating array that outputs the first light distributed by the optical switch distribution network to an external target and receives the first light reflected from the target as reflected light; a first coupler that combines the reflected light with second light split from the light; and a first photodiode that photoelectrically converts light combined by the first coupler into a first electric signal, and the electric circuit including: a power supply that supplies electric power to the light source and the optical switch distribution network; and a controller that controls the power supply.

The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. In particular, the disclosure relates to a semiconductor power packaging including the semiconductor device. It is a goal of the present disclosure to provide a method for manufacturing a semiconductor device without an insulation layer as a support layer for semiconductor dies thereby enhancing thermal and electrical performance as well as such a semiconductor device.

An electronic device includes a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate has first, second, and third levels including respective dielectric layers and conductive features, the first level including a first trace layer with an antenna and a first via layer with a portion of a ground wall laterally spaced outward from and surrounding the antenna, and the second level including a second trace layer having a ground plane connected to the ground wall, the semiconductor die attached to the first level of the multilevel package substrate, and the package structure including a molding compound enclosing the semiconductor die and extending on a side of the antenna, where the package structure mold compound maters and thickness can be tuned for improved performance.