3005results about "Semiconductor/solid-state device testing/measurement" patented technology

An object of the invention is to provide a probe card capable of properly performing a measurement. A probe card according to the invention includes: probes 100 shaped to allow vertical elastic deformation; a supporting substrate 200 with the probes provided on the lower surface thereof; a main substrate 300 positioned opposing the upper surface of the supporting substrate 200; an intermediate substrate 400 disposed between the supporting substrate 200 and main substrate 300; a supporting member 500 that is a column-shaped member with one end thereof attached to the center of the supporting substrate 200 and the other end thereof attached to the intermediate substrate 400 and holds the supporting substrate 200 so that the supporting substrate 200 is inclinable; and elastic members for holding the supporting substrate 200 so that the supporting substrate 200 is in a horizontal position relative to the main substrate 300, which are provided between the supporting substrate 200 and main substrate 300.

The invention discloses an intelligent sealing test method and system for a wafer in a semiconductor chip, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: initializing a magneto-electric field cooperation parameter, optimizing the magneto-electric field cooperation parameter through a multi-target genetic algorithm, and driving core-shell nanoparticles to carry out the metallization filling of a high-precision through hole wafer, generating a wafer with a metalized through hole structure; based on the metalized through hole structure wafer, bonding parameters are generated through a laser Doppler frequency vibration spectrum analysis method, flip interconnection is achieved through a thermal ultrasonic virtual process, and a low-defect bonding wafer is generated; a finite element inversion algorithm is adopted, a stress distribution map of a bonding interface is established, an anti-thermal-stress packaging layer is constructed through an intelligent stress matching algorithm, and the low-defect bonding wafer is packaged; and through a multi-target genetic algorithm, magnetoelectric field cooperation parameters are optimized, core-shell nano-particles are driven to directionally deposit, and accurate control over the metallization filling process is achieved.

The present disclosure provides an automated die bonding of LED substrates system in which an automated die bonding inspection module is used to determine the quality of incoming processing material and an automated die bonding process module is used to process the processing material, an automated die bonding post-process module is used to inspect the resultant process material for acceptability, and an automated die bonding historical module is used to analyze the post process results of the most recent process, against all historical data to find enhanced process changes in the automated die bonding process module and an automated die bonding integration module to update the automated die bonding process module based upon the results of the automated die bonding historical module.

The invention relates to the technical field of interconnection testing, in particular to an electrical performance and defect synchronous testing system of a CoWoS packaging TSV interconnection structure, which comprises a signal sorting module, a defect positioning module, a partition classification module, a hot area distribution positioning module and a load evaluation module. According to the method, through real-time monitoring and collection of the multi-source signals, the dynamic state of the key node in the TSV interconnection structure can be efficiently extracted and analyzed, the limitation of traditional single-point testing is broken through, abnormal fluctuation is accurately detected, a defect area is rapidly positioned, the recognition capability of electrical abnormity in the micro interconnection structure is improved, and the detection accuracy is improved. The device operation state and the load problem can be calibrated, the reliability of the packaging structure is optimized, the monitoring accuracy of the electrical performance of the complex interconnection structure is remarkably improved, the global problem is prevented from being missed, electrical anomalies of different hierarchies and regions are covered, the effectiveness of defect identification and fault prediction is enhanced, the detection efficiency and accuracy are improved, and the reliability of the packaging structure is improved. And the risks of missing detection and misjudgment are reduced.

The invention discloses an image taking control method and device, equipment, a storage medium and a product, and relates to the technical field of wafer image taking, and the image taking control method comprises the steps: transferring a wafer to be subjected to image taking, of which the center alignment is completed at a wafer edge finder, to a defect detection platform through a wafer conveying fork; and in different target light fields, through different types of cameras in a preset visual range, preset coordinates are traversed on the defect detection platform, shooting is carried out in sequence, defect images are obtained, the target light fields comprise a bright field, a dark field and a PL field, and the defect images comprise surface defect features, scratch features and growth defect features. According to the method and the device, the wafer surface defects and the growth defects of the deep layer of the wafer can be shot, the scratch features can also be shot, relatively comprehensive defect features can be covered, and the image quality of the shot defect image is improved.

The invention provides a cutting height adjusting method and device of a cutting knife, wafer processing equipment and a medium, and relates to the technical field of wafer processing equipment.The method comprises the steps that the surface height difference between a sample silicon wafer on an auxiliary workbench and a to-be-processed wafer on a main working disc is measured; after the cutting knife cuts the sample silicon wafer to form a cutting mark, calculating a cutting depth value corresponding to the cutting mark; calculating the surface height information of the sample silicon wafer according to the cutting depth value of the cutting mark and the height information corresponding to the lowest point of the cutting knife when the cutting knife cuts the sample silicon wafer on the auxiliary workbench; and according to a preset cutting depth value, the surface height information of the sample silicon wafer and the surface height difference between the sample silicon wafer on the auxiliary workbench and the to-be-processed wafer, target cutting height information of the cutting knife when the cutting knife cuts the to-be-processed wafer is determined. After the height of the cutting knife is adjusted according to the target cutting height information, the cutting mark cut by the cutting knife has high-precision cutting depth.

The invention relates to the technical field of semiconductor manufacturing, provides a wafer dry etching control method and system, aims to monitor an etching process in real time and dynamically control the etching process with high precision, and comprises the following steps: step 1, monitoring etching equipment, and collecting an etching parameter combination of etching and image information of a wafer etching area; 2, constructing a real-time data processing model, developing a multi-objective optimization function, and inputting a target value into the multi-objective optimization function to obtain an initial etching parameter combination; 3, in the etching process, a predicted value of etching result data is obtained through the real-time data processing model, the predicted value is compared with a target value, and an etching parameter combination of etching is dynamically adjusted; and 4, constructing an end point prediction model, monitoring whether the image features of the etched image information reach a preset threshold value or not in real time by the end point prediction model, and if yes, sending an etching end point signal. In addition, the invention provides a semiconductor wafer high-precision dry etching control system.

The invention relates to a gallium oxide epitaxial layer prediction method and device, equipment and a medium, and the method comprises the steps: collecting the technological parameters of MOCVD and the characterization data of an epitaxial layer, and carrying out the data preprocessing, and obtaining the preprocessed data; performing feature derivation and feature screening on the preprocessed data, and performing data set division on the data after feature screening to generate a training data set and a test data set; constructing an XGBoost regression model, and performing hyper-parameter search to obtain a target optimal parameter combination so as to train the XGBoost regression model and generate a trained XGBoost regression model; testing the trained XGBoost regression model through the test data set to generate a target XGBoost regression model; to-be-measured process parameters of MOCVD are obtained, and epitaxial layer prediction is carried out on the to-be-measured process parameters to obtain the target epitaxial layer thickness and the target full width at half maximum variation. The prediction accuracy of the gallium oxide epitaxial layer is improved.

The invention relates to the technical field of wafer detection, in particular to semiconductor wafer cutting section defect detection equipment and a detection method, and the semiconductor wafer cutting section defect detection equipment comprises a detection shell and a conveying shell; a carrying table is arranged in the conveying shell, and a piece taking device, a camera, a spotlight, a first rotating ring, a support and a first driving unit are arranged in the detection shell. The pick-up device is arranged in the detection shell and used for taking out the semiconductor wafer on the carrying table, the moving direction of the carrying table serves as a rotation axis, the pick-up device can rotate around the rotation axis, and the rotation angle of each time is 180 degrees; the camera is arranged on one side of the pick-up device; the spotlight is of an annular structure and is arranged on the periphery of the camera in a surrounding and sleeving mode. The first rotating ring is rotationally arranged in the detection shell along the rotating axis; the support is fixedly arranged on the first rotating ring, and the camera is arranged on the support; the first driving unit is arranged on one side of the first rotating ring. According to the invention, the precision and reliability of double-sided detection of the semiconductor wafer are improved.

The invention belongs to the technical field of information, and particularly relates to an industrial robot semiconductor etching system based on intelligent regulation and control. Based on an etching precision control algorithm of multi-sensor fusion and real-time feedback, a Dempster-Shafer evidence theory is used for fusing multi-sensor data, and etching parameters are adjusted in real time in combination with sliding mode control, so that the chip etching size deviation is reduced to + / -1nm from + / -5nm of a traditional process, and the rejection rate is reduced to 5% from 15%. According to an etching uniformity optimization algorithm based on multi-physical field monitoring and adaptive adjustment, a multi-physical field model is constructed through multi-source information fusion, process parameters are optimized in real time by adopting model prediction control, the etching depth deviation is reduced to + / -5nm from + / -15nm, the chip yield is improved to 90% from 70%, and the etching precision and uniformity are remarkably improved.

A package device is provided and includes a substrate and a conductive element. The substrate includes a through hole, a first portion, and a second portion, wherein the through hole penetrates the first portion and the second portion, and a first thickness of the first portion is less than a second thickness of the second portion. The conductive element is disposed in the through hole, wherein the first portion of the substrate includes compressive stress, and the second portion of the substrate includes tensile stress.

An electronic device and a manufacturing method thereof are disclosed. The manufacturing method of the electronic device includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming a through hole penetrating the substrate, a side wall of the through hole connected with the first surface and the second surface; providing a first conductive layer on the substrate, the first conductive layer extending into the through hole; providing a second conductive layer on the first conductive layer, the second conductive layer extending into the through hole and having an original thickness; performing a thinning step to remove at least a portion of the second conductive layer; and performing an inspection step to obtain a first inspection result, and determining whether to continue subsequent steps according to the first inspection result.

This disclosure provides a wafer inspection apparatus and method, relating to the field of semiconductor manufacturing technology. The apparatus includes a base platform, a wafer stage movably disposed on the base platform, a front inspection device disposed above the wafer stage, and a back inspection device disposed below the wafer stage. The back inspection device includes a support portion supporting the wafer, within which a cavity is formed. The cavity is filled with a transparent liquid to wet the outer surface of the blue film on the back side of the wafer. This disclosure eliminates light scattering caused by the frosted texture of the blue film through transparent liquid wetting, and simultaneously prevents sagging by supporting the wafer with the support portion, achieving simultaneous front and back inspection without flipping the wafer. This solves the technical problems of blue film imaging obstacles and automated inspection failures in the prior art.

An electronic device and a manufacturing method thereof are provided. The electronic device includes a substrate, at least one electronic unit, an adhesive layer, an insulating layer, and a conductive structure. The substrate has at least one recess. The electronic unit is disposed in the recess, and the adhesive layer is disposed between the electronic unit and a bottom surface of the recess. The insulating layer is disposed on the electronic unit and the recess. The conductive structure is disposed on the insulating layer, and the conductive structure penetrates through the insulating layer to be electrically connected to the electronic unit.

The present disclosure provides an electronic device and a method for manufacturing the same. The electronic device includes a first transparent substrate, a conductive element, a circuit structure, and an electronic unit. The first transparent substrate has a plurality of through holes. The conductive element is disposed in at least one of the plurality of through holes, wherein the conductive element includes a first portion and a second portion surrounded by the second portion. The circuit structure is disposed on the first transparent substrate. The electronic unit is disposed on the circuit structure and is electrically connected to the conductive element through the circuit structure. The surface of the first portion of the conductive element has a plurality of recesses, and at least one portion of the second portion of the conductive element is disposed in at least one of the plurality of recesses.

The invention discloses a wafer scanning method and device and a storage medium. The method comprises the steps of obtaining the radius of a to-be-scanned wafer and the preset effective length of a linear light spot of a scanning camera; the wafer is divided into a first area and a second area based on the radius and the effective length of the linear light spot, the first area comprises an annular area with the radius value larger than a first preset radius threshold value, and the second area comprises a circular area with the radius value smaller than the first preset radius threshold value; controlling the scanning camera to perform spiral line scanning on the first area, and then performing back-and-forth scanning on the second area along a straight line until scanning is completed; according to the invention, the surface area of the wafer is divided into the annular first area and the circular second area, the first area is subjected to spiral line scanning to improve the scanning rate of the wafer, and then the second area is subjected to back-and-forth scanning to ensure that the position close to the center of the wafer is accurately scanned.

The invention discloses a wafer detection method and device and application thereof, and the method comprises the steps: obtaining first reference data to construct a first coordinate system, obtaining a position relation between a to-be-detected crystal grain and a template crystal grain, and obtaining a reference coordinate of the to-be-detected crystal grain based on the first reference data and the position relation, calculating the number of complete crystal grains under the maximum scanning field of view based on the maximum scanning field of view of image acquisition and the first reference data, setting the scanning field of view of image acquisition and the minimum moving step length based on the number of the complete crystal grains, and obtaining the initial position of image acquisition based on the reference coordinates of the crystal grains to be detected, and planning a scanning path of wafer detection in combination with the scanning view and the minimum moving step length. According to the method, the distribution condition of all the to-be-detected crystal grains on the wafer is obtained based on the coordinate information of the template crystal grains and the adjacent crystal grains, then the scanning view and the minimum moving step length of image acquisition are determined based on the proportional relation between the crystal grain size and the maximum size of the scanning view, and the scanning path is accurately planned to improve the detection efficiency.

The invention discloses a cleaning end point judgment method and system for a semiconductor process chamber, and the method comprises the following steps: obtaining optical parameters of characteristic gas generated in a cleaning process, carrying out the data processing of the optical parameters, and obtaining a normalized absorptivity A; acquiring an electrical parameter V of characteristic gas generated in the cleaning process; performing data processing on the optical parameter and the electrical parameter V to obtain an optical end point index, an optical weight, an electrical end point index and an electrical weight; obtaining a decision index S; setting a first threshold value of the normalized absorption rate A and a second threshold value of the decision index S; when the decision index S is continuously lower than the second threshold value, it is judged that cleaning is completed. The cleaning end point judgment system comprises a semiconductor cavity, a tail gas emission pipeline and a detection device. The detection device is arranged on the tail gas emission pipeline to detect the concentration of the characteristic gas in real time. According to the invention, the anti-interference capability in the detection process can be improved.

The invention provides a polishing method. A semiconductor structure comprises a substrate, and gettering layers are formed on the front face and the back face of the substrate at the same time. Obtaining the initial bending degree and the initial warping degree of the semiconductor structure; and executing at least one chemical mechanical polishing process, and after each chemical mechanical polishing process, obtaining the bending degree variation and the warping degree variation of the semiconductor structure in real time until the bending degree variation and the warping degree variation of the semiconductor structure reach the preset bending degree variation and the preset warping degree variation. According to the method, in the multiple chemical mechanical polishing technological processes, the removal degree of the front gettering layer of the substrate is judged by monitoring changes of the bending degree and the warping degree of the semiconductor structure. And when the bending variation and the warping variation of the semiconductor structure reach preset values, the front gettering layer of the substrate is completely removed, and in the step-by-step polishing process, the chemical mechanical polishing process is timely stopped according to real-time monitoring data calculation, so that the front gettering layer of the substrate is effectively removed, and the over-polished substrate is reduced.

The invention relates to a continuous preparation system and method for a perovskite photovoltaic glass substrate. The continuous preparation system comprises a feeding module, a transfer module, a slit coating machine module, a flash evaporation module, an annealing furnace module and a discharging module which are sequentially matched with one another from left to right. The invention provides a continuous preparation system and method of a perovskite photovoltaic glass substrate, which can realize automatic feeding, transfer, coating, transfer, flash evaporation and annealing of the glass substrate, and realize automatic butt joint with front and rear equipment; and continuous coating can be carried out, the production takt is accelerated, the production cycle of products is shortened, the stability and conversion efficiency of the products are improved, and the production cost is reduced.

The invention provides a method and a device for determining credibility of a wafer detection result, and belongs to the technical field of semiconductor manufacturing. The method comprises the steps that the target grade of a wafer to be detected is determined, the target grade is selected from a plurality of preset product grades, and different product grades correspond to different preset quality thresholds; multiple times of virtual measurement are carried out on the wafer to be measured, a predicted value set is obtained, and the predicted value set comprises predicted values corresponding to each time of virtual measurement; and determining a virtual measurement result and the credibility of the virtual measurement result based on the predicted value set and a preset quality threshold value corresponding to the target grade. The credibility is matched with the target grade, so that differential evaluation can be carried out according to different product grades, the detection requirements of wafers of different product grades are met, and the accuracy of virtual measurement result evaluation is improved.

A surface scanning tool and methods of using a surface scanning tool to determine a surface shape of a tool. In embodiments, the surface scanning tool includes a laser, a detector, and a signal analysis module. The laser sends a beam of light that is reflected off a bottom surface of the tool. The detector receives the reflected beam of light and sends the reflected beam of light signals to a signal analysis module. The signal analysis module determines a surface shape of the bottom surface and triggers mitigation actions. In alternative embodiments, the surface scanning tool includes a camera and a signal analysis module. The camera takes a picture of the bottom surface of the tool and sends the image to the signal analysis module. The signal analysis module determines the surface shape of the bottom surface and triggers mitigation actions.

The invention relates to the technical field of semiconductor etching, in particular to a semiconductor etching method based on plasma coordinated regulation, which comprises the following steps: alternately using first plasma and second plasma on a semiconductor to be etched to obtain a plurality of groove structures with a preset depth-to-width ratio, the second plasma is used for cleaning side wall residues; detecting by using a laser interference measurement method to obtain an etching rate ratio and a side wall angle corresponding to each groove structure, and determining corresponding treatment according to the change condition of the etching rate ratio and the side wall angle, including maintaining the etching and cleaning parameters of the current stage, or adjusting the corresponding parameters of the first plasma according to the need, or corresponding parameters of the second plasma are adjusted according to needs. According to the method, the first plasma and the second plasma are cooperatively controlled to adjust the groove structure in each stage, so that the uniformity of the groove structure is improved, and the damage to the surface of the side wall is reduced.

The invention discloses an LED semiconductor packaging dispensing detection device which comprises a fixed mounting table, a base frame, a round supporting plate, a sealing cover, an LED semiconductor storage box and an LED semiconductor body, the round supporting plate and the fixed mounting table are installed at the two ends of the top of the base frame respectively, and an equipment mounting frame is fixedly arranged on the outer surface of the fixed mounting table. A detection equipment body used for detecting the dispensing quantity is mounted at the top of the equipment mounting rack, and the size detection mechanism comprises a bearing reversing table used for bearing an LED semiconductor body, and a main clamping plate and an auxiliary clamping plate which are arranged at the two ends of the LED semiconductor body respectively. Through the size detection mechanism, infrared correlation, mechanical clamping and a multi-angle steering mechanism, size detection and position correction can be automatically completed while the dispensing number of an LED semiconductor body is detected, and the problem of inaccurate measurement caused by semiconductor position deviation or size errors in traditional manual detection is solved.

The invention relates to the technical field of wafer detection, and provides a wafer detection mechanism and wafer detection equipment. The wafer detection mechanism comprises a wafer carrying disc, an optical detection module, a moving module and a carrying module. The wafer carrying disc comprises a supporting part provided with a light through hole and a light-transmitting element arranged in the light through hole, the light-transmitting element and the hole wall of the light through hole jointly define a light-transmitting medium groove, and the light-transmitting medium groove is used for containing a light-transmitting medium filled between the light-transmitting element and the wafer to be detected; the optical detection module is arranged below the wafer carrying disc; the moving module is connected to the optical detection module and / or the wafer carrying disc and is used for driving at least one of the optical detection module and the wafer carrying disc to move relative to the other one on the horizontal plane; the carrying module is arranged above the wafer carrying disc; the liquid removing module and the wafer carrying disc are arranged in a spaced mode. According to the wafer detection mechanism provided by the invention, optical detection of different positions of the wafer can be realized, and the overall detection efficiency is obviously improved.

The invention discloses a precise positioning control method and system for photovoltaic module laminating welding, particularly relates to the technical field of welding positioning, and is used for solving the problem of systematic alignment deviation caused by independent control of welding and laminating procedures, lack of unified reference and physical deformation of battery strings in the prior art. A battery string image is obtained after welding, a morphological feature point set is extracted, the morphological feature point set is registered with a theoretical feature point set to calculate a current deformation field, then local curved surface fitting residual and equivalent strain energy density collaborative analysis identification is carried out, a pseudo deformation area is filtered out, and a credible physical deformation field is obtained. And generating importance weight distribution by combining functional information of a battery string region, performing compensation reconstruction on theoretical positioning coordinates of a film coating material by taking the weight as a target, generating a target fitting track under a film coating process reference coordinate system, and finally controlling an execution mechanism to operate according to the track, thereby realizing high-precision alignment fitting of the battery string and the film coating material.

A semiconductor device inspection method includes: selecting, for a semiconductor device including at least one layer, a target layer on which inspection and measurement are to be performed; selecting a material to fill a hole region formed inside the semiconductor device; conducting a simulation for an optical inspection and a measurement for the semiconductor device; selecting, based on the simulation, a wavelength band of light for the optical inspection and the measurement; and detecting, through the light at the selected wavelength, a lower portion of the semiconductor device and a defect of the semiconductor device. A refractive index of the material filling the inside of the hole region is greater than a refractive index of a molding layer surrounding the outside of the hole region.

The invention relates to the technical field of semiconductors, and discloses a semiconductor defect and yield Map-based automatic calibration method, which comprises the following steps of: acquiring wafer surface data in real time through a multi-modal sensor, analyzing station process parameters, and generating a time-space aligned wafer holographic data set; performing nonlinear deformation compensation based on the wafer holographic data set to generate a dynamic Die grid; utilizing a multi-task deep reinforcement learning model to predict initial Offset parameters of the defect Map and the yield Map; and performing global optimization on the initial Offset parameters through a quantum annealing algorithm, and outputting an optimal Offset. Data are collected through a multi-mode sensor, space-time alignment is carried out through Kalman filtering, a wafer holographic data set of space-time alignment is generated, the data space-time unification is achieved, the wafer state is accurately and completely reflected, and a high-quality data basis is provided for defect analysis and yield evaluation. The problem that data of the multi-modal sensor are inconsistent in time and space and are difficult to effectively fuse is solved.

A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.