7972results about "Semiconductor/solid-state device testing/measurement" patented technology

The invention provides a defect detection method and system for integrated circuit manufacturing. Wherein in the integrated circuit packaging stage, packaged chips are divided into a first type of chips meeting a preset physical characteristic threshold value and a second type of chips exceeding the physical characteristic threshold value through a pneumatic sorting device; performing scanning electron microscope imaging on the surface of the second type of chip, generating a three-dimensional topological structure by using an image reconstruction technology, and positioning a micron-sized particle defect area by comparing reference type differences; synchronously applying high-frequency electric signal excitation in the sorting process, detecting impedance response of the second type of chips, and recording an abnormal signal sequence exceeding a preset frequency domain range; performing space-time correlation matching on the micron-sized particle defect area and the abnormal signal sequence, and judging that the defect is a multi-layer composite defect when a preset coupling condition is met; and dynamically adjusting the mesh diameter and vibration frequency parameters of the pneumatic sorting device. According to the technical scheme provided by the invention, accurate identification of the multi-layer composite defect of the chip is realized, and the defect interception efficiency is remarkably improved.

The invention provides a method and system for enhancing wafer detection in a semiconductor manufacturing process, and relates to the technical field of wafer detection, and the method comprises the steps: transmitting dual-frequency laser to the surface of a wafer to form a controllable overlapping region, and collecting a beat frequency signal to obtain initial height information; carrying out adaptive filtering processing on the beat frequency signal, reconstructing a three-dimensional contour of the surface of the wafer, and generating an initial defect distribution diagram; and determining a secondary detection area according to the initial defect distribution diagram to perform orthogonal scanning, identifying and rejecting pseudo defect signals, extracting defect features, and determining defect cause types. According to the invention, the accuracy and efficiency of wafer defect detection are improved, and the semiconductor manufacturing quality can be improved.

An object of the invention is to provide a probe card capable of properly performing a measurement. A probe card according to the invention includes: probes 100 shaped to allow vertical elastic deformation; a supporting substrate 200 with the probes provided on the lower surface thereof; a main substrate 300 positioned opposing the upper surface of the supporting substrate 200; an intermediate substrate 400 disposed between the supporting substrate 200 and main substrate 300; a supporting member 500 that is a column-shaped member with one end thereof attached to the center of the supporting substrate 200 and the other end thereof attached to the intermediate substrate 400 and holds the supporting substrate 200 so that the supporting substrate 200 is inclinable; and elastic members for holding the supporting substrate 200 so that the supporting substrate 200 is in a horizontal position relative to the main substrate 300, which are provided between the supporting substrate 200 and main substrate 300.

The invention relates to the technical field of semiconductor manufacturing, and discloses a semiconductor wafer etching method with a detection function. The method comprises the following steps: acquiring initial image data of a wafer surface through an optical detection device, and extracting geometric features and defect distribution information; processing through a multi-scale feature fusion algorithm, identifying an abnormal region and classifying defect types; dynamically adjusting process parameters of etching equipment according to defect conditions, and planning a self-adaptive etching path; during etching, a real-time monitoring module is used for collecting data, and etching parameters are corrected through a feedback control mechanism; and after etching, the etching precision is secondarily detected and verified by means of a multispectral imaging technology. According to the method, defects can be accurately positioned, the etching process is optimized, the etching precision and quality are effectively improved, the rejection rate is reduced, and the efficiency and reliability of semiconductor wafer manufacturing are improved.

The invention relates to the technical field of target detection, in particular to a photovoltaic panel detection method and system based on machine vision, and the method comprises the following steps: obtaining the displacement data of a photovoltaic panel cell, calculating the displacement gradient of a connection point, dividing a rigid region and a non-rigid region, generating a deformation classification result, and constructing a global deformation field. Generating a time sequence deformation trend matrix; calculating a displacement mean value of a bracket fixing point; adjusting a deformation compensation parameter; generating an adaptive compensation parameter, adjusting a welding point position, calculating an abnormal region Euclidean distance, and generating a defect matching identification result. According to the method, rigid and non-rigid areas are accurately divided by calculating the displacement gradient of a connection point, a global deformation field is constructed in combination with the displacement change of a feature point, trend continuity is ensured, a compensation parameter is adjusted by utilizing a fixed point displacement mean value, a deformation increment factor is calculated, the weight and stability are corrected, the position of a welding point is adjusted, and inverse deformation correction is optimized. The Euclidean distance is combined to match defects, so that the detection precision and stability are improved.

The invention provides a packaging test method of an LED flip chip and related equipment. The method comprises the following steps: acquiring wafer packaging parameters of the LED flip chip; determining a warping degree prediction model of wafer packaging parameters and a process parameter sensitivity sequence through multi-physics field coupling modeling; monitoring a warpage measurement distribution diagram of the wafer according to the warpage prediction model; determining wafer warpage compensation data according to the process parameter sensitivity sequence and the warpage measurement distribution diagram; comparing a three-dimensional deformation graph correspondingly generated by the wafer warping degree compensation data with a prediction result of the warping degree prediction model, and determining a comparison result; and performing welding spot defect high-resolution scanning on the wafer of the LED flip chip according to the comparison result, and identifying the welding spot defect of wafer packaging. Through the implementation of the scheme of the invention, accurate prediction, effective compensation and reliable detection of wafer buckling deformation in the packaging process of the LED flip chip can be realized, and the packaging quality is remarkably improved.

The invention relates to a computer implemented method for defect detection comprising: obtaining an imaging dataset and a reference dataset of an object comprising integrated circuit patterns; and detecting defects in the imaging dataset using the imaging dataset and the reference dataset, wherein a machine learning model for defect highlighting is applied to the imaging dataset as input and generates a highlighted defect dataset as output, and wherein the machine learning model for defect highlighting comprises at least one attention mechanism. The invention also relates to computer programs, computer-readable media and corresponding systems.

A method for surface defect inspection can comprise obtaining topographical data from one or more portions of a semiconductor element. The semiconductor element can have a surface comprising a dielectric and a plurality of metal pads. The method can further comprise processing the topographical data of the one or more portions of the semiconductor element to determine at least a first property of the plurality of metal pads, computing at least one variability value for the first property, and identifying candidate defects in the one or more portions of the semiconductor element based at least in part on the at least one variability value.

The invention relates to the technical field of semiconductor packaging detection, and provides a self-adaptive semiconductor packaging detection method which comprises the following steps: synchronously acquiring packaging surface heat distribution data, three-dimensional deformation data and pin electric signal data through a multi-source sensor; performing dynamic weighted fusion on the multi-modal data based on the packaging process parameters to generate a defect feature matrix; performing dynamic threshold calibration on the defect feature matrix by adopting an adaptive threshold generation algorithm according to clustering center distribution in the historical defect pattern library; performing matching judgment on the dynamic threshold value and the real-time defect feature matrix through a multi-level logic decision model, and outputting a defect type, a position coordinate and a confidence score; and based on the defect type and the confidence score, triggering adaptive compensation control of the packaging process parameters, generating a feedback control instruction, and adjusting a packaging equipment execution mechanism in real time. The packaging quality and reliability can be improved, and the production cost and the defective rate can be reduced.

A method of processing a substrate. The method including delivering, by an RF generator, an RF signal to a processing volume of a processing chamber through an RF match including a configurable impedance altering element. Measuring in real-time, an electrical characteristic of the RF signal. Determining in real-time, a target electrical characteristic based upon a comparison between a calibrated electrical characteristic value and the measured electrical characteristic, in which the calibrated electrical characteristic value is selected to achieve at least one desired plasma processing parameter result. Adjusting in real-time, a setting of the configurable impedance altering element of the RF match to achieve the target electrical characteristic and maintaining, the target electrical characteristic by controlling the setting of the configurable impedance altering element of the RF match.

The invention relates to the technical field of wafer detection, in particular to a wafer bearing device, detection equipment and a detection method.The wafer bearing device comprises a plurality of bearing single bodies and a rotary table, and the bearing single bodies are circumferentially distributed on the rotary table; each bearing single body comprises a horizontal moving mechanism and a vertical moving mechanism, a horizontal sliding block reciprocates in the radial direction of the rotary table under the action of a horizontal driving part, the vertical moving mechanism is arranged on the horizontal sliding block, and a vertical sliding block reciprocates and ascends on the horizontal sliding block in the vertical direction under the action of a vertical driving part; the vertical sliding block is fixedly connected with a clamping jaw used for clamping a wafer. According to the invention, the bearing single body at the to-be-detected position can independently withdraw the clamping jaw, so that the edge area of the wafer is completely exposed; the complete edge area of the wafer can be detected through one-time rotation, cooperation with other equipment is not needed, the device structure is effectively simplified, the detection time is shortened, and the precision and quality of a detection result are improved.

The invention relates to the technical field of semiconductor manufacturing, and discloses an edge breakage defect prediction and compensation method in a wafer cutting process, and the method comprises the steps: obtaining a wafer cutting initial scheme and historical cutting data, extracting edge breakage key parameters, defining an edge vulnerability function, and building a high-risk region space mapping model; according to the real-time cutting position, multi-dimensional data are collected through a three-level monitoring mode, the abnormal deviation state of the track is judged, and an edge breakage risk assessment model is constructed and early warning is carried out; a compensation scheme is formulated after early warning is triggered, cutting is implemented, and the effect is verified; according to the method, multi-dimensional data are fused, the risk area is dynamically delimited, self-adaptive adjustment of the cutting parameters is achieved, and the wafer cutting yield is remarkably improved.

Described herein are methods and systems for measuring polarization states of nonlinearly generated light by a sample illuminated in response to receiving an incident beam having a known polarization state to determine a characteristic of the sample. The system includes an optical ellipsometer configured to be included in-line of a semiconductor fabrication line and generate measured signals proportional to different polarization parameters of second-harmonic light nonlinearly generated light by the sample, allowing determination of a complete polarization state of the second harmonic light using a characteristic of the sample is determined.

The invention provides a defect detection method and system. The method comprises the following steps: acquiring defect coordinate point cloud data of a to-be-detected sample; converting the defect coordinate point cloud data into a two-dimensional data point set; dividing the two-dimensional data point set into a plurality of detection areas, wherein the detection areas comprise path points; planning a detection path based on the path points; and performing defect reinspection on the detection area according to the detection path. According to the defect detection method provided by the invention, the defect coordinate point cloud data is converted into the two-dimensional data point set, and the two-dimensional data point set is subjected to region division and clustering processing, so that the detection path is planned. Different from a traditional point-to-point detection mode, the method has the advantages that frequent movement can be avoided, meanwhile, each defect point is accurately detected, the detection efficiency is improved, and the yield of equipment is further improved.

The invention provides a wafer defect detection method and device, and belongs to the technical field of semiconductor manufacturing. The wafer defect detection method comprises the steps that defect data of the surface of each wafer are acquired, and the defect data comprise defect types and defect position coordinates; the defect position coordinates of the same batch of wafers are subjected to clustering analysis through a spatial clustering algorithm, the defect distribution mode and defect distribution density of the batch of wafers are determined, and the same production process parameters are adopted for the same batch of wafers; calculating the risk score of the batch of wafers according to the defect distribution mode and the defect distribution density of the batch of wafers and the proportion of abnormal wafers in the batch; and comparing the risk score of the batch of wafers with a preset risk threshold, and if the risk score of the batch of wafers is greater than the preset risk threshold, determining the batch of wafers as abnormal wafers. According to the invention, the batch defect of the wafer can be detected.

The invention relates to the technical field of information, in particular to a method for detecting and monitoring the cleaning effect of a semiconductor wafer in real time in the technical field of semiconductor wafer manufacturing, which comprises the following steps: introducing a rapid chemical analysis technology, combining an electrochemical sensor and spectral analysis, monitoring metal ion residues on the surface of the wafer in real time, and shortening the detection period; instant feedback on a production line is realized; a real-time feedback control system is constructed, according to the output of the comprehensive evaluation model, the working parameters of the cleaning equipment are automatically adjusted, the cleaning process is optimized, and the usage amount of cleaning liquid and the environmental influence are reduced; an edge computing technology is integrated, data processing and analysis tasks are sunk to a cleaning equipment end, data transmission delay is reduced, and the response speed of real-time monitoring and feedback control is increased; a visual monitoring platform is developed, key parameters, detection results and prediction trends in the cleaning process are displayed in a graphical mode, and operators can conveniently master the cleaning state in real time and quickly respond to abnormal conditions.

The present invention discloses an on-line detection device for surface defects of semiconductor wafers, which relates to the technical field of wafer detection. It solves the problem that the part where the wafer is attached to the carrier ring is blocked by the carrier ring, and the vision detection system cannot image the part where the wafer is attached to the carrier ring, resulting in a lack of integrity in the detection of surface defects of semiconductor wafers. The device includes a machine base, on the upper end of which a machine cover is fixedly installed. Inside the machine cover, a first detection probe is fixedly installed. Inside the machine base, a second detection probe is fixedly installed. It also includes a feeding mechanism for feeding the semiconductor wafer into the machine cover for detection, and the feeding mechanism is installed on the upper end of the machine base. By installing the feeding mechanism and the material loading component, the two high-transparency films in the material loading component can clamp the semiconductor wafer, prevent the wafer from displacement, and facilitate the first detection probe and the second detection probe to completely detect the semiconductor wafer.

The invention discloses a wafer detection device and method, and belongs to the field of wafer detection, and the device comprises a rotating table which is suitable for bearing and adsorbing a wafer and driving the wafer to rotate; the positioning mechanism is suitable for detecting the offset of the wafer in the wafer rotating process; the adjusting mechanism is suitable for jacking the wafer away from the rotating table and driving the jacked wafer to finely adjust the wafer along a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction in response to the offset detected by the positioning mechanism; the first detection mechanism is used for detecting the edge of the wafer; the first supporting mechanism is located below the wafer and corresponds to part of the wafer in the detection area of the first detection mechanism, and the first supporting mechanism is suitable for being upwards close to and supporting the edge of the wafer; the wafer is suitable for being driven by the rotating table to rotate so that all parts of the periphery of the wafer can flow through the detection area of the first detection mechanism. By adopting the structure, the wafer can be accurately and efficiently detected.

The invention discloses an intelligent sealing test method and system for a wafer in a semiconductor chip, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: initializing a magneto-electric field cooperation parameter, optimizing the magneto-electric field cooperation parameter through a multi-target genetic algorithm, and driving core-shell nanoparticles to carry out the metallization filling of a high-precision through hole wafer, generating a wafer with a metalized through hole structure; based on the metalized through hole structure wafer, bonding parameters are generated through a laser Doppler frequency vibration spectrum analysis method, flip interconnection is achieved through a thermal ultrasonic virtual process, and a low-defect bonding wafer is generated; a finite element inversion algorithm is adopted, a stress distribution map of a bonding interface is established, an anti-thermal-stress packaging layer is constructed through an intelligent stress matching algorithm, and the low-defect bonding wafer is packaged; and through a multi-target genetic algorithm, magnetoelectric field cooperation parameters are optimized, core-shell nano-particles are driven to directionally deposit, and accurate control over the metallization filling process is achieved.

The invention provides wafer detection equipment and a wafer detection method, which are used for solving the problem of how to improve the wafer detection efficiency. The wafer detection equipment comprises a double-sided detection unit, the double-sided detection unit comprises a scanning carrying platform, a front optical imaging module and a back optical imaging module, and the scanning carrying platform can linearly move along a first direction; the front optical imaging module and the back optical imaging module are respectively arranged on two opposite sides of the scanning stage and are respectively provided with a back bright field light source and a back dark field light source; when the scanning stage moves along the positive direction of the first direction, the front bright field light source and the back bright field light source are synchronously turned on, and the front optical imaging module and the back optical imaging module respectively generate bright field images of the front and back of the wafer; and when the scanning stage moves along the negative direction of the first direction, the front and back dark field light sources are synchronously turned on, and the front optical imaging module and the back optical imaging module respectively generate dark field images of the front and back of the wafer.

Proposed are an electro-conductive contact pin capable of effectively testing the electrical characteristics of a test object without a body thereof being elastically bent or curved in a convex shape in the horizontal direction by pressure applied to opposite ends thereof, and a vertical probe card having the same.

According to the wafer surface defect detection system based on the multi-channel sensor, multi-dimensional information of the to-be-detected wafer is collected through the data collection module, multiple types of defects can be detected, more complete information is provided for production quality control, and the chip performance problem and the yield reduction risk caused by the fact that the defects are not detected out are effectively reduced; the intelligent decision-making module can automatically learn and identify defect features, accurately judge defect types and severity, and reduce the influence of manual intervention and subjective factors. The data splicing and weighted fusion technology enables the model to make full use of multi-sensor information to adapt to a complex detection scene; the result storage and report generation module records detection data in detail and generates a report, the report contains defect position, type, size, image or signal feature and influence analysis, the detection result is visually displayed, a user is helped to rapidly know the wafer quality condition, and a powerful basis is provided for subsequent decision making.

The invention relates to the technical field of chip mounting, in particular to a die bonder and a die bonding method. The die bonder comprises a track device, a feeding device, a gluing device, a mounting device, a chip supply device and a discharging device. The feeding device and the discharging device are arranged at the two ends of the track device in the length direction correspondingly. The gluing device is arranged at the end, close to the feeding device, of the side edge of the rail device. The mounting device is arranged at the end, close to the discharging device, of the side edge of the rail device, the mounting device and the gluing device are located on the same side of the rail device, and the mounting device comprises a visual positioning component and a mounting component which are independently arranged; and the chip supply device is arranged on the other side of the track device and corresponds to the mounting device. The die bonder provided by the invention is compact in structure, the moving distance of each link is reduced, and the mounting efficiency is improved.

The invention discloses a chip-level GaAs etching temperature control method, which comprises the following steps: detecting the upper surface temperature of a GaAs wafer in the etching process in real time to obtain first temperature data; and according to a partition structure in the electrostatic chuck and the first temperature data, determining a to-be-adjusted electrostatic chuck partition and determining a second temperature of the upper surface of the carried GaAs wafer corresponding to the to-be-adjusted electrostatic chuck partition. And on the basis of the second temperature data and the target temperature, power adjustment is carried out on the heating unit of the to-be-adjusted electrostatic chuck partition through the partition temperature PID control module, and the second temperature data is adjusted to the target temperature. According to the invention, the power of the local heating unit is adjusted according to the wafer surface temperature data obtained in real time by using the partition temperature PID control module, and the temperature of each area is ensured to be uniform and stable. The control coefficient of the PID controller is optimized in an auxiliary mode through the neural network, and the self-adaptive capacity and the control precision of the system are improved.

The invention relates to the technical field of semiconductor manufacturing, in particular to an accurate detection method and system for a flat-edge sheet wafer placement rotary chuck, and the method comprises the steps: when a wafer is placed on the rotary chuck, scanning the lap joint condition of a wafer edge and a chuck contact area through a laser sensor, and obtaining the real-time distribution data of an edge lap joint sheet; flat edge position information is extracted from the edge lap joint distribution data, an image matching algorithm is adopted to compare a preset orientation reference, and a specific angle value of orientation deviation is determined; according to the orientation deviation angle value and the edge lapping piece distribution data, the rotating speed and the angle of the rotating chuck are adjusted through a cooperative control algorithm, and a final positioning result of the wafer on the chuck is obtained; after a final positioning result is obtained, the in-place state of the wafer is classified and judged through a deep learning model, and whether the residual deviation or wafer lapping phenomenon exists or not is determined; and extracting abnormal data from a classification judgment result, and adjusting collaborative parameters of carrying and placing according to the abnormal data to obtain an optimized process control scheme.

The invention provides an adjustment method of detection equipment, and the detection equipment sequentially comprises an objective lens, a spectroscope, a barrel lens and a detector from an object space to an image space, and also comprises a Kohler illumination module. The illumination light beam is emitted from the Kohler illumination module and is transmitted to the objective lens through the spectroscope, when the object to be detected is arranged on one side, far away from the spectroscope, of the objective lens, the illumination light beam emitted from the objective lens is reflected to obtain a reflected light beam, and the reflected light beam sequentially passes through the objective lens, the spectroscope and the barrel lens to reach the detector. After an aperture diaphragm is inserted into the Kohler illumination module and an auxiliary lens is arranged between the barrel lens and the detector, obtaining a first light spot position of a light spot formed by the aperture diaphragm at an entrance pupil of the objective lens through the detector; and under the condition that the Kohler illumination module does not provide the illumination light beam and the light source is used as an object to be detected, acquiring a second light spot position of the light spot of the entrance pupil of the objective lens through the detector, adjusting the position of the aperture diaphragm according to the first light spot position and the second light spot position, and aligning the illumination optical axis and the imaging optical axis.

The invention relates to the field of semiconductor detection, and discloses a chip detecting and sorting device and method.A rack is provided with a feeding and discharging gripper module, a detecting module, a transferring module and a braiding module; the transfer module comprises a first conveying line, a second conveying line, a third conveying line and a tray transfer mechanism; the detection module comprises a first detection device and a second detection device, the first detection device is used for detecting the side surface and the bottom surface of the chip, and the second detection device is used for detecting the front surface of the chip; the taping module comprises a taping mechanism, and the taping mechanism is used for taping and packaging the chip; the feeding and discharging gripper module comprises a feeding mechanism and a discharging mechanism. The feeding mechanism is used for transferring chips between the first conveying line and the first detection device. The discharging mechanism is used for transferring chips among the second conveying line, the third conveying line and the braiding mechanism. The chips are transferred through the feeding mechanism and the discharging mechanism, damage to the chips when the chips are manually moved is avoided, and the chip sorting and detecting efficiency is higher.

The invention belongs to the technical field of wafer processing, and discloses a multi-section high-flatness wafer cutting method which comprises the following steps: S1, wafer pretreatment and stress buffer layer preparation; s2, performing layered rough cutting by using a diamond blade; s3, plasma fine cutting and interface repairing; s4, performing multi-layer cooling and surface polishing; and S5, surface quality closed-loop detection is carried out. According to the method, copper layer residues and resin carbonization defects are synchronously eliminated. Cryogenic treatment induces lattice reconstruction through ultrafast phase change and blocks a chain reaction of dislocation defects, so that the intrinsic mechanical strength of the material is recovered, and a chemical mechanical polishing system activates the self-repairing characteristic of the material while removing a sub-surface damaged layer through the synergistic effect of abrasive chemical activity and mechanical shearing force, so that an atomic-scale smooth interface is formed, and the self-repairing performance of the material is improved. A closed-loop detection system depends on multi-dimensional data fusion and ion beam fixed-point repair, accurate positioning and performance recovery of cross-scale defects are achieved, and the electrical integrity of a chip functional area is ensured.

The invention relates to the technical field of chip packaging, and discloses an ultrathin multi-layer storage chip stacking packaging method, which comprises the following steps of: obtaining a storage chip to be packaged, performing chip quality division on the storage chip to be packaged to obtain a target chip, and performing fine classification on the target chip to obtain a plurality of groups of chips; performing thickness optimization on the multiple groups of divided chips to obtain thickness-optimized chips, and performing chip selection on the thickness-optimized chips to obtain selected chips; performing material coating on the selected chip to obtain a coated chip, performing chip curing on the coated chip to obtain a cured chip, and performing chip stacking on the cured chip to obtain a stacked chip; carrying out three-dimensional modeling on the stacked chips so as to carry out dispensing path planning on the stacked chips to obtain a dispensing path, and carrying out chip reinforcement on the stacked chips to obtain reinforced chips; and performing internal interconnection, preliminary packaging and shell injection molding on the reinforced chip to obtain a packaged chip. According to the invention, the packaging quality of the ultrathin multi-layer memory chip can be improved.

The invention relates to the technical field of light source regulation and control, and discloses a UV light source accurate regulation and control method for wafer defect detection and related equipment, and the method comprises the following steps: determining initial detection parameters of wafer defect detection; obtaining a wafer surface image of the target wafer according to the initial detection parameters; identifying defect information of the wafer surface image; evaluating a detection effect value of the initial detection parameter according to the defect information; and if the detection effect value is lower than the preset detection threshold value, generating a UV light source regulation and control strategy according to the defect information. Through the implementation of the scheme of the invention, a closed-loop feedback mechanism is established by obtaining the initial detection parameters and evaluating the detection effect value, the situation that the detection effect is not ideal is found in time, the UV light source parameters are adjusted according to the situation, it is ensured that defect detection is always kept in the optimal state, and the accuracy of wafer defect detection is improved.