673results about How to "Guaranteed high speed operation" patented technology

A thin film transistor structure in which a source electrode and a drain electrode formed from a metal material are in direct contact with an oxide semiconductor film may lead to high contact resistance. One cause of high contact resistance is that a Schottky junction is formed at a contact plane between the source and drain electrodes and the oxide semiconductor film. An oxygen-deficient oxide semiconductor layer which includes crystal grains with a size of 1 nm to 10 nm and has a higher carrier concentration than the oxide semiconductor film serving as a channel formation region is provided between the oxide semiconductor film and the source and drain electrodes.

An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.

Air based emergency monitor, multimode communication, control and position finder system with a receiver having multiple inputs for reception and demodulation of position finder signals to position finder baseband signals. One or more cameras or microphones or data signal generation devices, storage devices, and processors for recording or storing and processing of signals obtained from one or more cameras or microphones or data signal generation devices. A processor for processing input signals and for providing cross-correlated shaped in-phase and quadrature-phase baseband signals. Transceivers for multimode GSM, spread spectrum, CDMA, OFDM, TDMA and other signals. A receiver and demodulator for reception of modulated position finder radio frequency (RF) signals transmitted by a Global Positioning System (GPS) transmitter and a receiver and demodulator for reception of modulated position finder radio frequency (RF) signals transmitted by other than a GPS transmitter for providing the demodulated and receiver processed signal to an emergency unit. An air based position finding, signal monitor, control and emergency multimode communication system for use in one or more units located in or on airplanes, or helicopters, or unmanned vehicles (UV) or balloons or rockets, or missiles, or space shuttles or birds or other air based items with a multimode bit rate agile (BRA) and modulation demodulation (modem) format selectable (MFS) signal modulator.

A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane. Further, the CPU writes a second byte of data into the second plane and writes the second byte of data having been stored in the second plane while writing the first byte of data having been stored in the first plane into the memory array.

A semiconductor graphene is used for a channel layer, and a metal graphene is used for electrode layers for a source, a drain, and a gate which serve as interconnections as well. An oxide is used for a gate insulating layer. The channel layer and the electrode layers are located on the same plane.

In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level.

A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

A semiconductor integrated circuit according to the present invention comprises a MOS transistor formed on an SOI substrate and a subsidiary transistor provided between a body node and a drain node of the MOS transistor and sharing a gate electrode with the MOS transistor, whereby body potential of the MOS transistor is controlled by gate and drain potentials. Accumulated body charge in a non-conducting state in the semiconductor integrated circuit is extracted by a resistor formed between the body node and a source, whereby various phenomena caused by floating body effect are eliminated. Since the body potential of the MOS transistor can be varied without creating an undesirable leakage current path, and hence without limitations to supplied voltage, its threshold voltage can be made variable so as to follow change in an input signal, thereby making it possible to achieve higher speed and lower voltage operation of the semiconductor integrated circuit. According to the present invention, it is possible to eliminate floating body effect, which is the greatest problem with an SOI transistor formed on an SOI substrate, and also to achieve lower voltage and greater current operation of a transistor without posing limitations to supplied voltage and without causing the problem of leakage current.

Global Positioning System (GPS) and non GPS position finder, emergency, multiple input multiple output (MIMO), multimode, spread spectrum, code division multiple access (CDMA), Global Mobile System or Global System Mobile (GSM) and orthogonal frequency division multiplex (OFDM) communication systems. Position finder and emergency communication multiple input multiple output (MIMO) system and a receiver having multiple inputs for reception and demodulation of position finder signals to position finder baseband signals. A processor for processing position finder signals with a signal containing an emergency number. A processors for processing signals to provide cross-correlated shaped in-phase and quadrature-phase baseband signals, spread spectrum and OFDM baseband signals. A control unit for control and selection of one of the jointly processed signals and a selector for providing the selected signal to a modulator. A modulator for modulating the selected signal and for connecting the modulated signal to a multiple output signal transmitter for signal transmission. A demodulator connected to the emergency receiver for demodulation of the modulation format selectable (MFS) and bit rate agile (BRA) modulated signal with at least one demodulator filter which has a mis-match with the corresponding filter of the modulator.

A semiconductor integrated circuit device is comprised a main memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns and a sub memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns, wherein at least one of address input terminals assigning rows or columns of the main memory portion and at least one of address input terminals assigning rows or columns of the sub memory portion are commonly used and a total number of address input terminals is equal to or smaller than the number of address input terminals assigning rows or columns of the main memory portion. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

An imaging method and system that flexibly accesses light sensor elements and processes imaging signals. The imaging system comprises an array of pixel sensor cells, an array controller and a readout control circuit. The imaging system provides color interpolation.

Provided is a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and which does not have a limitation on the number of writing. The semiconductor device includes both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small), and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (that is, a transistor capable of operating at sufficiently high speed). Further, the peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion, so that the area and size of the semiconductor device can be decreased.

An object of the invention is to improve the reliability of a light-emitting device. Another object of the invention is to provide flexibility to a light-emitting device having a thin film transistor using an oxide semiconductor film. A light-emitting device has, over one flexible substrate, a driving circuit portion including a thin film transistor for a driving circuit and a pixel portion including a thin film transistor for a pixel. The thin film transistor for a driving circuit and the thin film transistor for a pixel are inverted staggered thin film transistors including an oxide semiconductor layer which is in contact with a part of an oxide insulating layer.