45 results about "Floating body effect" patented technology

Novel NEDMOS and / or LDMOS FET integrated circuit structures that reduce or eliminate the floating body effect by reducing the built-in voltage Vbi of the device. Reduction of Vbi includes adding a source-side structure that includes a “Vbi Reduction Material” (VRM) layer. VRM has a bandgap less than the bandgap of Si and, for an N-type device, a valence band that is higher than the valence band of the body material. The low Vbi of the VRM layer on the source-side of a MOSFET device that would otherwise exhibit a floating body effect allows significantly freer movement of holes from the body of the device towards the source region, thus increasing body hole collection efficiency, and significantly reduces the floating body effect.

Embodiments of the present disclosure provide a memory device and a vertical fin gate transistor. A memory device includes a memory cell, wherein the memory cell includes a bit line, a word line over the bit line, and a semiconductor substrate on the bit line. The word line includes a plurality of fin-type words, a fin connector connecting the fin-type word line, and a common word line on the fin connector. The memory cell also includes a body line physically contacting one of the sidewalls of the semiconductor substrate and an insulating layer covering the body line, wherein the remaining sidewalls of the semiconductor substrate are partially covered by the fin word lines. The body line is grounded to direct accumulated charge out of the semiconductor substrate, thereby reducing floating body effects in the memory cell.

Embodiments of the present disclosure provide a memory device and a vertical fin field effect transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, a plurality of semiconductor fins on the bit line and embedded in the word line, a body line physically contacting one of sidewalls of each of the semiconductor fins, and an insulating layer embedding the body line. The body line is grounded to direct the accumulated charges out of the semiconductor fins, thereby reducing the floating body effect in the memory cell.

The invention provides a preparation method of a deep trench isolation structure, the structure and a semiconductor device, and relates to the technical field of semiconductor devices. The preparation method of the deep trench isolation structure comprises the following steps: providing a substrate; the substrate comprises a bottom layer, a buried oxide layer and an active layer which are stacked in sequence. A first groove is formed in the substrate, the first groove penetrates through the active layer, and the groove bottom of the first groove ends at the buried oxide layer. Forming a second groove communicated with the first groove in the buried oxide layer; the second groove penetrates through the buried oxide layer. And forming doped polycrystalline silicon on the side wall of the second groove. Forming an oxide filling the first groove and the second groove; wherein the doped polycrystalline silicon in the second groove is relatively positioned on the periphery of the oxide in the second groove. According to the preparation method, the self-heating effect and the floating body effect of the SOI device can be effectively inhibited.

Methods for forming floating body effect attenuated 3D dynamic random access memory elements are disclosed herein. In one example, a method may include forming a plurality of layers stacked in a first direction, the plurality of layers including gate layers formed on a first oxide layer, and source / drain (S / D) layers between a set of gate oxide layers. The set of gate oxide layers may be formed over the gate layer, and the S / D layer may include a source and a drain on opposite sides of the body. The method may also include forming a doped layer over the source electrode and the drain electrode.

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure comprises a semiconductor layer which comprises a first end part, a second end part and a middle part located between the first end part and the second end part, wherein the first end part and the second end part are integrally formed; in the first section, the middle part is annular; the second end part comprises a first extension part and a second extension part; the first extension part extends along a first direction and a second direction; the second extension part extends along the third direction and is connected with the middle part and the first extension part; in the first section, the first extending part is in a solid closed shape, the second extending part is annular, and the size of the first extending part is larger than the outer side overall size of the second extending part. According to the invention, the floating body effect can be inhibited.

Semiconductor devices and methods of manufacturing the same are described. The methods form a 3D DRAM architecture that includes a semiconductor isolation bridge, eliminating a floating body effect. The method includes forming an epitaxial layer in a deep trench isolation opening and creating a semiconductor isolation bridge between adjacent deep trench isolation openings.

The invention relates to a complementary ring channel MOS transistor and a preparation method thereof, a semiconductor device and electronic equipment. The complementary ring channel MOS transistor comprises a first MOS transistor and a second MOS transistor, wherein the first MOS transistor comprises a gate structure and a first surrounding structure, and the second MOS transistor comprises a gate structure and a second surrounding structure. According to the invention, the first surrounding structure and the second surrounding structure surround the outer surface of the gate structure, so that the circuit density is greatly improved, and the chip area in the subsequent process is greatly saved; meanwhile, the preparation process is simple, the production cost is low, the floating body effect does not exist, and batch production is facilitated.

NEDMOS FETs capable of withstanding high drain voltages while attaining high device reliability, and which remediate the floating body effect using one of several novel architectures. Each architecture provides a P or P+ pathway between the body of a NEDMOS device and a device-wide P+ body tie. The P / P+ pathway enables collection and conveyance of holes over to the device-wide body ties, resulting in elimination or substantial mitigation of the floating body effect. Use of a body tie spanning the width of the gate conductive layer (e.g., polysilicon) provides a number of benefits without reducing the effective width of the gate structure or increasing the gate capacitance CGG. Thus, one aspect of the present invention encompasses a MOSFET including a pathway between a body of the MOSFET and a device-wide body tie, wherein the pathway enables collection and conveyance of holes from the body over to the device-wide body tie.

This technology includes a vertical cell array transistor (VCAAT) with improved floating body effect. The array includes one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The array includes one or more channels extending vertically substantially orthogonal to the first and second horizontal directions such that the bit lines intersect the source / drain regions of the multiple channels and the word lines intersect the gate regions of the multiple channels. The array includes a case where the source / drain region has a first section adjacent to the source / drain junction and a second section adjacent to the channel body, and the first section has a higher doping concentration than the second section.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof, and the device comprises an SOI (Silicon On Insulator) substrate which comprises a silicon substrate and an insulating layer formed in the silicon substrate, and the insulating layer isolates the silicon substrate into a top substrate located at the upper part and a bottom substrate located at the lower part; the gate dielectric layer is formed on the top layer substrate; the grid electrode is formed on the grid dielectric layer; wherein a well region and a drift region are formed in the top substrate, a first heavily doped region is formed in the drift region, a second heavily doped region is formed in the well region, an LDD region is formed in the well region between the second heavily doped region and the gate in the transverse direction, and the LDD region is in contact with the second heavily doped region; when the LDMOS device works, the first heavily doped region is a drain electrode, the LDD region is a source electrode, and the second heavily doped region is a body electrode. According to the LDMOS device provided by the embodiment of the invention, the floating body effect can be improved, and the design flexibility of an SOI chip is improved.

The invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises an SOI substrate, and the SOI substrate comprises a bottom substrate, a buried oxide layer and a top semiconductor layer which are stacked in sequence; the isolation structure is embedded in the SOI substrate so as to divide the SOI substrate into device regions; the isolation structure comprises a first STI structure and a second STI structure, the first STI structure extends from the top semiconductor layer to be in contact with the buried oxide layer, and the second STI structure extends from the top semiconductor layer to the bottom substrate; and a substrate contact connected with the bottom substrate through the first STI structure. Therefore, the substrate contact of the device region is isolated from the substrate contact of another adjacent device region through the isolation structure, so that the semiconductor structure provided by the invention can be respectively pressurized and controlled, and the floating body effect of the semiconductor structure is weakened while the uniformity between the semiconductor structures is improved.

The present disclosure relates to a memory cell structure, a memory cell array, and a method for fabricating the same. The memory cell structure includes an active platform, a target active pillar, a bit line structure, a first word line structure, and a second word line structure. The target active pillar is located on the top surface of the active platform and includes a common active pillar, a first active pillar, an intermediate isolation structure, and a second active pillar located on the top surface of the common active pillar and sequentially distributed along a first direction. The bit line structure is located on the top surface of the active platform and circumferentially surrounds the bottom of the target active pillar. The first word line structure and the second word line structure are located on opposite sides of the common active pillar along the first direction. This method effectively avoids the floating body effect and improves bit line flatness and leakage current.

The present technology includes a vertical cell dynamic random access memory (DRAM) array access transistor with improved hole distribution. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending in a vertical direction orthogonal to the first direction and the second horizontal direction such that the plurality of bit lines intersect source / drain regions of the plurality of channels and the plurality of word lines intersect gate regions of the plurality of channels. Further, the array includes a p-doped bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, where the first channel is spaced apart from the second channel in a row extending in the second horizontal direction.

The embodiment of the invention relates to a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a plurality of active groups which are arranged in an array, and each active group comprises two semiconductor columns which are arranged at an interval along a first direction; the body region control line and the two word lines correspond to an active group and are arranged at intervals in the first direction, the body region control line is located on the first side walls, close to each other, of the two semiconductor columns, and the two word lines are located on the second side walls, away from the body region control line, of the two semiconductor columns respectively; the body region control line and the word line are partially opposite in the first direction. The semiconductor structure provided by the embodiment of the invention at least can improve the floating body effect and the coupling effect of the semiconductor structure at the same time.

This specification discloses a method for forming a three-dimensional dynamic random access memory device with reduced floating body effects. In one embodiment, the method may include forming a plurality of layers stacked in a first direction, the plurality of layers including a gate layer formed on a first oxide layer and source / drain (S / D) layers between the series of gate oxide layers. The series of gate oxide layers may be formed on top of the gate layer, and the S / D layers may include a source and a drain located on opposite sides of the body. The method may further include forming doped layers on top of the source and drain.

Devices and methods include a partially depleted silicon on insulator device that comprises a transistor. The transistor comprises a gate terminal. The transistor also includes a first non-gate terminal and a second non-gate terminal. Moreover, the first non-gate terminal is coupled to a body of the partially depleted silicon on insulator device.

Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include a dielectric isolation structure located at least partially beneath a semiconductor body and between the semiconductor body and a substrate. Example semiconductor devices and methods also include an electrical contact coupling the semiconductor body to the substrate. In one example, the electrical contact reduces or eliminates a floating body effect in the semiconductor body.

Embodiments of the present disclosure provide a memory device and a vertical fin-gate transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, and a semiconductor substrate on the bit line. The word line includes a plurality of fin type word lines and a common word line connecting the fin type word lines, where the fin type word lines partially cover a first sidewall of the semiconductor substrate. The memory cell also includes a body line physically contacting a second sidewall of the semiconductor substrate opposite to the first sidewall of the semiconductor substrate, and an insulating layer embedding the body line. The body line is grounded to direct the accumulated charges out of the semiconductor substrate, thereby reducing the floating body effect in the memory cell.

The present invention provides an integrated structure based on a multi-material composite substrate structure and a manufacturing method thereof. In the above device, a multi-layer structure is epitaxially disposed on the multi-material composite substrate; the multi-layer structure includes a buffer layer, a high-resistance layer, and a channel layer arranged in an overlapping manner; a plurality of p-type regions are spaced in the region of the channel layer; a barrier layer is epitaxially disposed on the channel layer, and a two-dimensional electron gas is formed at the interface; a trench isolation region penetrates from the top of the barrier layer downward to the multi-material composite substrate; a first channel penetrates from the top of the barrier layer downward to the buffer layer; a second channel penetrates from the top of the barrier layer downward to the channel layer and contacts the p-type region; a passivation dielectric layer is deposited on the surface of the barrier layer, filled in the trench isolation region, and covers the inner wall sides of the first channel and the second channel. This integrated structure can effectively solve a series of problems existing in the prior art, such as the floating body effect, self-heating effect, hot carrier effect, short channel effect, latch-up effect of bulk silicon devices, power consumption, and the increase of parasitic resistance and capacitance.

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure includes a semiconductor layer including a first end portion, a second end portion, and an intermediate portion between the first end portion and the second end portion; in a first cross section intersecting with the extending direction of the semiconductor layer, the middle part is annular, and the size of the outer side outline of the middle part is smaller than that of the outer side outline of the first end part and / or smaller than that of the outer side outline of the second end part. According to the invention, the purpose of inhibiting the floating body effect can be achieved.

Novel NEDMOS and / or LDMOS FET integrated circuit structures that reduce or eliminate the floating body effect by reducing the built-in voltage Vbi of the device. Reduction of Vbi includes adding a source-side structure that includes a "Vbi Reduction Material" (VRM) layer. VRM has a bandgap less than the bandgap of Si and, for an N-type device, a valence band that is higher than the valence band of the body material. The low Vbi of the VRM layer on the source-side of a MOSFET device that would otherwise exhibit a floating body effect allows significantly freer movement of holes from the body of the device towards the source region, thus increasing body hole collection efficiency, and significantly reduces the floating body effect.

Embodiments of the present disclosure provide a memory device and a vertical fin-gate transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, and a semiconductor substrate on the bit line. The word line includes a plurality of fin type word lines, a fin connector connecting the fin type word lines, and a common word line on the fin connector. The memory cell also includes a body line physically contacting one of sidewalls of the semiconductor substrate and an insulating layer embedding the body line, where the fin type word lines partially cover others of the sidewalls of the semiconductor substrate. The body line is grounded to direct the accumulated charges out of the semiconductor substrate, thereby reducing the floating body effect in the memory cell.

The invention relates to a body-connected transistor device and a method. Apparatuses and methods are disclosed, including transistors, semiconductor devices, and systems. Example semiconductor devices and methods include a dielectric isolation structure positioned at least partially below a semiconductor body and between the semiconductor body and a substrate. Example semiconductor devices and methods also include coupling the semiconductor body to an electrical contact of the substrate. In one example, the electrical contacts reduce or eliminate floating body effects in the semiconductor body.

A SOI substrate, SOI device, and method for forming the same. The SOI substrate comprises: a bottom silicon layer; a buried oxide layer located on the bottom silicon layer; a composite core layer located in the buried oxide layer; the top surface of the composite core layer being flush with the top surface of the buried oxide layer; a top silicon layer located on the buried oxide layer and the composite core layer; the top silicon layer having an active region, wherein source / drain doped regions are subsequently formed in the active region; the composite core layer is located below the subsequently formed source / drain doped regions and is used to absorb and conduct charges from the subsequently formed neutral region. The above-described scheme can effectively suppress the floating body effect and improve the performance of the resulting SOI device.

Embodiments of the present disclosure provide a memory device and a vertical fin gate transistor. A memory device includes a memory cell, wherein the memory cell includes a bit line, a word line over the bit line, and a semiconductor substrate on the bit line. The word lines include a plurality of fin-type word lines and a common word line connecting the fin-type word lines, wherein the fin-type word lines partially cover a first sidewall of the semiconductor substrate. The memory cell also includes a body line physically contacting a second sidewall of the semiconductor substrate opposite the first sidewall of the semiconductor substrate, and an insulating layer covering the body line. The body line is grounded to direct accumulated charge out of the semiconductor substrate, thereby reducing floating body effects in the memory cell.

Embodiments of the present disclosure provide a memory device and a vertical fin field effect transistor. The memory device includes a memory cell, wherein the memory cell includes a bit line, a word line over the bit line, a plurality of semiconductor fins on the bit line and embedded in the word line, a body line physically contacting one sidewall of each semiconductor fin, and an insulating layer covering the body line. The body line is grounded to direct accumulated charge out of the semiconductor fins, thereby reducing floating body effects in the memory cell.

Devices (180) and methods (200) include a partially depleted silicon on insulator device (50) that comprises a transistor. The transistor comprises a gate terminal (106). The transistor also includes a first non-gate terminal (108) and a second non-gate terminal (110). Moreover, the first non-gate terminal (108) is coupled to a body (194) of the partially depleted silicon on insulator device (50).

The present technology includes vertical cell array transistor (VCAAT) with improved floating body effect. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source / drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the source / drain region has a first section adjacent to a source / drain junction and a second section adjacent to a channel body, where the first section has a doping concentration that greater than a doping concentration of the second section.

The present technology includes a vertical cell array transistor (VCAAT) with an improved floating body effect. The arrays include one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The array includes one or more channels extending in a vertical direction substantially orthogonal to the first direction and the second horizontal direction such that the bit lines intersect source / drain regions of the plurality of channels and the word lines intersect gate regions of the plurality of channels. The array includes a source / drain region having a first section adjacent the source / drain junction and a second section adjacent the channel body, wherein the doping concentration of the first section is greater than the doping concentration of the second section.