33 results about "Floating body effect" patented technology

Novel NEDMOS and / or LDMOS FET integrated circuit structures that reduce or eliminate the floating body effect by reducing the built-in voltage Vbi of the device. Reduction of Vbi includes adding a source-side structure that includes a “Vbi Reduction Material” (VRM) layer. VRM has a bandgap less than the bandgap of Si and, for an N-type device, a valence band that is higher than the valence band of the body material. The low Vbi of the VRM layer on the source-side of a MOSFET device that would otherwise exhibit a floating body effect allows significantly freer movement of holes from the body of the device towards the source region, thus increasing body hole collection efficiency, and significantly reduces the floating body effect.

Embodiments of the present disclosure provide a memory device and a vertical fin gate transistor. A memory device includes a memory cell, wherein the memory cell includes a bit line, a word line over the bit line, and a semiconductor substrate on the bit line. The word line includes a plurality of fin-type words, a fin connector connecting the fin-type word line, and a common word line on the fin connector. The memory cell also includes a body line physically contacting one of the sidewalls of the semiconductor substrate and an insulating layer covering the body line, wherein the remaining sidewalls of the semiconductor substrate are partially covered by the fin word lines. The body line is grounded to direct accumulated charge out of the semiconductor substrate, thereby reducing floating body effects in the memory cell.

Embodiments of the present disclosure provide a memory device and a vertical fin field effect transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, a plurality of semiconductor fins on the bit line and embedded in the word line, a body line physically contacting one of sidewalls of each of the semiconductor fins, and an insulating layer embedding the body line. The body line is grounded to direct the accumulated charges out of the semiconductor fins, thereby reducing the floating body effect in the memory cell.

The invention provides a preparation method of a deep trench isolation structure, the structure and a semiconductor device, and relates to the technical field of semiconductor devices. The preparation method of the deep trench isolation structure comprises the following steps: providing a substrate; the substrate comprises a bottom layer, a buried oxide layer and an active layer which are stacked in sequence. A first groove is formed in the substrate, the first groove penetrates through the active layer, and the groove bottom of the first groove ends at the buried oxide layer. Forming a second groove communicated with the first groove in the buried oxide layer; the second groove penetrates through the buried oxide layer. And forming doped polycrystalline silicon on the side wall of the second groove. Forming an oxide filling the first groove and the second groove; wherein the doped polycrystalline silicon in the second groove is relatively positioned on the periphery of the oxide in the second groove. According to the preparation method, the self-heating effect and the floating body effect of the SOI device can be effectively inhibited.

Methods for forming floating body effect attenuated 3D dynamic random access memory elements are disclosed herein. In one example, a method may include forming a plurality of layers stacked in a first direction, the plurality of layers including gate layers formed on a first oxide layer, and source / drain (S / D) layers between a set of gate oxide layers. The set of gate oxide layers may be formed over the gate layer, and the S / D layer may include a source and a drain on opposite sides of the body. The method may also include forming a doped layer over the source electrode and the drain electrode.

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure comprises a semiconductor layer which comprises a first end part, a second end part and a middle part located between the first end part and the second end part, wherein the first end part and the second end part are integrally formed; in the first section, the middle part is annular; the second end part comprises a first extension part and a second extension part; the first extension part extends along a first direction and a second direction; the second extension part extends along the third direction and is connected with the middle part and the first extension part; in the first section, the first extending part is in a solid closed shape, the second extending part is annular, and the size of the first extending part is larger than the outer side overall size of the second extending part. According to the invention, the floating body effect can be inhibited.

Semiconductor devices and methods of manufacturing the same are described. The methods form a 3D DRAM architecture that includes a semiconductor isolation bridge, eliminating a floating body effect. The method includes forming an epitaxial layer in a deep trench isolation opening and creating a semiconductor isolation bridge between adjacent deep trench isolation openings.

The invention relates to a complementary ring channel MOS transistor and a preparation method thereof, a semiconductor device and electronic equipment. The complementary ring channel MOS transistor comprises a first MOS transistor and a second MOS transistor, wherein the first MOS transistor comprises a gate structure and a first surrounding structure, and the second MOS transistor comprises a gate structure and a second surrounding structure. According to the invention, the first surrounding structure and the second surrounding structure surround the outer surface of the gate structure, so that the circuit density is greatly improved, and the chip area in the subsequent process is greatly saved; meanwhile, the preparation process is simple, the production cost is low, the floating body effect does not exist, and batch production is facilitated.

NEDMOS FETs capable of withstanding high drain voltages while attaining high device reliability, and which remediate the floating body effect using one of several novel architectures. Each architecture provides a P or P+ pathway between the body of a NEDMOS device and a device-wide P+ body tie. The P / P+ pathway enables collection and conveyance of holes over to the device-wide body ties, resulting in elimination or substantial mitigation of the floating body effect. Use of a body tie spanning the width of the gate conductive layer (e.g., polysilicon) provides a number of benefits without reducing the effective width of the gate structure or increasing the gate capacitance CGG. Thus, one aspect of the present invention encompasses a MOSFET including a pathway between a body of the MOSFET and a device-wide body tie, wherein the pathway enables collection and conveyance of holes from the body over to the device-wide body tie.

This technology includes a vertical cell array transistor (VCAAT) with improved floating body effect. The array includes one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The array includes one or more channels extending vertically substantially orthogonal to the first and second horizontal directions such that the bit lines intersect the source / drain regions of the multiple channels and the word lines intersect the gate regions of the multiple channels. The array includes a case where the source / drain region has a first section adjacent to the source / drain junction and a second section adjacent to the channel body, and the first section has a higher doping concentration than the second section.

The invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises an SOI substrate, and the SOI substrate comprises a bottom substrate, a buried oxide layer and a top semiconductor layer which are stacked in sequence; the isolation structure is embedded in the SOI substrate so as to divide the SOI substrate into device regions; the isolation structure comprises a first STI structure and a second STI structure, the first STI structure extends from the top semiconductor layer to be in contact with the buried oxide layer, and the second STI structure extends from the top semiconductor layer to the bottom substrate; and a substrate contact connected with the bottom substrate through the first STI structure. Therefore, the substrate contact of the device region is isolated from the substrate contact of another adjacent device region through the isolation structure, so that the semiconductor structure provided by the invention can be respectively pressurized and controlled, and the floating body effect of the semiconductor structure is weakened while the uniformity between the semiconductor structures is improved.

The present technology includes a vertical cell dynamic random access memory (DRAM) array access transistor with improved hole distribution. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending in a vertical direction orthogonal to the first direction and the second horizontal direction such that the plurality of bit lines intersect source / drain regions of the plurality of channels and the plurality of word lines intersect gate regions of the plurality of channels. Further, the array includes a p-doped bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, where the first channel is spaced apart from the second channel in a row extending in the second horizontal direction.

This specification discloses a method for forming a three-dimensional dynamic random access memory device with reduced floating body effects. In one embodiment, the method may include forming a plurality of layers stacked in a first direction, the plurality of layers including a gate layer formed on a first oxide layer and source / drain (S / D) layers between the series of gate oxide layers. The series of gate oxide layers may be formed on top of the gate layer, and the S / D layers may include a source and a drain located on opposite sides of the body. The method may further include forming doped layers on top of the source and drain.

Devices and methods include a partially depleted silicon on insulator device that comprises a transistor. The transistor comprises a gate terminal. The transistor also includes a first non-gate terminal and a second non-gate terminal. Moreover, the first non-gate terminal is coupled to a body of the partially depleted silicon on insulator device.

Embodiments of the present disclosure provide a memory device and a vertical fin-gate transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, and a semiconductor substrate on the bit line. The word line includes a plurality of fin type word lines and a common word line connecting the fin type word lines, where the fin type word lines partially cover a first sidewall of the semiconductor substrate. The memory cell also includes a body line physically contacting a second sidewall of the semiconductor substrate opposite to the first sidewall of the semiconductor substrate, and an insulating layer embedding the body line. The body line is grounded to direct the accumulated charges out of the semiconductor substrate, thereby reducing the floating body effect in the memory cell.

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure includes a semiconductor layer including a first end portion, a second end portion, and an intermediate portion between the first end portion and the second end portion; in a first cross section intersecting with the extending direction of the semiconductor layer, the middle part is annular, and the size of the outer side outline of the middle part is smaller than that of the outer side outline of the first end part and / or smaller than that of the outer side outline of the second end part. According to the invention, the purpose of inhibiting the floating body effect can be achieved.

Novel NEDMOS and / or LDMOS FET integrated circuit structures that reduce or eliminate the floating body effect by reducing the built-in voltage Vbi of the device. Reduction of Vbi includes adding a source-side structure that includes a "Vbi Reduction Material" (VRM) layer. VRM has a bandgap less than the bandgap of Si and, for an N-type device, a valence band that is higher than the valence band of the body material. The low Vbi of the VRM layer on the source-side of a MOSFET device that would otherwise exhibit a floating body effect allows significantly freer movement of holes from the body of the device towards the source region, thus increasing body hole collection efficiency, and significantly reduces the floating body effect.

Embodiments of the present disclosure provide a memory device and a vertical fin-gate transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, and a semiconductor substrate on the bit line. The word line includes a plurality of fin type word lines, a fin connector connecting the fin type word lines, and a common word line on the fin connector. The memory cell also includes a body line physically contacting one of sidewalls of the semiconductor substrate and an insulating layer embedding the body line, where the fin type word lines partially cover others of the sidewalls of the semiconductor substrate. The body line is grounded to direct the accumulated charges out of the semiconductor substrate, thereby reducing the floating body effect in the memory cell.

Embodiments of the present disclosure provide a memory device and a vertical fin gate transistor. A memory device includes a memory cell, wherein the memory cell includes a bit line, a word line over the bit line, and a semiconductor substrate on the bit line. The word lines include a plurality of fin-type word lines and a common word line connecting the fin-type word lines, wherein the fin-type word lines partially cover a first sidewall of the semiconductor substrate. The memory cell also includes a body line physically contacting a second sidewall of the semiconductor substrate opposite the first sidewall of the semiconductor substrate, and an insulating layer covering the body line. The body line is grounded to direct accumulated charge out of the semiconductor substrate, thereby reducing floating body effects in the memory cell.

Embodiments of the present disclosure provide a memory device and a vertical fin field effect transistor. The memory device includes a memory cell, wherein the memory cell includes a bit line, a word line over the bit line, a plurality of semiconductor fins on the bit line and embedded in the word line, a body line physically contacting one sidewall of each semiconductor fin, and an insulating layer covering the body line. The body line is grounded to direct accumulated charge out of the semiconductor fins, thereby reducing floating body effects in the memory cell.

Devices (180) and methods (200) include a partially depleted silicon on insulator device (50) that comprises a transistor. The transistor comprises a gate terminal (106). The transistor also includes a first non-gate terminal (108) and a second non-gate terminal (110). Moreover, the first non-gate terminal (108) is coupled to a body (194) of the partially depleted silicon on insulator device (50).

The present technology includes a vertical cell array transistor (VCAAT) with an improved floating body effect. The arrays include one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The array includes one or more channels extending in a vertical direction substantially orthogonal to the first direction and the second horizontal direction such that the bit lines intersect source / drain regions of the plurality of channels and the word lines intersect gate regions of the plurality of channels. The array includes a source / drain region having a first section adjacent the source / drain junction and a second section adjacent the channel body, wherein the doping concentration of the first section is greater than the doping concentration of the second section.

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a bottom semiconductor layer; the buried dielectric layer is located on the bottom semiconductor layer; the transistor structure is located on the buried dielectric layer; the first insulation isolation structure is located on the side face of the transistor structure, and the first insulation isolation structure extends downwards to the buried dielectric layer; the side face of the conductive structure is surrounded by the first insulation isolation structure, the bottom of the conductive structure penetrates through the buried dielectric layer to be electrically connected with the bottom semiconductor layer, and the conductive structure extends upwards to lead out the potential of the bottom semiconductor layer; and the second insulating isolation structure is positioned on the side surface of the transistor structure and extends downwards to the buried dielectric layer. The electric potential of the bottom semiconductor layer is led out to the upper surface of the device through the conductive structure, so that the influence of the floating body effect is eliminated. And the conductive structure is surrounded by the first insulation isolation structure, and the second insulation isolation structure is arranged to further enhance the isolation effect, so that the withstand voltage of the device is ensured.

The application provides a double-gate MOSFET transistor and a forming method thereof. The forming method comprises the following steps: providing a first substrate and a second substrate, the second substrate is provided with two protruding structures which are arranged at intervals; performing an N-type ion implantation process on the protruding structures; performing a planarization treatment on the second insulating layer, and performing a bonding treatment on the first substrate and the second substrate, the first insulating layer is arranged towards the second insulating layer; forming a source electrode and a drain electrode in the side of the second substrate which is away from the first substrate, and forming a floating gate on the second substrate between the source electrode and the drain electrode, the source electrode and the drain electrode are arranged in overlap with a protruding structure respectively. The application optimizes the electric field intensity and the hole concentration of the drain electrode through the N-type doped protruding structure. The N-type ion implantation process makes the thermal conductivity of the protruding structure higher than that of the first insulating layer and the second insulating layer, and effectively improves the floating body effect and the self-heating effect of the double-gate MOSFET transistor.

MOSFET structures and corresponding methods that mitigate or eliminate the floating body effect in a MOSFET while reducing parasitic gate-source capacitance CGS and improving the FT of the device. This invention addresses the floating body effect by reshaping a conductive body tie region and eliminating or reducing any body tie extension at the source side of a MOSFET to improve CGS. One embodiment includes a body region and a body tie region implanted within a source region in direct contact with a first side of the body region without a body tie extension. Another embodiment includes a body region, a gate structure including a drain-side extension, and a body tie region implanted within a source region in direct contact with a first side of the body region, wherein the drain-side extension of the gate structure is sized to block implantation of the body tie region within a drain region.

A partially depleted silicon-on-insulator (PDSOI) transistor and a method for fabricating the PDSOI transistor are disclosed. In PDSOI transistor, a first space is provided between a bottom surface of a source and a top surface of a buried oxide layer, and a second space is provided between a bottom surface of a drain and the top surface of the buried oxide layer. Moreover, a source contact structure extends into the source and a third space is provided between the source contact structure and the top surface of the buried oxide layer. With this configuration, electric charge can be picked up from the body region through the third space and the source contact structure, thereby avoiding the problem of the floating body effect (FBE) and enabling the PDSOI transistor to have improved quality and reliability.

An NMOS device structure and a forming method thereof, the device comprising: an SOI substrate, the SOI substrate comprising a top silicon layer, a source region, a drain region and a body contact region distributed in the top silicon layer, the source region and the drain region arranged along a first direction, the body contact region located at least on one side of the top silicon layer between the source region and the drain region along a second direction, the first direction being perpendicular to the second direction; a first isolation structure located at least between the top silicon layer between the source region and the drain region and the body contact region and penetrating the top silicon layer, and the first isolation structure partially overlapping with a gate structure, two ends of the first isolation structure along the first direction being a first isolation end and a second isolation end respectively, the first isolation end being located between the source region and the drain region, and the second isolation end being flush with or exceeding a boundary of the body contact region in the first direction; and the gate structure being located on a surface of the top silicon layer, the source region and the drain region being located on two sides of the gate structure respectively, and the first isolation structure partially overlapping with the gate structure. The parasitic capacitance is reduced and the floating body effect is inhibited.

The present technology includes vertical cell array transistor (VCAAT) with improved floating body effect. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source / drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the source / drain region has a first section adjacent to a source / drain junction and a second section adjacent to a channel body, where the first section has a doping concentration that greater than a doping concentration of the second section.

The invention discloses a transistor structure, a semiconductor structure and a preparation method thereof, and the transistor structure comprises a dielectric structure which is provided with a first side wall parallel to a first direction; the first source and drain electrode structure and the second source and drain electrode structure are located on the two sides of the dielectric structure in the first direction respectively, the first source and drain electrode structure is provided with a second side wall parallel to the first direction, and the second source and drain electrode structure is provided with a third side wall parallel to the first direction; the gate stack surrounds the first side wall of the dielectric structure, a part of the second side wall of the first source and drain electrode structure and a part of the third side wall of the second source and drain electrode structure, the gate stack comprises a channel layer, a gate dielectric layer and a gate conductive layer which are stacked in sequence, and the channel layer is in contact with the first source and drain electrode structure and the second source and drain electrode structure. The transistor structure at least can improve the floating body effect.

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a bottom semiconductor layer; the buried dielectric layer is located on the bottom semiconductor layer; the transistor structure is located on the buried dielectric layer; the insulation isolation structure is located on the side face of the transistor structure, and the insulation isolation structure extends downwards to the buried dielectric layer; the side surface of the conductive structure is surrounded by the insulating isolation structure, the bottom of the conductive structure penetrates through the buried dielectric layer so as to be electrically connected with the bottom semiconductor layer, and the conductive structure extends upwards to lead out the potential of the bottom semiconductor layer. The electric potential of the bottom semiconductor layer is led out to the upper surface of the semiconductor device through the conductive structure, so that the influence of the floating body effect is eliminated. And the conductive structure is surrounded by the insulating isolation structure arranged on the side surface of the transistor structure, so that the influence of the conductive structure on the isolation effect is reduced, and the withstand voltage of the device is ensured.