49 results about "Power integrated circuits" patented technology

The invention discloses a high-side driving circuit applied to a gallium nitride fully-integrated half-bridge power chip, and belongs to the field of power integrated circuits. The circuit comprises an input stage circuit, an anti-VSW negative voltage shift circuit and a low-power-consumption output stage circuit. Wherein the anti-VSW negative voltage shift circuit guarantees correct transmission of a signal under a VSW node negative voltage condition through a negative voltage transmission structure, and in addition, the anti-VSW negative voltage shift circuit can generate an advanced pulse control signal for the low-power-consumption output stage circuit; and the low-power-consumption output stage circuit only charges the bootstrap capacitor in a short time before the output state is changed through the advanced pulse control signal, so that the problem of high power consumption of a capacitor charging branch in a traditional scheme is greatly relieved. According to the invention, the signal transmission reliability of the high-side driving circuit under the negative-voltage working condition is remarkably improved, the static power consumption is effectively reduced, and the high reliability and low power consumption requirements of the gallium nitride fully-integrated half-bridge driving chip on the high-side access are considered.

The present invention belongs to the field of power semiconductor technology and relates to a lateral enhancement-mode gallium oxide field-effect transistor with an integrated freewheeling diode. When the gate-source voltage is zero, the work function difference between the gate-source metal and the gallium oxide semiconductor depletes the conductive channel, realizing a normally-off enhancement-mode device. During forward conduction, the voltage applied to the gate is greater than the threshold voltage, turning the transistor on; when the source voltage is zero, the work function difference between the source metal and the gallium oxide semiconductor depletes the conductive channel, turning the integrated diode off. During reverse freewheeling, the applied source voltage narrows the depletion region, turning the integrated diode on with a low turn-on voltage; when the source voltage is further increased, a high-concentration electron accumulation layer forms on the channel sidewalls, achieving a low on-state voltage drop. Compared to vertically separated field-effect transistors that need to be packaged into a chip or module with a freewheeling diode, the lateral power device of the present invention is easy to integrate, and the field-effect transistor and integrated diode processes are compatible, which facilitates widespread application in power integrated circuits and reduces parasitic parameters and module volume.

To provide a high-voltage, high-current power integrated circuit semiconductor device that can achieve low loss, small chip area, and high reliability by eliminating the snap-back phenomenon characteristic of reverse-conducting semiconductor elements.SOLUTION: An Si power integrated circuit semiconductor device chip 200 consists of an element-integrated substrate 201 in which a semiconductor chip body with dielectric isolation integrated circuit structure is laid out with single-crystal islands containing integrated circuit components in an isolation area 217 and an element support substrate 202 with both support and conductive path functions for the element-integrated substrates laminated on top of each other, and the element-integrated substrate is provided with a main functional part of vertical semiconductor element in a predetermined single-crystal island and a drain 205 or a collector 204 by removing a dielectric insulation isolation film 206 at the bottom of the single-crystal island and laminated with the element support substrate to form the vertical semiconductor element.SELECTED DRAWING: Figure 2

The utility model belongs to the technical field of chip packaging, and discloses a high-power integrated circuit chip packaging device which comprises a feeding structure, a machine body, a control unit, a suction unit, a feeding structure and a fixing structure. The feeding structure comprises a tray, a guide part and a transmission part, the guide part is connected to the machine body and used for driving the transmission part to move, the transmission part is connected to the guide part and used for driving the tray to move, the tray is connected to the transmission part and used for bearing chips, and the control unit is connected to the machine body and used for controlling the packaging device to operate. When the chip is packaged, the rack meshed with the gear is moved, so that the end part of the clamping block is attached to the end part of the chip, the chip is fixed on the slide holder, the position deviation of the chip during packaging is effectively avoided, and the packaging quality and the product percent of pass are greatly improved.

The application discloses a diode load type high-voltage level shift circuit with anti-negative voltage capability, and belongs to the technical field of power electronics and power integrated circuits. The application comprises a narrow pulse generation circuit, a level shift module, a cross-coupled current mirror module, a current-voltage conversion module and an RS latch. The narrow pulse generation circuit converts an input signal into two narrow pulse signals, controls the conduction and turn-off of an LDMOS tube in the level shift module, the cross-coupled current mirror module cross-mirrors the conduction current of the LDMOS tube, and outputs a clean and stable narrow pulse level signal through the current-voltage conversion module; and the RS latch restores the narrow pulse signal into a normal signal. The application adopts a diode load to replace a traditional resistor, reduces the sensitivity of an output voltage to resistance, avoids the breakdown of a gate in a later stage, and significantly improves the anti-negative voltage capability through optimization of a current path, and has the advantages of simple structure, high reliability, good temperature stability and the like.

The present application relates to a kind of high low side double mechanism fusion's IGBT short circuit protection circuit, it is related to power integrated circuit design technical field, the circuit includes high side desaturation short circuit detection circuit, low side resistance short circuit detection circuit, high side fault processing module, low side fault processing module and two-stage collaborative soft turn-off circuit;The signal output end of high side desaturation short circuit detection circuit is electrically connected to the input end of high side fault processing module and the first trigger input end of two-stage collaborative soft turn-off circuit respectively;The signal output end of low side resistance short circuit detection circuit is electrically connected to the input end of low side fault processing module and the second trigger input end of two-stage collaborative soft turn-off circuit respectively;The output end of high side fault processing module and the output end of low side fault processing module are electrically connected to the control input end of two-stage collaborative soft turn-off circuit;Two-stage collaborative soft turn-off circuit is electrically connected to high side IGBT gate and low side IGBT gate.The effect of considering turn-off speed and peak suppression is realized.

The present invention proposes a method for manufacturing a power integrated circuit, comprising: growing an epitaxial layer of a second type of doped semiconductor with different concentrations on a silicon substrate of a first type of doped semiconductor, and producing a gate oxide layer on the epitaxial layer; determining the doping concentration of the first type of doped semiconductor in different functional areas of the epitaxial layer according to the design of the components and the integrated circuit, performing photolithography and ion implantation on the gate oxide layer according to the doping concentration, defining first type doped semiconductor regions with different concentrations on the epitaxial layer and forming low concentration regions and high concentration regions through annealing, forming a gate pattern on the gate oxide layer through photolithography and etching; depositing a refractory metal layer on the gate oxide layer, and performing photolithography and etching on the refractory metal layer to form ohmic contact windows for different functional areas; forming silicide on the silicon substrate, depositing an ohmic contact metal layer, and photolithography and etching the ohmic contact metal layer to form component and circuit interconnection and circuit isolation of a high-power silicon integrated circuit.

The application provides a three-dimensional integrated power integrated circuit thermal management method and system, relates to the technical field of power integrated circuits, and comprises the following steps: receiving a running index sequence of a target power integrated circuit in a preset monitoring window and performing running state feature analysis; traversing embedded temperature sensors of a chip layer set to collect temperature distribution and identify hot spot regions; combining circuit running working condition features and the hot spot region set to perform thermal management strategy analysis, obtaining a thermal management strategy, and using a plurality of MOSFET switching circuits to adaptively control and manage a plurality of power output branches. The application solves the technical problem that, in the prior art, due to the fact that the power integrated circuit is dominated by long thermal paths and horizontal heat dissipation, local regions are overheated and thermal management response is lagged, thereby affecting the stability of the circuit, and the stability of the power integrated circuit is improved by using a MOSFET switching circuit array to realize thermal sensing power path dynamic scheduling.

Embodiments relate to flip-flops for a low power integrated circuit (IC) in a standard cell library. A master stage flip-flop includes multistage cascaded inverters to generate a buffered data output for providing input to a slave stage flip-flop. A transistor bridge circuit is used for sharing a clock signal between the master stage flip-flop and the slave stage flip-flop. The slave stage flip-flop is configured to generate a final output using the generated buffered output from the master stage flip-flop.

The invention relates to the field of circuit board technology and integrated circuit manufacturing, and particularly discloses a preparation process of a multilayer circuit board with a thermoelectric separation substrate, which comprises the following steps of: preparing and laminating an FR4 multilayer board at one time; and finally, through secondary pressing, the red copper plate boss is accurately embedded into the groove of the FR4 plate and is electrically connected with the circuit bonding pad, so that a thermoelectric separation integrated structure is realized. The method is suitable for packaging and heat dissipation requirements of high-power integrated circuits and semiconductor devices, and particularly can be used for producing high-density and high-heat-dissipation circuit modules in semiconductor device special equipment such as a special photoetching machine and an etching machine. The obtained product has the high-density wiring advantage of the FR4 multilayer board and the high heat dissipation performance of the metal substrate, the lowest thermal resistance path to the heat dissipation substrate is achieved through direct connection of the bosses, meanwhile, the reliability and the electrical insulation performance of the overall structure are guaranteed, the stability of electronic equipment under the high-temperature and high-power working conditions is remarkably improved, and the service life of the electronic equipment under the high-temperature and high-power working conditions is remarkably prolonged.

A low-power lightning current waveform acquisition circuit belongs to the technical field of lightning protection, comprising a protection circuit, an integration circuit, a signal conditioning circuit, a trigger circuit, a microprocessor circuit, a storage circuit, a communication circuit and a power conversion circuit, the protection circuit is electrically connected with a lightning current signal sensor Rogowski coil and the integration circuit respectively, the integration circuit is electrically connected with the signal conditioning circuit and the trigger circuit respectively; the signal conditioning circuit and the trigger circuit are electrically connected with the microprocessor circuit; the storage circuit is electrically connected with the microprocessor circuit; the communication circuit is electrically connected with the microprocessor circuit; the power conversion circuit is electrically connected with the integration circuit, the signal conditioning circuit, the trigger circuit, the microprocessor circuit, the storage circuit and the communication circuit. The low-power function circuit composed of the STM32L471 low-power processor and other low-power integrated circuits realizes the acquisition, storage and transmission of the lightning current waveform.

A high power density integrated circuit module packaging method and its packaging structure belong to the field of microelectronic device packaging technology. In the inner cavity assembly area of the ceramic packaging shell, the chip assembly area is provided with a heat sink area and a functional area, the heat sink area and the functional area are provided as flat bottom pits, the power of the chips in the circuit is graded, a two-stage or more stepped structure is adopted, the chips are distributed from deep flat bottom pits to shallow flat bottom pits according to the power from large to small, the heat sink area is lower than the functional area, the power type chip with large power is assembled in the heat sink area, and the functional type chip with small power is assembled in the functional area. A metal through hole penetrating through the ceramic base body is arranged below the heat sink area or the functional area to realize shortest path heat dissipation and shortest path internal and external electrical connection. The problems of low power density, low integration, large parasitic impedance and parasitic inductance, low reliability and high application cost of the existing high-power devices (assemblies or modules) are solved. It is widely used in the field of high-reliability power integrated circuit module integration technology.

The application relates to a temperature control method, device, equipment and medium for dynamic burn-in of an integrated circuit, wherein the method comprises the following steps: in the process of dynamic burn-in of a to-be-tested integrated circuit, according to a burn-in temperature control strategy, the burn-in temperature of the to-be-tested integrated circuit in the burn-in process is controlled until a preset burn-in time length is reached; wherein the burn-in temperature control strategy comprises the following steps: according to a first temperature value and a target temperature value of the to-be-tested integrated circuit, a first control strategy of the burn-in temperature is determined; according to a second temperature value, a power consumption value and a preset temperature-power consumption mapping relationship model of the to-be-tested integrated circuit, a second control strategy of the burn-in temperature is determined; the second temperature value is a temperature value of the to-be-tested integrated circuit obtained after the first control strategy is adjusted. In this way, the trend of temperature rise or fall of a high-power integrated circuit can be predicted in advance, so that the controller can send a temperature rise or fall control signal in advance, and compared with a traditional method based on temperature regulation and control only, the temperature control precision is higher.

The application provides an adaptive power regulation method and system for a power integrated circuit, and relates to the technical field of power regulation. The method comprises the following steps: dividing the power integrated circuit and outputting multiple power domains; constructing multiple power feature vector sets according to power requirement data of each power domain, performing Gaussian mixture model clustering, and constructing a complementarity matrix based on multiple clustering results; establishing a pairing priority list according to the complementarity matrix, obtaining a complementary power regulator pair based on the pairing priority list; configuring an adaptive power regulator for the complementary power regulator pair, and performing adaptive power regulation on each complementary power regulator pair based on an adaptive power switching regulation logic model. The application can solve the technical problem of poor power regulation stability of the power integrated circuit in the prior art, and achieve the technical effect of improving the power regulation stability.

A driving circuit, for driving a touch display panel, includes a controller, a first diode, a first capacitor, a second diode and a second capacitor. The controller is configured to provide a first modulation signal and a second modulation signal. The first diode is coupled between a power integrated circuit and a first node for providing a low gate output signal to the touch display panel. The first capacitor is coupled between the controller and the first node. The second diode is coupled between the power integrated circuit and a second node for providing a high gate output signal to the touch display panel. The second capacitor is coupled between the controller and the second node. During a touch period, the controller is configured to provide the first modulation signal with toggling voltage levels, and provide the second modulation signal with toggling voltage levels.

The invention discloses a high-precision floating power rail circuit, and relates to the technical field of high-voltage power integrated circuits, and the circuit comprises a sampling circuit, an error correction circuit and an adjustment circuit, the sampling circuit is connected between an input high voltage VDD and a floating power rail voltage VF, and is used for sampling the voltage difference between the VDD and the VF, and outputting a sampling signal Vsense; the input end of the error correction circuit is connected to the output end of the sampling circuit and the standard reference voltage Vref, and the error correction circuit is used for comparing the sampling signal Vsense with the standard reference voltage Vref and generating a control signal Vgate according to a comparison result; the control end of the adjusting circuit is connected to the output end of the error correction circuit, the main path of the adjusting circuit is connected between the floating power rail voltage VF and the ground, and the adjusting circuit is used for adjusting the floating power rail voltage VF according to the control signal Vgate, so that the difference between the VDD and the VF is kept at a fixed value, and the high-precision and stable floating power rail voltage can be generated.

This invention discloses a high-precision floating power rail circuit, relating to the field of high-voltage power integrated circuit technology. The circuit includes: a sampling circuit, an error correction circuit, and an adjustment circuit. The sampling circuit is connected between the input high voltage VDD and the floating power rail voltage VF, used to sample the voltage difference between VDD and VF and output a sampling signal Vsense. The error correction circuit has its input connected to the output of the sampling circuit and a reference voltage Vref, used to compare the sampling signal Vsense with the reference voltage Vref, and generate a control signal Vgate based on the comparison result. The adjustment circuit has its control terminal connected to the output of the error correction circuit, and its main path is connected between the floating power rail voltage VF and ground, used to adjust the floating power rail voltage VF according to the control signal Vgate, so that the difference between VDD and VF remains a fixed value, generating a high-precision and stable floating power rail voltage.

The invention provides an epitaxial method for improving crystal point defects on the back surface of an epitaxial wafer, and the method mainly comprises the steps: carrying out the epitaxy through employing Poly and LTO in sequence, and carrying out the epitaxy through employing a perforated graphite disc, and obtaining an 8-inch epitaxial wafer. The epitaxial wafer can be used for a power semiconductor device, a photoelectric semiconductor device, a radio frequency and microwave device and a power integrated circuit. The method has the advantages that the perforated graphite disc is used for epitaxy, reaction gas entering the back of the substrate in the epitaxy process can be discharged to the lower part of the reaction chamber along the holes in the surface of the graphite disc, aggregation reaction on the back of the substrate is greatly reduced, and the crystal point defects on the back of the epitaxial wafer are greatly reduced; besides, in the epitaxy process, HCl gas is introduced into the lower end of the graphite plate, the HCl gas enters the back surface of the substrate through holes of the graphite plate to achieve the effect of etching crystal points on the back surface, and meanwhile, the HCl serving as a by-product in the epitaxy process can also achieve the effects of inhibiting the chemical reaction of SiHCl3 and H2 and reducing the generation of crystal point defects on the back surface.

The invention discloses an LDO circuit with a temperature compensation function for a GaN power integrated circuit. The LDO circuit comprises a reference voltage source, a TRK voltage source and a differential operational amplifier circuit with negative feedback. The reference voltage source is used for generating reference voltage with stable temperature; the input end of the TRK voltage source is connected with the output end of the reference voltage source, and the TRK voltage source is used for generating voltage offset matched with GaN HEMT threshold voltage drift according to temperature changes. And the input end of the differential operational amplifier circuit with negative feedback is connected with the output end of the TRK voltage source and is used for adjusting the voltage of the output end according to the input voltage so as to realize voltage-stabilized output. The circuit is simple in structure, high in temperature compensation precision and suitable for local voltage stabilization power supply of low-voltage bias, driving and control modules in a GaN power chip, and the reliability and the temperature adaptability of a system can be remarkably improved.

The preferred embodiment of the present invention relates to an ultra low power integrated circuit, a power saving method for integrated circuit and a touch display driving circuit using the same. The ultra-low power integrated circuit comprises two functional blocks. The first functional block is disposed within the first power ring and stores configuration settings. The power consumption control block is disposed within the second power ring, which is constantly powered on. When switching from normal mode to low power mode, a series of procedures are executed: First, the power consumption control block temporarily stores the configuration settings of the first functional block and cuts off its power supply; it then reduces its own clock frequency and waits for a preset period of time; after that, it increases the clock frequency, powers on the first functional block, and loads the configuration settings; the first functional block then performs a wake-up determination, and if it is not to be woken up, the previous steps are repeated, effectively saving power.

This application provides a level shifter and a high-voltage half-bridge driver, belonging to the field of high-voltage power integrated circuit technology. The level shifter includes a first capacitor driving module, an input logic edge detection module, a bootstrap capacitor module, an active control module, a first isolation capacitor module, a second capacitor driving module, a second isolation capacitor module, a first pulse sensing module, a second pulse sensing module, and a latch output module. The first capacitor driving module generates a first pulse signal; the first pulse sensing module generates a fourth pulse signal; the second pulse sensing module generates a seventh pulse signal; the latch output module generates a target pulse signal and sends a feedback signal when the voltages of the fourth and seventh pulse signals are both greater than the target high voltage, so that the voltages of the fourth and seventh pulse signals are both less than or equal to the target high voltage. This application can reduce the signal transmission delay and power consumption of the level shifter and improve reliability.

Disclosed herein is a high-performance thermal chuck for enhanced thermal management of high-power integrated circuit (IC) devices. The disclosed high-performance thermal chuck provides active heating and cooling for post-manufacture device testing. A high-performance heatsink comprises microfluidic channels in a high thermal conductivity silicon carbide (SiC) body for providing enhanced active cooling of an IC device. A refractory heating element is embedded between an integrated heat spreader comprising diamond and the heatsink for providing active heating. The integrated heat spreader is bonded to the heatsink. Closely matched coefficients of thermal expansion between the diamond heat spreader and the heatsink mitigate thermally-induced warpage.

A semiconductor package contains a first semiconductor die, electrically coupled to a plurality of leads around a perimeter of the semiconductor package via a molded interconnect. The molded interconnect comprises a plurality of embedded interconnects in a first mold compound which electrically couple the plurality of bond pads of the first semiconductor die to the plurality of leads of the semiconductor package. The molded interconnect may have a greater cross-sectional area at a given pitch compared to a similar wire bonded semiconductor package and allow advantageous thermal management of the semiconductor package compared to other electrical coupling techniques. The molded interconnect may allow small high-power integrated circuits to be packaged with a package footprint which is smaller than would otherwise be available.

The present application belongs to the technical field of power integrated circuit, and particularly relates to a method for establishing and simulating a lateral high-voltage device equivalent circuit model. The circuit model comprises: a field effect transistor; a drain resistance, one end of which is connected to the drain of the field effect transistor and the second end of which is used as the drain of a high-voltage device; a source resistance, one end of which is connected to the source of the field effect transistor and the second end of which is used as the source of a high-voltage transistor; a body diode, which is connected in series with a diode cathode through a parallel network of a cathode resistance and an inductor, the anode of which is connected to the source of the high-voltage transistor, and the other end of the cathode resistance is connected to the drain of the high-voltage device; a first current source, one end of which is connected to the drain of the high-voltage device and the other end of which is connected to the source of the high-voltage device; and a simulation model, which uses a voltage control resistance value relationship to correct the resistance value of an external resistance. Compared with a traditional model, the resistance expression of the present application has a clear physical meaning, effectively improves the simulation accuracy of the lateral high-voltage device model, and has better convergence.

The invention provides a self-adaptive power regulation and control method and system for a power integrated circuit, and relates to the technical field of power regulation and control, and the method comprises the steps: dividing the power integrated circuit, and outputting a plurality of power domains; constructing a plurality of power feature vector sets according to the power demand data of each power domain, performing Gaussian mixture model clustering, and constructing a complementarity matrix based on a plurality of clustering results; establishing a pairing priority list according to the complementarity matrix, and obtaining a complementary power regulator pair based on the pairing priority list; and configuring adaptive power regulators for the complementary power regulator pairs, and performing adaptive power regulation on each complementary power regulator pair based on the adaptive power switching regulation logic model. According to the invention, the technical problem of poor power regulation and control stability of a power integrated circuit in the prior art can be solved, and the technical effect of improving the power regulation and control stability is achieved.

The invention relates to a (6, 5) chiral carbon nanotube field effect transistor for inhibiting interband tunneling and a preparation method thereof, and belongs to the technical field of semiconductors. According to the method, a (6, 5) chiral carbon nanotube dispersion liquid with high purity (greater than 95%) and high concentration (increased to 3 times) is prepared in a single toluene solvent on the basis of a PFO-BPy polymer oriented coating and multi-stage circulating centrifugal separation strategy; a uniform and compact film is formed on a substrate with a gate dielectric layer in a self-assembly mode, and an isolation channel is defined through photoetching and etching processes; and finally preparing a source electrode and a drain electrode to complete device construction. The obtained transistor shows excellent electrical properties, the inter-band tunneling effect of the transistor is remarkably suppressed, the off-state current is lower than 10 <-11 > A, the switching ratio is higher than 106, the sub-threshold swing is kept stable under different voltages, the transistor is remarkably superior to a traditional device, and the transistor is suitable for an ultra-low power consumption integrated circuit.

The invention relates to a temperature control method and device for dynamic aging of an integrated circuit, equipment and a medium, and the method comprises the steps: controlling the aging temperature of the to-be-tested integrated circuit in the aging process according to an aging temperature control strategy in the dynamic aging process of the to-be-tested integrated circuit until a preset aging duration is reached; wherein the burn-in temperature control strategy comprises the following steps: determining a first control strategy of the burn-in temperature according to a first temperature value and a target temperature value of the integrated circuit to be tested; determining a second control strategy of the aging temperature according to a second temperature value and a power consumption value of the to-be-tested integrated circuit and a preset temperature-power consumption mapping relation model; the second temperature value is the temperature value of the to-be-tested integrated circuit obtained after adjustment based on the first control strategy. Thus, the temperature rising or cooling trend of the high-power integrated circuit can be pre-judged in advance, the controller sends out a temperature rising or cooling control signal in advance, and compared with a traditional method only based on temperature regulation and control, the temperature control precision is higher.

The invention discloses a gallium integrated circuit chip and a preparation method thereof, and belongs to the technical field of semiconductor device integration. The gallium integrated circuit chip comprises a basic circuit module formed by connecting a main pipe device and an auxiliary pipe device, a drain electrode of the auxiliary pipe device is connected with a grid electrode of the main pipe device, and source electrodes of the auxiliary pipe device and the main pipe device are connected together; grid electrodes of the main tube and the auxiliary tube receive inverted input signals; when the main pipe generates grid voltage ringing due to coupling of adjacent circuit switches, the conducted auxiliary pipe provides a discharge path for grid charges of the main pipe, and misconduction is restrained. Preferably, the auxiliary tube and the main tube are integrated in a monolithic manner, and a high-reliability device structure comprising a cylindrical P-GaN region, double grids and a field plate is adopted; and the chip can be integrated with a phase inverter formed by a GaN device, so that a phase inversion control signal is generated locally, and external driving is simplified. The invention also provides a corresponding preparation method. On the premise that the switching speed is not sacrificed, the ringing problem of the gallium nitride power integrated circuit is effectively solved, and the reliability and the integration degree of the system are remarkably improved.

The application provides an ESD protection circuit and a multi-power integrated circuit, and relates to the technical field of integrated circuits. The ESD protection circuit comprises a first port and a second port, the first port is coupled with a contact pad, and the second port is coupled with a power supply; a plurality of parallel ESD devices, each of which comprises a first sub-port and a second sub-port; all the first sub-ports are coupled with the first port; all the second sub-ports are coupled with the second port; each of the ESD devices comprises a resistor and an OTS element, and the resistor and the OTS element are connected in series; and the ESD protection circuit provides ESD protection for the contact pad. The ESD protection circuit and the multi-power integrated circuit provided by the application have the advantages of reducing the area of the ESD protection circuit and reducing the cost.

A combo circuit with electrostatic discharge protection includes a pulse width modulation integrated circuit and a power integrated circuit. The pulse width modulation integrated circuit has an electrostatic discharge protection circuit and the electrostatic discharge protection circuit is installed between a source of the power integrated circuit and a reference ground potential of the combo circuit.