30 results about "Power integrated circuits" patented technology

The utility model belongs to the technical field of chip packaging, and discloses a high-power integrated circuit chip packaging device which comprises a feeding structure, a machine body, a control unit, a suction unit, a feeding structure and a fixing structure. The feeding structure comprises a tray, a guide part and a transmission part, the guide part is connected to the machine body and used for driving the transmission part to move, the transmission part is connected to the guide part and used for driving the tray to move, the tray is connected to the transmission part and used for bearing chips, and the control unit is connected to the machine body and used for controlling the packaging device to operate. When the chip is packaged, the rack meshed with the gear is moved, so that the end part of the clamping block is attached to the end part of the chip, the chip is fixed on the slide holder, the position deviation of the chip during packaging is effectively avoided, and the packaging quality and the product percent of pass are greatly improved.

The present application relates to a kind of high low side double mechanism fusion's IGBT short circuit protection circuit, it is related to power integrated circuit design technical field, the circuit includes high side desaturation short circuit detection circuit, low side resistance short circuit detection circuit, high side fault processing module, low side fault processing module and two-stage collaborative soft turn-off circuit;The signal output end of high side desaturation short circuit detection circuit is electrically connected to the input end of high side fault processing module and the first trigger input end of two-stage collaborative soft turn-off circuit respectively;The signal output end of low side resistance short circuit detection circuit is electrically connected to the input end of low side fault processing module and the second trigger input end of two-stage collaborative soft turn-off circuit respectively;The output end of high side fault processing module and the output end of low side fault processing module are electrically connected to the control input end of two-stage collaborative soft turn-off circuit;Two-stage collaborative soft turn-off circuit is electrically connected to high side IGBT gate and low side IGBT gate.The effect of considering turn-off speed and peak suppression is realized.

The application provides a three-dimensional integrated power integrated circuit thermal management method and system, relates to the technical field of power integrated circuits, and comprises the following steps: receiving a running index sequence of a target power integrated circuit in a preset monitoring window and performing running state feature analysis; traversing embedded temperature sensors of a chip layer set to collect temperature distribution and identify hot spot regions; combining circuit running working condition features and the hot spot region set to perform thermal management strategy analysis, obtaining a thermal management strategy, and using a plurality of MOSFET switching circuits to adaptively control and manage a plurality of power output branches. The application solves the technical problem that, in the prior art, due to the fact that the power integrated circuit is dominated by long thermal paths and horizontal heat dissipation, local regions are overheated and thermal management response is lagged, thereby affecting the stability of the circuit, and the stability of the power integrated circuit is improved by using a MOSFET switching circuit array to realize thermal sensing power path dynamic scheduling.

Embodiments relate to flip-flops for a low power integrated circuit (IC) in a standard cell library. A master stage flip-flop includes multistage cascaded inverters to generate a buffered data output for providing input to a slave stage flip-flop. A transistor bridge circuit is used for sharing a clock signal between the master stage flip-flop and the slave stage flip-flop. The slave stage flip-flop is configured to generate a final output using the generated buffered output from the master stage flip-flop.

The invention relates to the field of circuit board technology and integrated circuit manufacturing, and particularly discloses a preparation process of a multilayer circuit board with a thermoelectric separation substrate, which comprises the following steps of: preparing and laminating an FR4 multilayer board at one time; and finally, through secondary pressing, the red copper plate boss is accurately embedded into the groove of the FR4 plate and is electrically connected with the circuit bonding pad, so that a thermoelectric separation integrated structure is realized. The method is suitable for packaging and heat dissipation requirements of high-power integrated circuits and semiconductor devices, and particularly can be used for producing high-density and high-heat-dissipation circuit modules in semiconductor device special equipment such as a special photoetching machine and an etching machine. The obtained product has the high-density wiring advantage of the FR4 multilayer board and the high heat dissipation performance of the metal substrate, the lowest thermal resistance path to the heat dissipation substrate is achieved through direct connection of the bosses, meanwhile, the reliability and the electrical insulation performance of the overall structure are guaranteed, the stability of electronic equipment under the high-temperature and high-power working conditions is remarkably improved, and the service life of the electronic equipment under the high-temperature and high-power working conditions is remarkably prolonged.

A low-power lightning current waveform acquisition circuit belongs to the technical field of lightning protection, comprising a protection circuit, an integration circuit, a signal conditioning circuit, a trigger circuit, a microprocessor circuit, a storage circuit, a communication circuit and a power conversion circuit, the protection circuit is electrically connected with a lightning current signal sensor Rogowski coil and the integration circuit respectively, the integration circuit is electrically connected with the signal conditioning circuit and the trigger circuit respectively; the signal conditioning circuit and the trigger circuit are electrically connected with the microprocessor circuit; the storage circuit is electrically connected with the microprocessor circuit; the communication circuit is electrically connected with the microprocessor circuit; the power conversion circuit is electrically connected with the integration circuit, the signal conditioning circuit, the trigger circuit, the microprocessor circuit, the storage circuit and the communication circuit. The low-power function circuit composed of the STM32L471 low-power processor and other low-power integrated circuits realizes the acquisition, storage and transmission of the lightning current waveform.

A high power density integrated circuit module packaging method and its packaging structure belong to the field of microelectronic device packaging technology. In the inner cavity assembly area of the ceramic packaging shell, the chip assembly area is provided with a heat sink area and a functional area, the heat sink area and the functional area are provided as flat bottom pits, the power of the chips in the circuit is graded, a two-stage or more stepped structure is adopted, the chips are distributed from deep flat bottom pits to shallow flat bottom pits according to the power from large to small, the heat sink area is lower than the functional area, the power type chip with large power is assembled in the heat sink area, and the functional type chip with small power is assembled in the functional area. A metal through hole penetrating through the ceramic base body is arranged below the heat sink area or the functional area to realize shortest path heat dissipation and shortest path internal and external electrical connection. The problems of low power density, low integration, large parasitic impedance and parasitic inductance, low reliability and high application cost of the existing high-power devices (assemblies or modules) are solved. It is widely used in the field of high-reliability power integrated circuit module integration technology.

The application relates to a temperature control method, device, equipment and medium for dynamic burn-in of an integrated circuit, wherein the method comprises the following steps: in the process of dynamic burn-in of a to-be-tested integrated circuit, according to a burn-in temperature control strategy, the burn-in temperature of the to-be-tested integrated circuit in the burn-in process is controlled until a preset burn-in time length is reached; wherein the burn-in temperature control strategy comprises the following steps: according to a first temperature value and a target temperature value of the to-be-tested integrated circuit, a first control strategy of the burn-in temperature is determined; according to a second temperature value, a power consumption value and a preset temperature-power consumption mapping relationship model of the to-be-tested integrated circuit, a second control strategy of the burn-in temperature is determined; the second temperature value is a temperature value of the to-be-tested integrated circuit obtained after the first control strategy is adjusted. In this way, the trend of temperature rise or fall of a high-power integrated circuit can be predicted in advance, so that the controller can send a temperature rise or fall control signal in advance, and compared with a traditional method based on temperature regulation and control only, the temperature control precision is higher.

The application provides an adaptive power regulation method and system for a power integrated circuit, and relates to the technical field of power regulation. The method comprises the following steps: dividing the power integrated circuit and outputting multiple power domains; constructing multiple power feature vector sets according to power requirement data of each power domain, performing Gaussian mixture model clustering, and constructing a complementarity matrix based on multiple clustering results; establishing a pairing priority list according to the complementarity matrix, obtaining a complementary power regulator pair based on the pairing priority list; configuring an adaptive power regulator for the complementary power regulator pair, and performing adaptive power regulation on each complementary power regulator pair based on an adaptive power switching regulation logic model. The application can solve the technical problem of poor power regulation stability of the power integrated circuit in the prior art, and achieve the technical effect of improving the power regulation stability.

The invention discloses a high-precision floating power rail circuit, and relates to the technical field of high-voltage power integrated circuits, and the circuit comprises a sampling circuit, an error correction circuit and an adjustment circuit, the sampling circuit is connected between an input high voltage VDD and a floating power rail voltage VF, and is used for sampling the voltage difference between the VDD and the VF, and outputting a sampling signal Vsense; the input end of the error correction circuit is connected to the output end of the sampling circuit and the standard reference voltage Vref, and the error correction circuit is used for comparing the sampling signal Vsense with the standard reference voltage Vref and generating a control signal Vgate according to a comparison result; the control end of the adjusting circuit is connected to the output end of the error correction circuit, the main path of the adjusting circuit is connected between the floating power rail voltage VF and the ground, and the adjusting circuit is used for adjusting the floating power rail voltage VF according to the control signal Vgate, so that the difference between the VDD and the VF is kept at a fixed value, and the high-precision and stable floating power rail voltage can be generated.

This invention discloses a high-precision floating power rail circuit, relating to the field of high-voltage power integrated circuit technology. The circuit includes: a sampling circuit, an error correction circuit, and an adjustment circuit. The sampling circuit is connected between the input high voltage VDD and the floating power rail voltage VF, used to sample the voltage difference between VDD and VF and output a sampling signal Vsense. The error correction circuit has its input connected to the output of the sampling circuit and a reference voltage Vref, used to compare the sampling signal Vsense with the reference voltage Vref, and generate a control signal Vgate based on the comparison result. The adjustment circuit has its control terminal connected to the output of the error correction circuit, and its main path is connected between the floating power rail voltage VF and ground, used to adjust the floating power rail voltage VF according to the control signal Vgate, so that the difference between VDD and VF remains a fixed value, generating a high-precision and stable floating power rail voltage.

The invention provides an epitaxial method for improving crystal point defects on the back surface of an epitaxial wafer, and the method mainly comprises the steps: carrying out the epitaxy through employing Poly and LTO in sequence, and carrying out the epitaxy through employing a perforated graphite disc, and obtaining an 8-inch epitaxial wafer. The epitaxial wafer can be used for a power semiconductor device, a photoelectric semiconductor device, a radio frequency and microwave device and a power integrated circuit. The method has the advantages that the perforated graphite disc is used for epitaxy, reaction gas entering the back of the substrate in the epitaxy process can be discharged to the lower part of the reaction chamber along the holes in the surface of the graphite disc, aggregation reaction on the back of the substrate is greatly reduced, and the crystal point defects on the back of the epitaxial wafer are greatly reduced; besides, in the epitaxy process, HCl gas is introduced into the lower end of the graphite plate, the HCl gas enters the back surface of the substrate through holes of the graphite plate to achieve the effect of etching crystal points on the back surface, and meanwhile, the HCl serving as a by-product in the epitaxy process can also achieve the effects of inhibiting the chemical reaction of SiHCl3 and H2 and reducing the generation of crystal point defects on the back surface.

The invention discloses an LDO circuit with a temperature compensation function for a GaN power integrated circuit. The LDO circuit comprises a reference voltage source, a TRK voltage source and a differential operational amplifier circuit with negative feedback. The reference voltage source is used for generating reference voltage with stable temperature; the input end of the TRK voltage source is connected with the output end of the reference voltage source, and the TRK voltage source is used for generating voltage offset matched with GaN HEMT threshold voltage drift according to temperature changes. And the input end of the differential operational amplifier circuit with negative feedback is connected with the output end of the TRK voltage source and is used for adjusting the voltage of the output end according to the input voltage so as to realize voltage-stabilized output. The circuit is simple in structure, high in temperature compensation precision and suitable for local voltage stabilization power supply of low-voltage bias, driving and control modules in a GaN power chip, and the reliability and the temperature adaptability of a system can be remarkably improved.

A semiconductor package contains a first semiconductor die, electrically coupled to a plurality of leads around a perimeter of the semiconductor package via a molded interconnect. The molded interconnect comprises a plurality of embedded interconnects in a first mold compound which electrically couple the plurality of bond pads of the first semiconductor die to the plurality of leads of the semiconductor package. The molded interconnect may have a greater cross-sectional area at a given pitch compared to a similar wire bonded semiconductor package and allow advantageous thermal management of the semiconductor package compared to other electrical coupling techniques. The molded interconnect may allow small high-power integrated circuits to be packaged with a package footprint which is smaller than would otherwise be available.

The present application belongs to the technical field of power integrated circuit, and particularly relates to a method for establishing and simulating a lateral high-voltage device equivalent circuit model. The circuit model comprises: a field effect transistor; a drain resistance, one end of which is connected to the drain of the field effect transistor and the second end of which is used as the drain of a high-voltage device; a source resistance, one end of which is connected to the source of the field effect transistor and the second end of which is used as the source of a high-voltage transistor; a body diode, which is connected in series with a diode cathode through a parallel network of a cathode resistance and an inductor, the anode of which is connected to the source of the high-voltage transistor, and the other end of the cathode resistance is connected to the drain of the high-voltage device; a first current source, one end of which is connected to the drain of the high-voltage device and the other end of which is connected to the source of the high-voltage device; and a simulation model, which uses a voltage control resistance value relationship to correct the resistance value of an external resistance. Compared with a traditional model, the resistance expression of the present application has a clear physical meaning, effectively improves the simulation accuracy of the lateral high-voltage device model, and has better convergence.

The invention discloses a gallium integrated circuit chip and a preparation method thereof, and belongs to the technical field of semiconductor device integration. The gallium integrated circuit chip comprises a basic circuit module formed by connecting a main pipe device and an auxiliary pipe device, a drain electrode of the auxiliary pipe device is connected with a grid electrode of the main pipe device, and source electrodes of the auxiliary pipe device and the main pipe device are connected together; grid electrodes of the main tube and the auxiliary tube receive inverted input signals; when the main pipe generates grid voltage ringing due to coupling of adjacent circuit switches, the conducted auxiliary pipe provides a discharge path for grid charges of the main pipe, and misconduction is restrained. Preferably, the auxiliary tube and the main tube are integrated in a monolithic manner, and a high-reliability device structure comprising a cylindrical P-GaN region, double grids and a field plate is adopted; and the chip can be integrated with a phase inverter formed by a GaN device, so that a phase inversion control signal is generated locally, and external driving is simplified. The invention also provides a corresponding preparation method. On the premise that the switching speed is not sacrificed, the ringing problem of the gallium nitride power integrated circuit is effectively solved, and the reliability and the integration degree of the system are remarkably improved.

The application provides an ESD protection circuit and a multi-power integrated circuit, and relates to the technical field of integrated circuits. The ESD protection circuit comprises a first port and a second port, the first port is coupled with a contact pad, and the second port is coupled with a power supply; a plurality of parallel ESD devices, each of which comprises a first sub-port and a second sub-port; all the first sub-ports are coupled with the first port; all the second sub-ports are coupled with the second port; each of the ESD devices comprises a resistor and an OTS element, and the resistor and the OTS element are connected in series; and the ESD protection circuit provides ESD protection for the contact pad. The ESD protection circuit and the multi-power integrated circuit provided by the application have the advantages of reducing the area of the ESD protection circuit and reducing the cost.

A combo circuit with electrostatic discharge protection includes a pulse width modulation integrated circuit and a power integrated circuit. The pulse width modulation integrated circuit has an electrostatic discharge protection circuit and the electrostatic discharge protection circuit is installed between a source of the power integrated circuit and a reference ground potential of the combo circuit.

The present disclosure relates to a power supply device and an image display device having same. A power supply device according to an embodiment of the present disclosure comprises: a power integrated circuit which has a first switching element and a second switching element connected in series to each other, and outputs a second direct-current voltage to an output terminal on the basis of a first direct-current voltage input to an input terminal; a first trace electrically connected to the input terminal; and at least one capacitor electrically connected to the first trace, wherein the first trace has a first region to which the capacitor is electrically connected, and a second region arranged for separation between the first region and the input terminal, and the distance between the capacitor and the power integrated circuit is greater than the length of the second region. Accordingly, it is possible to reduce the likelihood of burnout of other circuit elements when the power integrated circuit burns out.

The invention discloses a protection device and method for a power integrated circuit, a motor driving module, a motor and a power supply, and the device comprises a physical thermal current-limiting protection module which is used for sensing the temperature of the power integrated circuit under the condition that the power integrated circuit works, physical thermal current limiting protection is carried out on the working current of the power integrated circuit according to the temperature of the power integrated circuit; and the electronic current-limiting protection module is used for obtaining the working current of the power integrated circuit after the physical thermal current-limiting protection module performs physical thermal current-limiting protection on the working current of the power integrated circuit, and performing electronic current-limiting protection on the power integrated circuit according to the working current of the power integrated circuit. And dual protection of physical thermal current limiting and electronic current limiting of the power integration module is realized. According to the scheme, the physical thermal current-limiting protection module is arranged on the periphery of the power integrated circuit to form double cooperative protection with the electronic current-limiting protection module in the power integrated circuit, so that the safety of the power integrated circuit is improved.

A power integrated circuit, the power integrated circuit comprising: a gallium nitride (GaN) chip having a heterojunction structure, the GaN chip having at least one GaN layer and at least one aluminum gallium nitride (AlGaN) layer, the GaN chip having at least one main power device having a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas (2DEG) formed at an interface between the AlGaN layer and the GaN layer and formed between the source terminal and the drain terminal, the gate terminal being configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal; and a driver having at least one low-side component and at least one high-side component, the low-side component being configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal. a low-side component having a terminal connected to a low DC voltage rail and at least one other terminal connected to a gate terminal of the main power device, and a high-side component having at least one terminal connected to a high DC voltage rail and at least one other terminal connected to the gate of the main power device, wherein at least one low-side component of the driver is configured to discharge an input capacitance of the main power device during turn-off of the main power device and is monolithically integrated within the GaN chip, and at least one high-side component of the driver is configured to charge an input capacitance of the main power device and is formed in a semiconductor region including a material other than GaN.

The present disclosure relates to a display device, and more specifically, to a display device in which noise characteristics are improved by outputting mutually inverted switching signals from a first power integrated circuit (IC) and a second power IC. According to the present disclosure, the noise characteristics of the display device are improved by outputting the mutually inverted switching signals from the first power IC and the second power IC.

This invention discloses and provides a compact electronic hardware testing device, enabling universal testing of different project boards and devices, significantly reducing the design workload and error probability of dedicated test boards, and shortening debugging time. The invention includes at least one functional box and a power control box, wherein the power control box provides power to the functional box. The functional box is used for electronic hardware testing. The functional box includes a housing and an integrated module disposed within the housing. The integrated module includes an FPGA control module, a power integrated circuit, an audio output measurement circuit, a channel switching circuit, a ripple measurement circuit, a GPIO control circuit, and an AC / DC voltage measurement circuit. This invention applies to the technical field of electronic hardware testing.

The present application relates to a kind of high low side double mechanism fusion's IGBT short circuit protection circuit, it is related to power integrated circuit design technical field, the circuit includes high side desaturation short circuit detection circuit, low side resistance short circuit detection circuit, high side fault processing module, low side fault processing module and two-stage collaborative soft turn-off circuit;The signal output end of high side desaturation short circuit detection circuit is electrically connected to the input end of high side fault processing module and the first trigger input end of two-stage collaborative soft turn-off circuit respectively;The signal output end of low side resistance short circuit detection circuit is electrically connected to the input end of low side fault processing module and the second trigger input end of two-stage collaborative soft turn-off circuit respectively;The output end of high side fault processing module and the output end of low side fault processing module are electrically connected to the control input end of two-stage collaborative soft turn-off circuit;Two-stage collaborative soft turn-off circuit is electrically connected to high side IGBT gate and low side IGBT gate.The effect of considering turn-off speed and peak suppression is realized.

A semiconductor package (100) contains a first semiconductor die (110), electrically coupled to a plurality of leads (106) around a perimeter of the semiconductor package (100) via a molded interconnect (116). The molded interconnect (116) comprises a plurality of embedded interconnects (118) in a first mold compound (140) which electrically couple a plurality of bond pads (114) of the first semiconductor die (110) to the plurality of leads (106) of the semiconductor package (100). The molded interconnect (116) may have a greater cross-sectional area at a given pitch compared to a similar wire bonded semiconductor package and allow advantageous thermal management of the semiconductor package (100) compared to other electrical coupling techniques. The molded interconnect (116) may allow small high-power integrated circuits to be packaged with a package footprint which is smaller than would otherwise be available.

This invention belongs to the field of alloy casting technology and relates to a lightweight, low-thermal-expansion, high-thermal-conductivity magnesium-copper alloy material. The magnesium-copper alloy material comprises, by weight percentage, the following components: Cu 25-30%, with the balance being Mg. This invention also discloses a method for preparing the magnesium alloy, including: alloy raw material batching and pretreatment, melting and alloying, settling and casting, and aging treatment to obtain the magnesium-copper alloy material. The magnesium-copper alloy material of this invention overcomes the problem in the prior art of simultaneously improving the strength, thermal conductivity, and dimensional stability of magnesium alloys, possessing high thermal conductivity, low coefficient of thermal expansion, and low density. It is particularly suitable for the preparation of material components requiring efficient heat dissipation, dimensional stability, and lightweight design, such as LED lighting heat dissipation substrates, high-power integrated circuit packaging and heat dissipation housings, satellite optical instrument brackets, and / or aerospace precision structural components, and has enormous application prospects.

The invention discloses an external resistor linear adjustable dead zone generation circuit, and belongs to the technical field of power electronics and power integrated circuits. The circuit comprises a reference voltage generation circuit, a charging current generation circuit, a comparison circuit and a logic control circuit. The reference voltage generating circuit is connected with an enabling end and generates reference voltage by using an external resistor; the charging current generating circuit is connected with an input signal and generates charging current related to reference voltage to charge the capacitor; the comparison circuit compares the capacitor voltage with the reference voltage and outputs a dead time control signal; the logic control circuit controls on-off of the charging current according to the input signal and the control signal and resets the capacitor voltage after the dead zone ends. Accurate linear adjustment of the dead time is achieved through the external resistor, the dead time meets the relation tDT = RDT * C * K, and the circuit has the advantages of being simple, low in cost, wide in adjustable range, small in temperature influence and the like and can be widely applied to half-bridge or full-bridge power drive circuits.

The invention discloses a sub-1 nanometer gate length carbon nanotube ring gate field effect transistor, which is characterized in that a single-wall semiconductor carbon nanotube is used as a channel, single-layer or multi-layer graphene is used as a gate material, and graphene is reserved on a dielectric step in an under-coverage area through graphical angle etching, so that a full-surrounding gate with atomic-scale thickness is formed; and the physical gate length is broken through to sub-1 nanometer scale. And the gate dielectric layer and the under-coverage region dielectric layer cooperatively form a three-dimensional electric field regulation and control structure, so that the static control capability of the gate on the channel is enhanced, and the short-channel effect is effectively inhibited. The preparation process is combined with a material transfer and selective etching technology, and after a medium is deposited on the surface of the suspended carbon nanotube in a shape-preserving manner, the graphene grid electrode is accurately positioned by utilizing the side wall of the step, so that a self-aligned ring grid configuration is formed. The invention provides a high-scalability and low-complexity device solution for sub-1 nanotechnology nodes, and is suitable for manufacturing of a next-generation high-density and low-power-consumption integrated circuit.

The invention belongs to the technical field of power semiconductors, and relates to a GaN-based P-type field effect transistor and an integration method thereof. A semiconductor function layer of the transistor sequentially comprises a low-resistance P-type GaN layer, a high-resistance GaN body region, a polarization electric field layer and a GaN electron collection layer from the surface to the bottom, a medium groove penetrates through the low-resistance P-type GaN layer to form a groove gate structure, and the medium groove is composed of an insulating medium layer located on the inner wall of the groove and a conductive material surrounded by the insulating medium layer. A gate electrode is led out from the conductive material in the medium groove, and a drain electrode and a source electrode are led out through ohmic contact. According to the transistor, the heterojunction tunneling effect is achieved through the polarized electric field layer, the current density and the switch ratio are remarkably improved, and the sub-threshold swing and the static power consumption are reduced. The structure can be integrated with an existing n-type GaN device in a monolithic mode to form a GaN-based complementary logic circuit, the problems that in the prior art, a p-type device is insufficient in performance and difficult to integrate are solved, and the GaN-based complementary logic circuit is suitable for an efficient power integrated circuit and an ultra-low power consumption electronic system.