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374 results about "Spiral inductor" patented technology

Spiral inductor. Spiral inductors, as well as transformers, are often used in RF circuits. The goal in simulations is to find their inductance (L) and quality factor (Q). Spiral inductors have many parasitic elements, including parallel capacitances.

System and method for linearizing a CMOS differential pair

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.
Owner:AVAGO TECH INT SALES PTE LTD

Semiconductor device with a spiral inductor

A first semiconductor device includes a first conductive layer, a second conductive layer located above or below the first conductive layer, and an insulating layer interposed between the first conductive layer and the second conductive layer, a spiral inductor having a spiral pattern that is formed in the first conductive layer, and an electromagnetic wave shield formed in a plane shape in the second conductive layer. The electromagnetic wave shield is grounded or connected to a constant voltage source and is located above or below the spiral inductor. Furthermore the first semiconductor device includes an opening formed in the electromagnetic wave shield. The opening is located in a region corresponding to a region above or below a central region of the spiral pattern of the spiral inductor. A second semiconductor device includes a first conductive layer, a second conductive layer located above or below the first conductive layer, an insulating layer interposed between the first conductive layer and the second conductive layer, a spiral inductor having a spiral pattern that is formed in the first conductive layer, and an electromagnetic wave shield formed in a plane shape in the second conductive layer. The electromagnetic wave shield is grounded or connected to a constant voltage source and is located above or below the spiral inductor. Furthermore the second semiconductor includes a slit formed in the electromagnetic wave shield. The slit extends from a position of the electromagnetic wave shield, the position corresponding to a region above or below a center of the spiral inductor, to a peripheral direction of the electromagnetic wave shield.
Owner:KK TOSHIBA

Integrated spiral inductor

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors with shields to increase circuit Q. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
Owner:AVAGO TECH INT SALES PTE LTD

System and method for ESD protection

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
Owner:AVAGO TECH WIRELESS IP SINGAPORE PTE
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